CN118626421A

CN118626421A - Front-end circuit of processor, board card device and electronic equipment

Info

Publication number: CN118626421A
Application number: CN202411080296.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shanghai Bi Ren Technology Co ltd; Beijing Bilin Technology Development Co ltd
Current assignee: Shanghai Bi Ren Technology Co ltd; Beijing Bilin Technology Development Co ltd
Priority date: 2024-08-08
Filing date: 2024-08-08
Publication date: 2024-09-10

Abstract

The application relates to a front-end circuit of a processor, a board card device and an electronic device. Based on the application, the front-end circuit of the processor can comprise a programmable automatic polling module, the programmable automatic polling module can replace a chip management module to drive a serial bus controller, the programmable automatic polling module can also store the acquired power state sampling data, and the chip management module can periodically acquire at least two target sampling data in the power state sampling data from the programmable automatic polling module in the power consumption frequency dynamic management process. The chip management module obtains at least two target sampling data based on the on-chip access of the processor, and the time-consuming time of the on-chip access is far less than that of the access operation based on the serial bus, so that the management performance of dynamic management of the power consumption frequency is improved.

Description

Front-end circuit of processor, board card device and electronic equipment

Technical Field

The present application relates to dynamic management technology of power consumption frequency, and more particularly, to a front-end circuit of a processor, a board device, and an electronic device.

Background

Power consumption frequency dynamic management (Dynamic Voltage and Frequency Scaling, DVFS) is a processor technology for balancing performance and power consumption by adjusting the voltage and operating frequency of the processor.

In a front-end circuit of a processor supporting dynamic management of power consumption frequency, a chip management module may be included, a board card where the processor is located may be provided with a power supply sampling component for sampling various power supply states, power supply state sampling data obtained by sampling the power supply sampling component may include at least two kinds of target sampling data respectively used for characterizing different power supply states, and the chip management module may implement dynamic management of power consumption frequency for the processor according to the power supply state sampling data periodically obtained from the power supply sampling component.

In general, the chip management module needs to drive the serial bus controller to perform a serial bus-based access operation on the power supply sampling assembly, and acquire at least two kinds of target sampling data among the power supply state sampling data one by one from the power supply sampling assembly through a plurality of times of the serial bus-based access operation. Since the access operation through the serial bus takes a long time, the chip management module frequently generates a long interrupt waiting for completion of the access operation due to acquisition of the power state sampling data during the period of implementing the power consumption frequency dynamic management on the processor. Therefore, the long interruption frequently occurring in the power consumption frequency dynamic management process may cause the management performance of the power consumption frequency dynamic management to be not high.

As can be seen from the above, how to improve the management performance of dynamic management of power consumption frequency becomes a technical problem to be solved in the related art.

Disclosure of Invention

The embodiment of the application provides a front-end circuit of a processor, the processor, a board card device and electronic equipment, which are beneficial to improving the management performance of dynamic management of power consumption frequency.

In one embodiment of the application, there is provided a front-end circuit of a processor, comprising:

The chip management module is used for realizing dynamic management of the power consumption frequency of the processor according to the periodically acquired power state sampling data, wherein the power state sampling data comprises at least two target sampling data;

The serial bus controller is used for connecting a power supply sampling assembly through a serial bus, wherein the power supply sampling assembly is used for sampling at least two target sampling data;

The programmable automatic polling module is used for driving the serial bus controller to poll and acquire at least two target sampling data from the power supply sampling component and storing the at least two target sampling data acquired by polling;

wherein the periodic acquisition of the power state sampling data by the chip management module is configured to: at least two target sampling data stored by the programmable automatic polling module are periodically acquired through on-chip access inside the processor.

In some examples, optionally, the driving of the serial bus controller by the programmable autopolling module is configured by the chip management module, and the at least two target sample data that are polled for are determined based on the configuration of the programmable autopolling module by the chip management module.

In some examples, optionally, the programmable auto-poll module is further configured to save a set of operating instructions generated by the chip management module; the programmable auto-poll module is configured to: and sequentially sending a plurality of access operation instructions to the serial bus controller through polling a plurality of access operation instructions in the operation instruction set, so that the serial bus controller executes access operation for polling to acquire at least two target sampling data on the power supply sampling assembly according to the sequentially received access operation instructions.

In some examples, optionally, the access destination address of the access operation instruction includes a device bus address of any one of the power sampling devices in the power sampling assembly, and the device bus addresses included in the access destination addresses of the plurality of access operation instructions are not identical, so that the access operation polls to acquire at least two of the target sampling data from different ones of the power sampling devices in the power sampling assembly by switching between the different ones of the power sampling devices.

In some examples, optionally, the plurality of access operation instructions includes a write operation instruction having an access operation type of a write operation for writing sample configuration data associated with the target sample data to any one of the power sampling devices of the power sampling assembly, the sample configuration data provided by the chip management module, and a read operation instruction having an access operation type of a read operation for reading the target sample data from any one of the power sampling devices of the power sampling assembly.

In some examples, optionally, each of the plurality of access operation instructions includes a data transfer length, and the data transfer length is used to indicate the length of data transferred using the serial bus during a single access operation of the serial bus controller in response to any one of the access operation instructions.

In some examples, optionally, the polling access by the programmable autonomous polling module to a plurality of the access operation instructions is configured to: transmitting the access operation instruction which is successfully polled to the serial bus controller in response to the access operation instruction which is successfully polled and the current state of the serial bus controller being available; and responding to the serial bus controller to finish the access operation corresponding to one currently received access operation instruction, and polling the next access operation instruction.

In some examples, optionally, the programmable autonomous polling module includes a register set, and the register set is configured to store a plurality of access operation instructions written by the chip management module, and at least two of the target sample data acquired by the serial bus controller through the access operation poll; the programmable auto-poll module further includes an auto-poll controller, and the auto-poll controller is to: sequentially transmitting a plurality of access operation instructions stored in the register set to the serial bus controller through polling access to the register set; and writing at least two target sample data acquired by the serial bus controller through the access operation polling into the register set; wherein the periodic acquisition of the power state sampling data by the chip management module is configured to: and periodically acquiring at least two target sampling data stored in the register set through the on-chip access.

In some examples, optionally, the registers in the register set are MMIO registers.

In some examples, optionally, the register set includes an instruction register set in which a plurality of the access operation instructions are held, and a data register set in which at least two of the target sample data are held.

In some examples, optionally, the polling access of the set of registers by the auto-polling controller is controlled by a finite state machine, and the polling access of the set of registers by the auto-polling controller is controlled based on state switching of the finite state machine to: transmitting the access operation instruction of the current polling position in the register set to the serial bus controller in response to the successful inquiry of the access operation instruction of the current polling position in the register set and the availability of the current state of the serial bus controller; and in response to the serial bus controller completing the access operation corresponding to the currently received access operation instruction, updating the current polling position in the register group according to the address offset used when the chip management module writes a plurality of access operation instructions in the register group.

In some examples, optionally, the finite state machine includes the following states: an idle state, a bus check state, a destination address configuration state, an operation control state, and an operation waiting state; when the finite state machine is in the idle state, the auto-poll controller queries the access operation instruction at a current poll location in the register set, and, in response to a successful query of the access operation instruction at the current poll location in the register set, the finite state machine transitions from the idle state to the bus check state; when the finite state machine is in the bus check state, the auto-poll controller checks whether a current state of the serial bus controller is available and whether an access destination address of the serial bus controller needs to be updated, and, in response to the current state of the serial bus controller being available and the access destination address not needing to be updated, the finite state machine transitions from the bus check state to the operation control state, or in response to the current state of the serial bus controller being available and the access destination address needing to be updated, the finite state machine transitions from the bus check state to the destination address configuration state; when the finite state machine is in the destination address configuration state, the automatic polling controller updates an access destination address of the serial bus controller according to the access operation instruction successfully queried at a current polling position, and the finite state machine is migrated from the destination address configuration state to the operation control state in response to completion of updating of the access destination address; when the finite state machine is in the operation control state, the automatic polling controller triggers the serial bus controller to execute the access operation corresponding to the access operation instruction successfully inquired at the current polling position, and the finite state machine is migrated from the operation control state to the operation waiting state in response to the completion of triggering the access operation; when the finite state machine is in the operation waiting state, the automatic polling controller waits for the serial bus controller to finish the access operation corresponding to the access operation instruction successfully inquired at the current polling position, and in response to the execution of the access operation being finished, the finite state machine transits from the operation waiting state to the idle state and triggers the updating of the current polling position in the register group.

In some examples, optionally, the automatic polling controller checking whether the current state of the serial bus controller is available comprises: checking whether the current working state of the serial bus controller is idle or not and whether a controller cache of the serial bus controller is empty or not, wherein if the current working state of the serial bus controller is idle and the controller cache is empty, the current state of the serial bus controller is available, otherwise, the current state of the serial bus controller is unavailable.

In some examples, optionally, the access destination address of the access operation instruction includes a device bus address of any one of the power sampling apparatuses in the power sampling assembly, the device bus addresses included in the access destination addresses of the access operation instructions are not identical, and the checking by the autopolling controller whether the access destination address of the serial bus controller needs to be updated includes: checking whether the device bus address indicated by the access operation instruction is queried at the current polling position in the register group and the device bus address included in the access destination address when the serial bus controller executes the access operation last time are the same, wherein if so, the device bus address is not required to be updated, otherwise, the device bus address is required to be updated.

In some examples, optionally, the plurality of access operation instructions includes a write operation instruction of an access operation type of a write operation for writing sample configuration data associated with the target sample data to any one of the power supply sampling devices of the power supply sampling assembly, and a read operation instruction of an access operation type of a read operation for reading the target sample data from any one of the power supply sampling devices of the power supply sampling assembly; the operation control states include a write operation control state and a read operation control state, and the operation waiting state includes a write operation waiting state and a read operation waiting state; when the finite state machine is in the bus checking state or the destination address configuration state, selectively migrating to the write operation control state or the read operation control state according to the access operation type of the access operation instruction queried at the current polling position in the register group; when the finite state machine is in the writing operation control state, the automatic polling controller triggers the serial bus controller to execute writing operation corresponding to the access operation instruction successfully inquired at the current polling position and writes the sampling configuration data into a controller cache of the serial bus controller, and the finite state machine is migrated from the writing operation control state to the writing operation waiting state in response to completion of triggering the writing operation; when the finite state machine is in the write operation waiting state, the auto-polling controller waits for the serial bus controller to complete writing of the sampling configuration data, and in response to the writing of the sampling configuration data being completed, the finite state machine transitions from the write operation waiting state to the idle state and triggers updating of a current polling position in the register set; when the finite state machine is in the read operation control state, the automatic polling controller triggers the serial bus controller to execute the read operation corresponding to the access operation instruction successfully inquired at the current polling position, and the finite state machine is migrated from the read operation control state to the read operation waiting state in response to the completion of triggering the read operation; when the finite state machine is in the read operation waiting state, the auto-polling controller waits for the serial bus controller to complete the read operation of the target sample data, and, in response to the completion of the read operation of the target sample data, the auto-polling controller writes the target sample data held in a controller cache of the serial bus controller into the register component, and the finite state machine transitions from the read operation waiting state to the idle state and triggers an update of a current polling position in the register group.

In another embodiment of the application, a processor is provided that includes a front-end circuit as described in the previous embodiments.

In another embodiment of the present application, a board card apparatus is provided, including a circuit board, a processor as described in the previous embodiment, and the power supply sampling assembly, and the processor and the power supply sampling assembly are both disposed on the circuit board.

In another embodiment of the present application, an electronic device is provided, including the board card device as described in the foregoing embodiment.

Based on the above embodiment of the present application, the front-end circuit of the processor may include a programmable auto-poll module, which may drive the serial bus controller instead of the chip management module, and the programmable auto-poll module may also store the acquired power state sampling data, and the chip management module may periodically acquire at least two target sampling data from the programmable auto-poll module in the power frequency dynamic management process. Because the chip management module obtains at least two target sampling data based on the on-chip access of the processor, and the time-consuming time of the on-chip access is far less than that of the serial bus-based access operation, the interrupt time caused by the chip management module obtaining the power state sampling data can be greatly reduced, and therefore the management performance of the dynamic management of the power consumption frequency is improved.

Drawings

The following drawings are only illustrative of the application and do not limit the scope of the application:

FIG. 1 is a schematic diagram of an exemplary architecture of a front-end circuit of a processor in an embodiment of the application;

FIG. 2 is a schematic diagram of an exemplary architecture of a programmable auto-poll module of a front-end circuit in an embodiment of the application;

FIG. 3 is a schematic diagram of a front-end circuit according to an embodiment of the present application for acquiring power status sampling data;

FIG. 4 is a timing diagram of a front-end circuit acquiring power state sampling data according to an embodiment of the present application;

FIG. 5 is a timing diagram of a comparison example for acquiring power state sampling data;

FIG. 6 is a schematic diagram of a configuration of a programmable auto-poll module of a front-end circuit according to an embodiment of the present application;

fig. 7 is a state transition schematic diagram of a finite state machine maintained by a programmable auto-poll module of a front-end circuit in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below by referring to the accompanying drawings and examples.

Fig. 1 is a schematic diagram of an exemplary architecture of a front-end circuit of a processor in an embodiment of the application. Referring to fig. 1, in an embodiment of the present application, front-end circuitry 95 of processor 90 may include a chip management module 10, a serial bus controller 20, and a programmable auto-poll module (Programmable Auto Polling Module, PAPM) 30.

In an embodiment of the present application, the chip management module 10 may include an MPU (Micro-Processing Unit) in the front-end circuit 95, and the chip management module 10 may be configured to implement dynamic management on the power consumption frequency of the processor 90 according to periodically acquired power state sampling Data, where the power state sampling Data may include at least two target sampling Data data_1 to data_n, and n is a positive integer greater than or equal to 2.

Illustratively, in an embodiment of the present application, at least two target sampling Data data_1 to data—n in the power state sampling Data may include, but are not limited to, at least two of the following: at least one of Power state sampling data, current state sampling data, voltage state sampling data, and temperature state sampling data of a Board Power supply (Board Power), at least one of Power state sampling data, current state sampling data, voltage state sampling data, and temperature state sampling data of a Power supply rail (Power rail), and Power state sampling data and temperature state sampling data of a high Power consumption element such as a virtual machine (Virtualization Machine, VM) core processor, and the like.

In an embodiment of the present application, the serial bus controller 20 may support any kind of bus for Data transmission based on a serial protocol, such as I2C (Inter-INTEGRATED CIRCUIT, integrated circuit bus), and the serial bus controller (e.g., I2C bus controller) 20 may be used to connect the power sampling component 50 through the serial bus (e.g., I2C bus), where the power sampling component 50 is located outside the chip of the processor 90, the power sampling component 50 may include at least one power sampling device disposed at a pre-selected sampling position in a board device where the processor 90 is located, and the power sampling component 50 (i.e., at least one power sampling device) may be used to sample at least two target sampling Data data_1 to data_n in the power status sampling Data.

Illustratively, in an embodiment of the present application, the Power sampling component 50 may include at least one of a Power Sensor (Power Sensor), a temperature Sensor (Temperature Sensing, TS), and a PMIC (Power MANAGEMENT INTEGRATED Circuit). Wherein the sampling object of the power sensor may include sampling data related to at least one of power consumption, current, and voltage, and the target sampling data obtained by sampling by the power sensor may include at least one of power consumption state sampling data, current state sampling data, and voltage state sampling data; the sampling object of the temperature sensor may include sampling data related to temperature, and the target sampling data obtained by sampling the temperature sensor may include temperature state sampling data; the sampling object of the PMIC may include sampling data related to at least one of power consumption, current, voltage, and temperature, and the target sampling data obtained by sampling by the PMIC may include at least one of power consumption state sampling data, current state sampling data, voltage state sampling data, and temperature state sampling data.

That is, in the embodiment of the present application, various status sampling Data (i.e., at least two target sampling Data data_1 to data_n) corresponding to the board-level power supply, the power supply rail and the high power consumption element in the power status sampling Data can be obtained by sampling at least one of the power supply sensor, the temperature sensor and the PMIC, which is not necessarily limited in the embodiment of the present application. It will be appreciated that the above illustration is merely intended to embody a diverse selection of power sampling assemblies 50 and is not intended to limit the specific composition of power sampling assemblies 50.

In an embodiment of the present application, the programmable automatic polling module 30 may be provided in the front-end circuit 95 by way of hardware programming, and the programmable automatic polling module 30 may be configured to:

the serial bus controller 20 is driven to acquire at least two target sampling Data data_1 to data_n in a polling manner from the power sampling component 50, that is, at least two target sampling Data data_1 to data_n acquired by sampling by the power sampling component 50 in a polling manner; and

The save serial bus controller 20 polls the at least two target sampled Data data_1 to data—n acquired from the power sampling component 50, that is, the at least two target sampled Data data_1 to data—n acquired by the power sampling component 50 may be saved in the programmable automatic polling module 30.

That is, in an embodiment of the present application, the programmable autonomous polling module 30 may be located between the chip management module 10 and the serial bus controller 20, and the programmable autonomous polling module 30 may drive the serial bus controller 20 instead of the chip management module 10.

Fig. 2 is a schematic diagram of an exemplary configuration of a programmable auto-poll module of a front-end circuit in an embodiment of the application. As shown in fig. 2, in an exemplary embodiment of the present application, the programmable auto-poll module 30 may include a register set 31 and an auto-poll controller (Auto Polling Controller) 32. The auto-polling controller 32 may be configured to drive the serial bus controller 20 to poll and acquire at least two target sampling Data data_1 to data_n from the power sampling component 50, and write the at least two target sampling Data data_1 to data_n acquired by polling the serial bus controller 20 into the register set 31; the register set 31 may be used to store at least two target sample Data data_1 to data—n obtained by polling by the serial bus controller 20.

Illustratively, the register set 31 may include MMIO (Memory-Mapped I/O, memory mapped input/output) registers, i.e., the registers in the register set 31 may be MMIO registers, the access addresses of the MMIO registers may be mapped in the Memory address space of the chip management module 10, and thus, the chip management module 10 reads and writes MMIO registers (i.e., the register set 31 of the i.e., auto-poll module 30) in a Memory-to-Memory manner to avoid I/O interrupts generated by accessing the MMIO registers (i.e., the register set 31 of the i.e., auto-poll module 30).

Illustratively, in an embodiment of the present application, the programmable automatic polling module 30 drives the polling process of the serial bus controller 20 for at least two target sampling Data data_1 to data—n, which may be continuous polling, for example, continuous polling during the period that the programmable automatic polling module 30 is enabled by the chip management module 10. That is, the programmable autopolling module 30 can drive the serial bus controller 20 to poll and acquire at least two target sampling Data data_1 to data_n cyclically (for example, cyclically during the period that the programmable autopolling module 30 is enabled by the chip management module 10).

In this case, after the programmable autopolling module 30 (e.g., the autopolling controller 32) drives the serial bus controller 20 to poll and acquire at least two target sample Data data_1 to data—n for the first time, the programmable autopolling module 30 may start to save (e.g., save continuously in the register set 31) at least two target sample Data data_1 to data—n continuously, and any one of the target sample data_i acquired for each subsequent poll after the first time may be used to update and replace the target sample Data data_i saved in the programmable autopolling module 30 (e.g., the register set 31).

Thus, the process of the programmable autopolling module 30 (e.g., the autopolling controller 32) driving the serial bus controller 20 to continuously or circularly poll and acquire at least two target sampling Data data_1 to data_n can be regarded as a process of continuously updating at least two target sampling Data data_1 to data_n stored in the programmable autopolling module 30 (e.g., the register set 31) according to the polling order. That is, at least two target sample Data data_1 to data—n can be continuously stored in the programmable automatic polling module 30 (e.g., the register set 31) after the first polling, and each of the at least two target sample Data data_1 to data—n stored in the programmable automatic polling module 30 (e.g., the register set 31) can be dynamically updated in the subsequent polling process according to the polling cycle frequency.

Illustratively, in embodiments of the present application, the programmable auto-poll module 30 (e.g., auto-poll controller 32) drives the first poll of the serial bus controller 20, preferably prior to the chip management module 10 initiating dynamic management of the power consumption frequency of the processor 90, e.g., the chip management module 10 may enable the programmable auto-poll module 30 prior to initiating dynamic management of the power consumption frequency of the processor 90.

Fig. 3 is a schematic diagram of a front-end circuit according to an embodiment of the present application for acquiring power status sampling data. Referring to the drawings, in the embodiment of the present application, since the programmable automatic polling module 30 can continuously store at least two target sampling Data data_1 to data_n that are continuously and dynamically updated by polling, the chip management module 10 can be configured to periodically acquire the power status sampling Data (i.e. at least two target sampling Data data_1 to data_n) during the period of implementing the power consumption frequency dynamic management on the processor 90: at least two target sample Data data_1 to data—n stored by the programmable auto-poll module 30 (e.g., the register set 31) are periodically acquired through on-chip access inside the processor.

Illustratively, in the embodiment of the present application, the process of periodically acquiring at least two target sample Data data_1 to data—n from the programmable autopolling module 30 (for example, the register set 31) by the chip management module 10 may be periodically polling to acquire at least two target sample Data data_1 to data—n stored in the programmable autopolling module 30 (for example, the register set 31), or may also be periodically concurrently acquiring at least two target sample Data data_1 to data—n stored in the programmable autopolling module 30 (for example, the register set 31).

Fig. 4 is a timing diagram of a front-end circuit acquiring power state sampling data according to an embodiment of the present application. Fig. 5 is a timing diagram for acquiring power state sampling data in a comparative example. In fig. 4, with an arrow labeled "data_i" between the programmable automatic polling module 30 and the chip management module 10, the generalization indicates that the chip management module 10 periodically acquires at least two target sampling Data data_1 to data_n from the programmable automatic polling module 30 (e.g. the register set 31) in a polling manner or a concurrent manner; in the comparative example shown in fig. 5, the front-end circuit does not include the programmable automatic polling module 30 according to the embodiment of the present application, and the chip management module 10 is configured to drive the serial bus controller.

As is clear from comparing fig. 4 and fig. 5, whether the chip management module 10 periodically acquires at least two target sampling Data data_1 to data—n from the programmable auto-poll module 30 (e.g., the register set 31) in a polling manner or in a concurrent manner, the acquisition of at least two target sampling Data data_1 to data—n by the chip management module 10 is realized based on the on-chip access inside the processor 90, and since the time-consuming period of the on-chip access inside the processor 90 is much less than that of the execution of the serial bus-based access operation by driving the serial bus controller 20, the long interrupt t_int caused by waiting for the serial bus-based access operation in fig. 5 does not occur when the chip management module 10 acquires the power state sampling Data, i.e., the interrupt time period caused by the acquisition of the power state sampling Data by the chip management module 10 can be greatly reduced or even completely eliminated (e.g., when the register set 31 of the programmable auto-poll module 30 is selected to use an MMIO register), thereby facilitating the dynamic frequency management of the performance.

As can be seen from comparing fig. 4 and 5, in the embodiment of the present application, since at least two target sampling Data data_1 to data_n in the programmable automatic polling module 30 are continuously stored, the chip management module 10 obtains the first cycle frequency f1 of the power status sampling Data (i.e. the at least two target sampling Data data_1 to data_n), and may not be limited to the second cycle frequency f2 of the programmable automatic polling module 30 driving the serial bus controller 20 to perform polling, where f2 is equal to 1/t_poll, and t_poll represents one polling cycle duration of polling to obtain the at least two target sampling Data data_1 to data_n by driving the serial bus controller 20 to perform the serial bus based access operation. Therefore, according to the embodiment of the present application, the chip management module 10 obtains the first cycle frequency f1 of the power status sampling Data (i.e. the at least two target sampling Data data_1 to data—n), which can be allowed to be higher than the second cycle frequency f2 of the driving serial bus controller 20 to perform polling, thereby being more beneficial to improving the management performance of the dynamic management of the power consumption frequency.

In the embodiment of the present application, as described above, the types of the power sampling devices included in the power sampling assembly 50 may be diversified, and the number and types of the at least two target sampling Data data_1 to data_n may also be set according to different requirements of the power consumption frequency dynamic management, so, in order to enable the embodiment of the present application to improve compatibility of the differential configuration of the power sampling assembly 50 and adaptation of the at least two target sampling Data data_1 to data_n to different requirements of the power consumption frequency dynamic management, the driving of the serial bus controller 20 by the programmable auto-poll module 30 (e.g., the auto-poll controller 32) may be configured by the chip management module 10, and the at least two target sampling Data data_1 to data_n obtained by polling may be determined based on the configuration of the chip management module 10 to the programmable auto-poll module 30 (e.g., the auto-poll controller 32).

In the embodiment of the present application, the configuration of the programmable autopolling module 30 by the chip management module 10 may be implemented by the chip management module 10 generating the operation instruction set for driving the serial bus controller 20 by itself and issuing the operation instruction set to the programmable autopolling module 30. In this case, the programmable auto-poll module 30 (e.g. register set 31) is also used to save the set of operating instructions generated by the chip management module 10; also, the programmable auto-poll module 30 (e.g., auto-poll controller 32) may be specifically configured to: the plurality of access operation instructions cmd_1 to cmd_m are sequentially transmitted to the serial bus controller 20 by polling a plurality of access operation instructions cmd_1 to cmd_m in the operation instruction set stored (for example, stored in the register group 31), so that the serial bus controller 20 performs an access operation for polling to acquire at least two target sampling Data data_1 to data_n on the power supply sampling component 50 according to the plurality of access operation instructions cmd_1 to cmd_m sequentially received, m being a positive integer greater than or equal to 2.

Illustratively, in the embodiment of the present application, if the programmable autopolling module 30 is configured by the chip management module 10, and the programmable autopolling module 30 includes the register set 31 and the autopolling controller 32, the register set 31 is used to save at least two target sampling Data data_1 to data_n acquired by the serial bus controller 20 through the access operation poll, and may also save a plurality of access operation instructions cmd_1 to cmd_m written by the chip management module 10.

Fig. 6 is a schematic diagram of a configuration principle of a programmable auto-polling module of a front-end circuit in an embodiment of the application. Referring to fig. 6, in the embodiment of the present application, if the register set 31 needs to store at least two target sampling Data data_1 to data_n obtained by the serial bus controller 20 through the access operation poll and a plurality of access operation instructions cmd_1 to cmd_m written by the chip management module 10, the register set 31 may include the instruction register set 311 and the Data register set 312, the plurality of access operation instructions cmd_1 to cmd_m written by the chip management module 10 may be stored in the instruction register set 311, and the at least two target sampling Data data_1 to data_n obtained by the serial bus controller 20 through the access operation poll may be stored in the Data register set 312.

Illustratively, in embodiments of the present application, if the programmable auto-poll module 30 is configured by the chip management module 10, and the programmable auto-poll module 30 includes a register set 31 and an auto-poll controller 32, the auto-poll controller 32 may be specifically configured by hardware programming to: the multiple access operation instructions cmd_1 to cmd_m stored in the register group 31 are sequentially transmitted to the serial bus controller 20 through polling access to the register group 31, and at least two target sample Data data_1 to data—n acquired by the serial bus controller 20 through the access operation polling are written into the register group 31.

Illustratively, in an embodiment of the present application, the polling access by the autopoll controller 32 (i.e., the i.e., autopoll module 30) to the plurality of access operation instructions cmd_1-cmd_m may be configured to: in response to the current successfully polled access operation instruction, sending the current successfully polled access operation instruction to the serial bus controller 20; and, in response to the serial bus controller 20 completing an access operation corresponding to one of the access operation instructions currently received, polling the next access operation instruction.

Further alternatively, in the embodiment of the present application, during the polling access process of the autopoll controller 32 (i.e. the i.autopoll module 30) to the plurality of access operation instructions cmd_1 to cmd_m, a status check of the serial bus controller 20 may be introduced, so as to find out an abnormal status of the serial bus controller 20 in time and report the abnormal status to the chip management module 10. In this case, the polling access by the autopoll controller 32 (i.e., the i.e., autopoll module 30) to the plurality of access operation instructions cmd_1 to cmd_m may be configured to: in response to the current presence of a successfully polled access operation command cmd_j and the current status of the serial bus controller 20 being available, sending the current successfully polled access operation command cmd_j to the serial bus controller 20; and, in response to the serial bus controller 20 completing an access operation corresponding to one of the currently received access operation instructions cmd_j, polling the next access operation instruction cmd_j+1 (when j is less than m) or cmd_1 (when j=m).

Illustratively, in an embodiment of the present application, the number m of the plurality of access operation instructions cmd_1 to cmd_m may be equal to or greater than the number n of the at least two target sampling Data data_1 to data—n. In the case where the instruction number m is greater than the Data number n, since the access operation for acquiring a certain target sample Data data_i requires an additional write operation in addition to the read operation, among the plurality of access operation instructions cmd_1 to cmd_m, at least 1 write operation instruction for driving the serial bus controller 20 to perform the write operation may be additionally included in addition to n read operation instructions for driving the serial bus controller 20 to read at least two target sample Data data_1 to data_n through n serial bus-based read operations, respectively.

For example, for at least one of power consumption state sampling Data, current state sampling Data, voltage state sampling Data, and temperature state sampling Data of a power supply rail, before driving the serial bus controller 20 to perform a corresponding read operation on a corresponding power supply sampling device in the power supply sampling assembly 50, it is also necessary to transmit sampling configuration Data such as a power supply rail identification to the power supply sampling device through a write operation to the power supply sampling device so that the power supply sampling device can be configured to sample one of the plurality of power supply rails indicated by the power supply rail identification, whereby the target sampling Data data_i obtained by the read operation of the power supply sampling device thereafter can characterize at least one of the power consumption state sampling Data, the current state sampling Data, the voltage state sampling Data, and the temperature state sampling Data of the power supply rail indicated by the power supply rail identification.

That is, in the embodiment of the present application, the plurality of access operation instructions cmd_1 to cmd_m may include a write operation instruction with an access operation type being a write operation and a read operation instruction with an access operation type being a read operation, that is, each access operation instruction cmd_j may include an operation type for characterizing a corresponding access operation. Wherein the write operation is for writing the sampling configuration Data associated with the target sampling Data data_i to any one of the power sampling devices in the power sampling assembly 50, and the read operation is for reading the target sampling Data data_i from any one of the power sampling devices in the power sampling assembly 50. The sampling configuration data, which is write data corresponding to the write operation instruction, may be provided by the chip management module 10 and stored in the programmable auto-poll module 30 (for example, the instruction register set 311 or the data register set 312 of the register set 31).

Thus, in an embodiment of the present application, the driving of the serial bus controller 20 by the programmable autopolling module 30 (e.g., autopolling controller 32) can support switching of the Data transfer direction in the serial bus, i.e., switching between the transfer of sampling configuration Data as write Data from the serial bus controller 20 to any one of the power sampling devices in the power sampling assembly 50 and the transfer of target sampling Data data_i as read Data from any one of the power sampling devices in the power sampling assembly 50 to the serial bus controller 20, by the compatibility of the two access operation types, i.e., write operation and read operation.

Illustratively, in an embodiment of the present application, each of the plurality of access operation instructions cmd_1-cmd_m may include an access destination address, and the access destination address of the access operation instruction cmd_j includes a device bus address of any one of the power sampling devices in the power sampling assembly 50, so that the access destination address of the access operation instruction cmd_j may implement the addressing of the serial bus controller 20 for reading the target sampling Data data_i.

For example, in the embodiment of the present application, at least two target sampling Data data_1 to data—n may be sampled by the same power sampling device in the power sampling assembly 50, or at least two target sampling Data data_1 to data—n may be sampled by different power sampling devices in the power sampling assembly 50. If at least two target sampling Data data_1 to data_n are obtained by sampling respectively by different power sampling devices in the power sampling component 50, the device bus addresses included in the access destination addresses of the multiple access operation instructions cmd_1 to cmd_m (e.g., n read operation instructions therein) may not be identical, so that the access operation (e.g., n read operations) performed by the programmable autopolling module 30 (e.g., the autopolling controller 32) to drive the serial bus controller 20 may be switched between the different power sampling devices in the power sampling component 50, and thus, the at least two target sampling Data data_1 to data_n may be acquired from different power sampling devices in the power sampling component 50.

Illustratively, in an embodiment of the present application, each of the plurality of access operation instructions cmd_1 to cmd_m may further include a data transmission length, and the data transmission length is used to indicate the data length transmitted by the serial bus controller 20 during a single access operation in response to any one of the access operation instructions cmd_j. For example, the data length transmitted by the serial bus indicated by the data transmission length of the write operation command refers to the data length of the sampling configuration data as write data when the write operation corresponding to the write operation command is executed; the Data length indicated by the Data transfer length of the read operation command and transferred by the serial bus is the Data length of the target sample Data data_i, which is read Data, when the read operation corresponding to the read operation command is executed.

As can be seen from the above, in the embodiment of the present application, each access operation instruction cmd_j in the plurality of access operation instructions cmd_1 to cmd_m may further include at least one of an access type, an access destination address and a data transmission length, in addition to the instruction content.

Illustratively, in an embodiment of the present application, to facilitate the programmable autopolling module 30 (e.g., the autopolling controller 32) to automatically implement a poll access to the plurality of access operation instructions cmd_1-cmd_m, and to drive the serial bus controller 20 based on the poll results to the plurality of access operation instructions cmd_1-cmd_m, the autopolling controller 32 of the programmable autopolling module 30 may be controlled with a FSM (FINITE STATE MACHINE ). In this case, the polling access by the autopilot controller 32 to the plurality of access operation instructions cmd_1 to cmd_m (i.e., the register group 31) is controlled by the FSM, and the polling access by the autopoll controller 32 to the plurality of access operation instructions cmd_1 to cmd_m (i.e., the register group 31) can be controlled based on the state switching of the FSM as follows:

In response to a successful query of the access operation instruction cmd_j at the current polling position in the register file 31 (i.e., the access operation instruction cmd_j currently being successfully polled) and the current status of the serial bus controller 20 being available, sending the access operation instruction cmd_j at the current polling position in the register file 31 (i.e., the access operation instruction cmd_j currently being successfully polled) to the serial bus controller 20; and

In response to the serial bus controller 20 completing the access operation corresponding to the currently received one access operation command cmd_j, the current polling position in the register set 31 is updated according to the address offset used when the chip management module 10 writes the plurality of access operation commands cmd_1 to cmd_m in the register set 31, so as to poll the next access operation command cmd_j+1 (j is smaller than m) or cmd_1 (j=m).

Fig. 7 is a state transition schematic diagram of a finite state machine maintained by a programmable auto-poll module of a front-end circuit in an embodiment of the present application. Referring to fig. 7, the FSM for controlling the auto-poll controller 32 may include the following states: IDLE state IDLE, bus CHECK state CHECK, destination address configuration state CONFIG, operation control state CTRL, and operation WAIT state WAIT. In fig. 7, taking an example that the plurality of access operation instructions cmd_1 to cmd_m may include a write operation instruction having an access operation type of a write operation and a read operation instruction having an access operation type of a read operation, the operation control state CTRL may include a write operation control state tx_ctrl and a read operation control state rx_ctrl, and the operation waiting state includes a write operation waiting state tx_wait and a read operation waiting state rx_wait.

As shown in fig. 7, in an embodiment of the present application, when the FSM is in the IDLE state IDLE, the auto-poll controller 32 queries the access operation instruction cmd_j at the current polling position in the register file 31, and, in response to the current polling position in the register file 31 querying the access operation instruction cmd_j being successful, the FSM transitions from the IDLE state IDLE to the bus CHECK state CHECK. That is, the state transition trigger condition cond_ idl-ck for the FSM to transition from the IDLE state IDLE to the bus CHECK state CHECK may include: the current polling position in the register set 31 is a successful inquiry for the access operation instruction cmd_j.

As shown in fig. 7, in the embodiment of the present application, when the FSM is in the bus CHECK state CHECK, the auto polling controller 32 CHECKs whether the current state of the serial bus controller 20 is available and whether the access destination address of the serial bus controller 20 needs to be updated, and:

In response to the current state of the serial bus controller 20 being available and the access destination address of the serial bus controller 20 not needing to be updated, the FSM transitions from the bus CHECK state CHECK to the operation control state CTRL, or

In response to the current state of the serial bus controller 20 being available and the access destination address of the serial bus controller 20 requiring an update, the FSM transitions from the bus CHECK state CHECK to the destination address configuration state CONFIG.

That is, the state transition trigger condition cond_ck-ctr for the FSM to transition from the bus CHECK state CHECK to the operation control state CTRL may include: the current state of the serial bus controller 20 is available and the access destination address of the serial bus controller 20 does not need to be updated; and, the state transition trigger condition cond_ck-cfg for the FSM to transition from the bus CHECK state CHECK to the destination address configuration state CONFIG may include: the current state of the serial bus controller 20 is available and the access destination address of the serial bus controller 20 needs to be updated.

Illustratively, the checking by the autopolling controller 32 whether the current state of the serial bus controller 20 is available may include: checking whether the current working state of the serial bus controller 20 is idle and whether the controller buffer of the serial bus controller 20 is empty, wherein if the current working state of the serial bus controller 20 is idle and the controller buffer of the serial bus controller 20 is empty, the current state of the serial bus controller 20 is available, otherwise, the current state of the serial bus controller 20 is unavailable.

For example, the controller buffer of the serial bus controller 20 may include two FIFO (First Input First Output, first-in first-out) buffers, one being a TX FIFO for storing write data and the other being an RX FIFO for storing read data, and checking whether the controller buffer of the serial bus controller 20 is empty includes: if the access operation command cmd_j for the current polling position in the register file 31 is a write operation command, checking whether the TX FIFO for storing write data is empty; if the access operation command cmd_j for the current polling position in the register file 31 is a read operation command, it is checked whether the RX FIFO for storing read data is empty.

For example, if the operation control state CTRL may include the write operation control state tx_ctrl and the read operation control state rx_ctrl, when the FSM is in the bus CHECK state CHECK, the operation control state may be selectively migrated to the write operation control state tx_ctrl or the read operation control state rx_ctrl according to the access operation type of the access operation command cmd_j currently polled in the register set 31. Namely: if the access operation command cmd_j of the current polling position in the register set 31 is a write operation command, the migrated operation control state CTRL is a write operation control state tx_ctrl; if the access operation command cmd_j of the current polling position in the register file 31 is a read operation command, the migrated operation control state CTRL is a read operation control state rx_ctrl.

That is, the state transition trigger condition cond_ck-ctr for the FSM to transition from the bus CHECK state CHECK to the operation control state CTRL may include: a state transition trigger condition cond_ck-txc for the FSM to transition from the bus CHECK state CHECK to the write operation control state tx_ctrl, and a state transition trigger condition cond_ck-rxc for the FSM to transition from the bus CHECK state CHECK to the read operation control state rx_ctrl. The state transition trigger condition cond_ck-txc may include: the current state of the serial bus controller 20 is available, the access destination address of the serial bus controller 20 does not need to be updated, and the access operation instruction cmd_j of the current polling position in the register group 31 is a write operation instruction; and, the state transition trigger condition cond_ck-rxc may include: the current state of the serial bus controller 20 is available, the access destination address of the serial bus controller 20 does not need to be updated, and the access operation instruction cmd_j of the current polling position in the register group 31 is a read operation instruction.

As shown in fig. 7, in the embodiment of the present application, when the FSM is in the destination address configuration state CONFIG, the auto-polling controller 32 updates the access destination address of the serial bus controller 20 according to the access operation instruction cmd_j successfully queried at the current polling position, that is, updates the access destination address of the serial bus controller 20 to the access destination address indicated by the access operation instruction cmd_j at the current polling position in the register group 31, and in response to completion of the update of the access destination address of the serial bus controller 20, the FSM transitions from the destination address configuration state CONFIG to the operation control state CTRL.

That is, the migration trigger condition cond_cfg-ctr for the FSM to migrate from the destination address configuration state CONFIG to the operation control state CTRL may include: the updating of the access destination address of the serial bus controller 20 is completed.

Illustratively, if the access destination address of the access operation command cmd_j includes a device bus address of any one of the power sampling devices in the power sampling assembly 50, then the checking by the autopolling controller 32 whether the access destination address of the serial bus controller 20 needs to be updated may include: checking whether the device bus address indicated by the current polling position inquiry access operation instruction cmd_j in the register file 31 is the same as the device bus address included in the access destination address at the time when the serial bus controller 20 executed the access operation last time; if the addresses are the same, the access destination addresses do not need to be updated; otherwise, it indicates that the access destination address needs to be updated, for example, the device bus addresses included in the access destination addresses of the plurality of access operation instructions cmd_1 to cmd_m are not identical, and the device bus address indicated by the current polling location query access operation instruction cmd_j in the register file 31 triggers a switch between different power sampling means in the power sampling assembly 50 after the previous execution of the access operation by the bus controller 20.

For example, if the operation control state CTRL may include the write operation control state tx_ctrl and the read operation control state rx_ctrl, similar to the bus CHECK state CHECK, the FSM may be selectively migrated to the write operation control state tx_ctrl or the read operation control state rx_ctrl according to the access operation type of the access operation command cmd_j currently polled in the register set 31 when the FSM is in the address configuration state CONFIG.

That is, the state transition trigger condition cond_cfg-ctr for the FSM to transition from the address configuration state CONFIG to the operation control state CTRL may include: a state transition trigger condition cond_cfg-txc for the FSM to transition from the address configuration state CONFIG to the write operation control state tx_ctrl, and a state transition trigger condition cond_cfg-rxc for the FSM to transition from the address configuration state CONFIG to the read operation control state rx_ctrl. The state transition trigger condition cond_cfg-txc may include: the update of the access destination address of the serial bus controller 20 is completed, and the access operation instruction cmd_j of the current polling position in the register group 31 is a write operation instruction; and, the state transition trigger condition cond_cfg-rxc may include: the updating of the access destination address of the serial bus controller 20 is completed, and the access operation instruction cmd_j of the current polling position in the register group 31 is a read operation instruction.

As shown in fig. 7, in the embodiment of the present application, when the FSM is in the operation control state CTRL, the auto-polling controller 32 triggers the serial bus controller 20 to execute the access operation corresponding to the access operation command cmd_j successfully queried at the current polling position, and, in response to the completion of the triggering of the access operation of the serial bus controller 20 by the auto-polling controller 32, the FSM transitions from the operation control state CTRL to the operation WAIT state WAIT.

Illustratively, when the FSM is in the write operation control state tx_ctrl, the autopolling controller 32 triggers the serial bus controller 20 to perform a write operation corresponding to the successfully queried access operation command cmd_j at the current polling location and to write sample configuration data as write data into the controller cache of the serial bus controller 20, and, in response to completion of the triggering of the write operation of the serial bus controller 20 by the autopolling controller 32, the FSM transitions from the write operation control state tx_ctrl to the write operation WAIT state tx_wait.

Illustratively, when the FSM is in the read operation control state rx_ctrl, the autopolling controller 32 triggers the serial bus controller 20 to perform a read operation corresponding to the successfully queried access operation command cmd_j at the current polling location, and, in response to the autopolling controller 32 completing the triggering of the read operation of the serial bus controller 20, the FSM transitions from the read operation control state rx_ctrl to the read operation WAIT state rx_wait.

That is, the state transition trigger condition cond_ctr-wt for the FSM to transition from the operation control state CTRL to the operation WAIT state WAIT includes completion of the trigger of the access operation of the auto-poll controller 32 to the serial bus controller 20. And, the state transition trigger condition cond_ctr-wt may include a state transition trigger condition cond_ txc-twt for the FSM to transition from the write operation control state tx_ctrl to the write operation WAIT state tx_wait, and a state transition trigger condition cond_ rxc-rwt for the FSM to transition from the read operation control state rx_ctrl to the read operation WAIT state rx_wait. Wherein the state transition trigger condition cond_ txc-twt may include a completion of a trigger of a write operation of the autopilot controller 32 to the serial bus controller 20, and the state transition trigger condition cond_ rxc-rwt may include a completion of a trigger of a read operation of the autopilot controller 32 to the serial bus controller 20.

As shown in fig. 7, in the embodiment of the present application, when the FSM is in the operation waiting state WAIT, the auto-polling controller 32 WAITs for the serial bus controller 20 to complete the access operation corresponding to the access operation instruction cmd_j successfully queried at the current polling position, and in response to completion of execution of the access operation by the serial bus controller 20, the FSM transitions from the operation waiting state WAIT to the IDLE state IDLE and triggers updating of the current polling position in the register group 31.

Illustratively, when the FSM is in the write operation WAIT state TX_WAIT, auto-poll controller 32 WAITs for serial bus controller 20 to complete a write operation to the sampled configuration data, and in response to serial bus controller 20 completing a write operation to the sampled configuration data, the FSM transitions from the write operation WAIT state TX_WAIT to the IDLE state IDLE and triggers an update of the current poll location in register set 31.

Illustratively, when the FSM is in the read operation WAIT state rx_wait, the autopolling controller 32 WAITs for the serial bus controller 20 to complete a read operation on the target sample Data data_i, and in response to the serial bus controller 20 completing a read operation on the target sample Data data_i, the autopolling controller 32 writes the target sample Data data_i held as read Data in the controller cache of the serial bus controller 20 to the register component 31, and the FSM transitions from the read operation WAIT state rx_wait to the IDLE state IDLE and triggers an update of the current polling position in the register set 31.

That is, the FSM transitions from the operation waiting state WAIT to the IDLE state IDLE state transition trigger condition Cond_wt-idl. And, the state transition trigger condition cond_wt-idl for the FSM to transition from the operation WAIT state WAIT to the IDLE state IDLE may include the state transition trigger condition cond_ twt-idl for the FSM to transition from the write operation WAIT state tx_wait to the IDLE state IDLE and the state transition trigger condition cond_ rwt-idl for the FSM to transition from the read operation WAIT state rx_wait to the IDLE state IDLE. The state transition trigger condition cond_ twt-idl may include that the write operation of the serial bus controller 20 to the sampling configuration Data is completed, and the state transition trigger condition cond_ rwt-idl may include that the read operation of the serial bus controller 20 to the target sampling Data data_i is completed.

It will be appreciated that in embodiments of the application, the exemplary illustrations may be of an "and/or" relationship between portions of the content. As used herein, "and/or" means that the contexts joined by them may be in a commonly defined relationship of "and" or alternatively may be in a defined relationship of "or". Thus, each section of content having an "and/or" relationship is understood to include each section of content having "and/or" representing a commonly defined relationship of "and" respectively, "or a different combination of instances of an alternative defined relationship of" or, "and such a combination of different instances may be considered to be substantially equivalent to a defined range of" at least one of the sections.

In an embodiment of the application, there is also provided a processor comprising the front-end circuit 95 described in the previous embodiment. Illustratively, in an embodiment of the present application, the processor including the front-end circuit 95 may be any of a CPU (Central Processing Unit ), a GPU (Graphics Processing Unit, graphics processor), a TPU (Tensor Processing Unit, tensor processor), an NPU (Neural network Processing Unit, neural network processor), a DPU (DEEP LEARNING Processing Unit, deep learning processor), an APU (ACCELERATED PROCESSING UNIT, acceleration processor), and a GPGPU (General-Purpose computing on Graphics Processing Unit, general purpose graphics processor). That is, embodiments of the application do not limit the type of processor.

In an embodiment of the present application, there is also provided a board device, which may include a circuit board, the processor in the above embodiment, and a power sampling assembly, where the processor and the power sampling assembly are disposed on the circuit board.

In an embodiment of the present application, there is also provided an electronic device including the board card device in the above embodiment.

The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.

Claims

1. A front-end circuit of a processor, comprising:

2. The front-end circuit of claim 1, wherein,

The driving of the serial bus controller by the programmable automatic polling module is configured by the chip management module, and at least two target sampling data obtained by polling are determined based on the configuration of the programmable automatic polling module by the chip management module.

3. The front-end circuit of claim 2, wherein,

The programmable automatic polling module is also used for storing an operation instruction set generated by the chip management module;

The programmable auto-poll module is configured to: and sequentially sending a plurality of access operation instructions to the serial bus controller through polling a plurality of access operation instructions in the operation instruction set, so that the serial bus controller executes access operation for polling to acquire at least two target sampling data on the power supply sampling assembly according to the sequentially received access operation instructions.

4. The front-end circuit of claim 3, wherein,

The access destination address of the access operation instruction comprises a device bus address of any one power sampling device in the power sampling assembly, and the device bus addresses included in the access destination addresses of the access operation instructions are not identical, so that the access operation can acquire at least two target sampling data from different power sampling devices in the power sampling assembly through switching among the different power sampling devices in the power sampling assembly;

And/or the number of the groups of groups,

The plurality of access operation instructions include a write operation instruction with an access operation type of a write operation for writing sampling configuration data associated with the target sampling data to any one of the power sampling devices in the power sampling assembly, the sampling configuration data being provided by the chip management module, and a read operation instruction with an access operation type of a read operation for reading the target sampling data from any one of the power sampling devices in the power sampling assembly;

And/or the number of the groups of groups,

Each of the plurality of access operation instructions includes a data transmission length, and the data transmission length is used for indicating the data length transmitted by the serial bus controller during a single access operation period of the serial bus controller responding to any one of the access operation instructions;

And/or the number of the groups of groups,

The polling access by the programmable autopolling module to the plurality of access operation instructions is configured to: transmitting the access operation instruction which is successfully polled to the serial bus controller in response to the access operation instruction which is successfully polled and the current state of the serial bus controller being available; and responding to the serial bus controller to finish the access operation corresponding to one currently received access operation instruction, and polling the next access operation instruction.

5. The front-end circuit of claim 3, wherein,

The programmable automatic polling module comprises a register group, and the register group is used for storing a plurality of access operation instructions written by the chip management module and at least two target sampling data acquired by the serial bus controller through the access operation polling;

The programmable auto-poll module further includes an auto-poll controller, and the auto-poll controller is to: sequentially transmitting a plurality of access operation instructions stored in the register set to the serial bus controller through polling access to the register set; and writing at least two target sample data acquired by the serial bus controller through the access operation polling into the register set;

Wherein the periodic acquisition of the power state sampling data by the chip management module is configured to: and periodically acquiring at least two target sampling data stored in the register set through the on-chip access.

6. The front-end circuit of claim 5, wherein,

The registers in the register set are MMIO registers;

And/or the number of the groups of groups,

The register set includes an instruction register set in which a plurality of the access operation instructions are held, and a data register set in which at least two of the target sample data are held.

7. The front-end circuit of claim 5, wherein,

The polling access of the automatic polling controller to the register set is controlled by a finite state machine, and the polling access of the automatic polling controller to the register set is controlled based on state switching of the finite state machine as follows:

Transmitting the access operation instruction of the current polling position in the register set to the serial bus controller in response to the successful inquiry of the access operation instruction of the current polling position in the register set and the availability of the current state of the serial bus controller; and

And responding to the serial bus controller to finish the access operation corresponding to one currently received access operation instruction, and updating the current polling position in the register group according to the address offset used when the chip management module writes a plurality of access operation instructions in the register group.

8. The front-end circuit of claim 7, wherein,

The finite state machine includes the following states: an idle state, a bus check state, a destination address configuration state, an operation control state, and an operation waiting state;

when the finite state machine is in the idle state, the auto-poll controller queries the access operation instruction at a current poll location in the register set, and, in response to a successful query of the access operation instruction at the current poll location in the register set, the finite state machine transitions from the idle state to the bus check state;

When the finite state machine is in the bus check state, the auto-poll controller checks whether a current state of the serial bus controller is available and whether an access destination address of the serial bus controller needs to be updated, and, in response to the current state of the serial bus controller being available and the access destination address not needing to be updated, the finite state machine transitions from the bus check state to the operation control state, or in response to the current state of the serial bus controller being available and the access destination address needing to be updated, the finite state machine transitions from the bus check state to the destination address configuration state;

When the finite state machine is in the destination address configuration state, the automatic polling controller updates an access destination address of the serial bus controller according to the access operation instruction successfully queried at a current polling position, and the finite state machine is migrated from the destination address configuration state to the operation control state in response to completion of updating of the access destination address;

When the finite state machine is in the operation control state, the automatic polling controller triggers the serial bus controller to execute the access operation corresponding to the access operation instruction successfully inquired at the current polling position, and the finite state machine is migrated from the operation control state to the operation waiting state in response to the completion of triggering the access operation;

When the finite state machine is in the operation waiting state, the automatic polling controller waits for the serial bus controller to finish the access operation corresponding to the access operation instruction successfully inquired at the current polling position, and in response to the execution of the access operation being finished, the finite state machine transits from the operation waiting state to the idle state and triggers the updating of the current polling position in the register group.

9. The front-end circuit of claim 8, wherein,

The automatic polling controller checking whether the current state of the serial bus controller is available includes: checking whether the current working state of the serial bus controller is idle and whether a controller cache of the serial bus controller is empty, wherein if the current working state of the serial bus controller is idle and the controller cache is currently empty, the current state of the serial bus controller is available, otherwise, the current state of the serial bus controller is unavailable;

And/or the number of the groups of groups,

The access destination address of the access operation instruction includes a device bus address of any one of the power sampling devices in the power sampling assembly, the device bus addresses included in the access destination addresses of the access operation instructions are not identical, and the checking by the autopolling controller whether the access destination address of the serial bus controller needs to be updated includes: checking whether the device bus address indicated by the access operation instruction is queried at the current polling position in the register group and the device bus address included in the access destination address when the serial bus controller executes the access operation last time are the same, wherein if so, the device bus address is not required to be updated, otherwise, the device bus address is required to be updated.

10. The front-end circuit of claim 8, wherein,

The plurality of access operation instructions include a write operation instruction of which an access operation type is a write operation for writing sampling configuration data associated with the target sampling data to any one of the power sampling devices in the power sampling assembly, and a read operation instruction of which an access operation type is a read operation for reading the target sampling data from any one of the power sampling devices in the power sampling assembly;

The operation control states include a write operation control state and a read operation control state, and the operation waiting state includes a write operation waiting state and a read operation waiting state;

when the finite state machine is in the bus checking state or the destination address configuration state, selectively migrating to the write operation control state or the read operation control state according to the access operation type of the access operation instruction queried at the current polling position in the register group;

When the finite state machine is in the writing operation control state, the automatic polling controller triggers the serial bus controller to execute writing operation corresponding to the access operation instruction successfully inquired at the current polling position and writes the sampling configuration data into a controller cache of the serial bus controller, and the finite state machine is migrated from the writing operation control state to the writing operation waiting state in response to completion of triggering the writing operation;

When the finite state machine is in the write operation waiting state, the auto-polling controller waits for the serial bus controller to complete writing of the sampling configuration data, and in response to the writing of the sampling configuration data being completed, the finite state machine transitions from the write operation waiting state to the idle state and triggers updating of a current polling position in the register set;

When the finite state machine is in the read operation control state, the automatic polling controller triggers the serial bus controller to execute the read operation corresponding to the access operation instruction successfully inquired at the current polling position, and the finite state machine is migrated from the read operation control state to the read operation waiting state in response to the completion of triggering the read operation;

When the finite state machine is in the read operation waiting state, the auto-polling controller waits for the serial bus controller to complete the read operation of the target sample data, and, in response to the completion of the read operation of the target sample data, the auto-polling controller writes the target sample data held in a controller cache of the serial bus controller into the register component, and the finite state machine transitions from the read operation waiting state to the idle state and triggers an update of a current polling position in the register group.

11. A processor comprising the front-end circuitry of any of claims 1 to 10.

12. A board card apparatus comprising a circuit board, the processor of claim 11, and the power sampling assembly, and wherein the processor and the power sampling assembly are both disposed on the circuit board.

13. An electronic device comprising the board card apparatus of claim 12.