CN118549797A - Chip frequency anomaly detection method, system and storage medium - Google Patents
Chip frequency anomaly detection method, system and storage medium Download PDFInfo
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Abstract
The invention provides a method, a system and a storage medium for detecting abnormal working frequency of a chip, which belong to the technical field of integrated circuits, wherein in the method, a first low-frequency alarm threshold value and a first high-frequency alarm threshold value of a frequency sensor are determined according to the expected working frequency of an external clock of the chip, the expected working frequency of an internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor, according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the external clock of the chip and the frequency division coefficient of the frequency sensor, the actual working frequency of the internal clock of the chip is determined, so that the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor are determined, the calibration of the frequency sensor is realized, finally, the calibrated frequency sensor is utilized to detect the working frequency of the external clock of the chip, and the precision and accuracy of the detection of the working frequency of the external clock of the chip are improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a method, a system and a storage medium for detecting abnormal frequency of a chip.
Background
The chip is widely applied to various fields such as national defense, finance, medical treatment, traffic and the like, and the safety of the chip is directly related to the reliability of the fields, so that a targeted protection means is needed to ensure the safety of the chip. When a chip is attacked, the frequency of the chip may be abnormal, and a security chip password detection criterion (GMT 0008-2012) requires the chip: when the chip carries out a certain cryptographic algorithm operation, the environment in which the chip is positioned is changed, and when the frequency threshold value declared by the chip is exceeded or is lower than the frequency threshold value declared by the chip, the alarm interrupt of the corresponding sensor is triggered, and whether the alarm has occurred is judged according to the action of the interrupt processing function. Therefore, by detecting the frequency of the chip, the frequency state of the chip can be effectively detected by alarming when the frequency exceeds or falls below the frequency threshold of the chip, and external physical attacks can be recognized and protected to a certain extent.
The patent application with the application publication number of CN101968840A discloses a chip anti-attack method based on voltage detection and frequency detection, and discloses that core data of normal operation of a chip is stored in a nonvolatile memory; monitoring external clock input through a frequency detection unit, reacting to the abnormality once the input clock frequency is abnormal, and transmitting the reaction result to a CPU main control unit; after the CPU main control unit receives the abnormal reaction of the frequency detection unit and the voltage detection unit, the whole chip is controlled by the anti-attack unit, and the protection of core data in the chip is implemented. However, the ring vibration in the frequency detection unit of the above patent application may be biased due to the influence of the temperature, voltage and/or production process of the chip, so that there is a certain difference in the ring vibration frequency between the chips, which may affect the accuracy of frequency detection to a certain extent.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides the chip frequency abnormality detection method which can detect the working frequency of the external clock of the chip, thereby being convenient for determining whether the frequency of the chip is abnormal according to the detection result of the frequency of the external clock of the chip and improving the frequency detection precision of the chip, particularly the safety chip.
In a first aspect, the present invention provides a method for detecting an abnormality of an operating frequency of an external clock of a chip, including:
Acquiring the expected working frequency of the external clock of the chip, the expected working frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
Determining a first low-frequency alarm threshold and a first high-frequency alarm threshold of the frequency sensor according to the expected working frequency of the chip external clock, the expected working frequency of the chip internal clock, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
acquiring the actual working frequency of an external clock of a chip;
Determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor;
Determining a second low-frequency alarm threshold and a second high-frequency alarm threshold of the frequency sensor according to the actual working frequency of the clock in the chip;
and determining whether the working frequency of the clock outside the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor.
Optionally, the determining the first low-frequency alarm threshold and the first high-frequency alarm threshold of the frequency sensor according to the expected operating frequency of the external clock of the chip, the expected operating frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor includes:
the first low frequency alarm threshold L 1 and the first high frequency alarm threshold H 1 of the frequency sensor are calculated according to the following formulas:
；
Wherein d is the frequency division coefficient of the frequency sensor; f 1 is the expected operating frequency of the chip internal clock; f 1 is the expected operating frequency of the chip external clock; p is the frequency detection accuracy of the frequency sensor.
Optionally, the determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor includes:
The actual operating frequency f 2 of the internal clock of the chip is calculated according to the following formula:
；
Wherein F 2 is the actual working frequency of the external clock of the chip; p is the frequency detection precision of the frequency sensor; d is the frequency division coefficient of the frequency sensor; l 1 is a first low-frequency alarm threshold of the frequency sensor.
Optionally, the determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor includes:
The actual operating frequency f 2 of the internal clock of the chip is calculated according to the following formula:
；
Wherein F 2 is the actual working frequency of the external clock of the chip; p is the frequency detection precision of the frequency sensor; d is the frequency division coefficient of the frequency sensor; h 1 is the first high-frequency alarm threshold of the frequency sensor.
Optionally, the determining the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor according to the actual working frequency of the internal clock of the chip includes:
the second low frequency alarm threshold L 2 and the second high frequency alarm threshold H 2 of the frequency sensor are calculated according to the following formulas:
；
Wherein d is the frequency division coefficient of the frequency sensor; f 2 is the actual working frequency of the clock inside the chip; f 1 is the desired operating frequency of the chip external clock.
Optionally, the determining whether the working frequency of the external clock of the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor includes:
Enabling the frequency sensor;
After enabling the frequency sensor, dividing the frequency of the external clock of the chip to obtain a clock div_clk of the external clock of the chip after the frequency division of the external clock of the chip in the internal clock domain of the chip;
Counting the single pulse length of div_clk to obtain the cycle number cnt of the internal clock of the chip contained in one single pulse length of div_clk;
And determining the abnormal working frequency of the external clock of the chip according to the cycle number cnt.
Optionally, the determining whether the working frequency of the external clock of the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor includes:
Delaying the enabling signal of the frequency sensor for two clock cycles under the clock domain in the chip, detecting the rising edge of the enabling signal delayed for two clock cycles, and enabling the frequency sensor at the rising edge of the enabling signal;
And/or after enabling the frequency sensor, adopting a counter to start counting at the rising edge of each chip external clock, turning over the clock after the frequency division of the chip external clock and resetting the counter when the counting reaches a preset frequency division coefficient to obtain a clock div_clk after the frequency division of the chip external clock under the chip internal clock domain;
And/or detecting rising edges and falling edges of the div_clk under the internal clock domain of the chip, setting a counter, and counting the single pulse length of the div_clk by adopting the internal clock of the chip to obtain a cycle number cnt containing the internal clock of the chip in one single pulse length of the div_clk;
And/or determining that the working frequency of the clock outside the chip is abnormal under the condition that cnt is larger than the second low-frequency alarm threshold or cnt is smaller than the second high-frequency alarm threshold. .
In a second aspect, the present invention provides a method for detecting frequency anomalies of a chip, including: and taking the detection result of whether the working frequency of the external clock of the chip is abnormal or not, which is obtained by the detection method of the working frequency abnormality of the external clock of the chip in the first aspect, as the detection result of whether the working frequency of the external clock of the chip is abnormal or not.
In a third aspect, the present invention provides a system for detecting abnormality of an operating frequency of an external clock of a chip, comprising:
The first acquisition module is used for acquiring the expected working frequency of the external clock of the chip, the expected working frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
the first determining module is used for determining a first low-frequency alarm threshold value and a first high-frequency alarm threshold value of the frequency sensor according to the expected working frequency of the external clock of the chip, the expected working frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
The second acquisition module is used for acquiring the actual working frequency of the external clock of the chip;
the second determining module is used for determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor;
The third determining module is used for determining a second low-frequency alarm threshold value and a second high-frequency alarm threshold value of the frequency sensor according to the actual working frequency of the clock in the chip;
And the fourth determining module is used for determining whether the working frequency of the clock outside the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor.
In a fourth aspect, the present invention provides a computer-readable storage medium storing a computer program; the computer program when executed by a processor implements the steps of the method for detecting an abnormality in the operating frequency of the external clock of the chip according to the first aspect.
Advantageous effects
The invention provides a method and a system for detecting abnormal working frequency of an external clock of a chip, which are used for a security chip, wherein the security chip at least has two clock sources of an internal clock and an external clock, the internal clock is generated by an internal ring oscillator which is fixed and is difficult to attack, the external clock is an external input clock, and the working efficiency of an internal circuit of the chip is determined by the external clock. The working state of the chip is abnormal and disordered due to the excessively high frequency of the external clock; too low an external clock frequency can affect chip performance and efficiency. Therefore, the method for detecting the abnormal working frequency of the external clock of the chip provided by the invention takes the external clock as the measured clock to be monitored. And determining a second low-frequency alarm threshold and a second high-frequency alarm threshold of the frequency sensor according to the actual working frequency of the internal clock of the chip so as to calibrate the frequency sensor, detecting the working frequency of the external clock of the chip according to the calibrated frequency sensor, and further determining whether the frequency of the chip is abnormal according to the frequency detection result of the external clock of the chip, thereby improving the frequency detection precision of the chip, particularly the safety chip.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for detecting an abnormality of an operating frequency of an external clock of a chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of high frequency alarm and low frequency alarm provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating connection between a frequency detection module and an alarm management module according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a synchronous processing of a frequency sensor enable signal according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a low frequency alarm according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a high frequency alarm according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a system for detecting an abnormality in the operating frequency of an external clock of a chip according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Based on believing that the internal clock of the chip is hard to attack relative to the external clock, the external clock is used as a detected clock to be monitored, the frequency of the external clock (detected clock) is counted by taking the internal clock as a reference clock, and whether the working frequency of the external clock of the chip is abnormal or not is further determined, and whether the frequency of the chip is abnormal or not is judged according to the working frequency.
Example 1
In an ideal state, the internal clock of the safety chip is relatively stable, and the internal ring vibration usually generates a reference clock with fixed frequency, but because the temperature, the voltage and/or the production process of the chip generate deviation, the chip-to-chip difference and other factors influence the frequency of the internal clock to be different to some extent, when the frequency is detected, the circuit of the frequency sensor is required to be calibrated first, and the frequency of the reference clock (internal ring vibration) is calibrated, so that the frequency of the detected clock can be counted by using the accurate frequency of the reference clock, thereby ensuring the accuracy of the frequency detection.
As shown in fig. 1, the present embodiment provides a method for detecting an abnormality of an operating frequency of an external clock of a chip, including:
Step 101, acquiring the expected operating frequency of the external clock of the chip, the expected operating frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor.
Step 102, determining a first low-frequency alarm threshold and a first high-frequency alarm threshold of the frequency sensor according to the expected operating frequency of the chip external clock, the expected operating frequency of the chip internal clock, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor.
In this step, the first low frequency alarm threshold L 1 and the first high frequency alarm threshold H 1 of the frequency sensor are exemplarily calculated according to the following formulas:
。
Wherein d is the frequency division coefficient of the frequency sensor; f 1 is the expected operating frequency of the chip internal clock; f 1 is the expected operating frequency of the chip external clock; p is the frequency detection accuracy of the frequency sensor.
Step 103, obtaining the actual working frequency of the external clock of the chip.
Step 104, determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor.
In this step, when determining the actual operating frequency of the internal clock of the chip according to the first low-frequency alarm threshold, the actual operating frequency of the external clock of the chip, and the frequency division coefficient of the frequency sensor, the actual operating frequency f 2 of the internal clock of the chip is calculated according to the following formula:
。
Wherein F 2 is the actual operating frequency of the chip external clock.
When the actual working frequency of the internal clock of the chip is determined according to the first high-frequency alarm threshold, the actual working frequency of the external clock of the chip and the frequency division coefficient of the frequency sensor, the actual working frequency f 2 of the internal clock of the chip is calculated according to the following formula:
。
wherein H 1 is a first high-frequency alarm threshold of the frequency sensor.
And 105, determining a second low-frequency alarm threshold value and a second high-frequency alarm threshold value of the frequency sensor according to the actual working frequency of the clock in the chip.
In this step, the second low-frequency alarm threshold L 2 and the second high-frequency alarm threshold H 2 of the frequency sensor are exemplarily calculated according to the following formulas:
。
And step 106, determining whether the working frequency of the clock outside the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor.
This step includes enabling the frequency sensor. Illustratively, the enable signal of the frequency sensor is delayed by two clock cycles under the chip internal clock domain, and the rising edge of the enable signal delayed by two clock cycles is detected, at which the frequency sensor is enabled.
After the frequency sensor is enabled, the external clock of the chip is divided to obtain a clock div_clk of the external clock of the chip after the external clock of the chip is divided under the internal clock domain of the chip. Illustratively, after the frequency sensor is enabled, a counter is adopted to start counting at the rising edge of each chip external clock, when the counter counts to a preset frequency division coefficient, the clock after the frequency division of the chip external clock is turned over, and the counter is reset, so that the clock div_clk after the frequency division of the chip external clock under the chip internal clock domain is obtained.
The single pulse length of div_clk is counted to obtain the cycle number cnt of the internal clock of the chip contained in one single pulse length of div_clk. Illustratively, under the internal clock domain of the chip, the rising edge and the falling edge of div_clk are detected, a counter is set, and the internal clock of the chip is used to count the single pulse length of div_clk, so as to obtain the period number cnt of the internal clock of the chip contained in one single pulse length of div_clk.
And determining the abnormal working frequency of the external clock of the chip according to the cycle number cnt. For example, if cnt is greater than the second low frequency alarm threshold or cnt is less than the second high frequency alarm threshold, an off-chip clock operating frequency anomaly is determined.
In this step, as shown in fig. 2, after the frequency sensor circuit is calibrated, the frequency division coefficient d (div) of the frequency sensor, the second low-frequency alarm threshold value, and the second high-frequency alarm threshold value are configured. The frequency sensor circuit is enabled and the frequency sensor starts to operate. Because the input signal of the frequency sensor and the working clock of the frequency sensor may be different in frequency, the frequency sensor needs to consider the problem of synchronization of the input signal when working, and the signals crossing clock domains are subjected to asynchronous handover. Since the input signals of the frequency sensor are configured after calibration except the enable signal (en), only the enable signal (en) of the frequency sensor is required to be synchronized to the reference clock domain. As shown in fig. 4, the D flip-flop triggered by three rising edges and an and gate are implemented, the enable signal is tapped two beats (i.e., delayed by two clock cycles to complete the synchronization operation in two consecutive clock cycles) under the reference clock domain, and the rising edges of the tapped enable signal are detected, and the frequency sensor is enabled at the rising edges of the enable signal, and the frequency sensor starts to operate.
The frequency sensor working mechanism is to count the frequency of a measured clock by taking an internal clock as a reference clock so as to judge whether the relative relation of the frequency of the measured clock accords with the expectation or not, and the frequency of an external clock of a safety chip is often far higher than that of an internal ring vibration clock, so that the frequency division processing is needed to be carried out on the external clock firstly, and the larger the frequency division coefficient is, the more the frequency difference between the two clocks is, the more accurate the counting is, and the higher the detection precision is. The specific implementation mode of dividing the measured clock test_clk by adopting the counter is as follows: setting an n-bit counter (n can be configured by an external input through a bus, and n can be all natural numbers within the data bit width of the bus), when the enabled frequency sensor works, starting the counter to count circularly under the trigger of the rising edge of the measured clock, counting from 0 to div-1, turning over the clock div_clk after the frequency division of the measured clock when the counted frequency division coefficient is set, and resetting the counter, so that the clock div_clk after the frequency division of the measured clock 2div is finally obtained.
After the measured clock is subjected to frequency division and synchronization processing, the measured clock is frequency-divided to a frequency far lower than that of the reference clock, and after the clock div_clk of the measured clock after frequency division in the reference clock domain is obtained, whether the frequency of the measured clock test_clk is in a threshold range can be detected through the frequency relation between div_clk and the reference clock ref_clk.
In an exemplary embodiment, an m-bit counter (m may be configured by an external input through a bus, m may take any natural number within a bus data bit width) is set in a reference clock domain, a rising edge and a falling edge of div_clk are detected, the counter starts counting under the triggering of the rising edge of div_clk, a single pulse length of div_clk is counted by using the reference clock ref_clk, the counter clears and starts counting cyclically under the triggering of the falling edge of div_clk, a cycle number cnt including the reference clock is counted in one single pulse length of div_clk, and a relative relationship between the cycle number cnt and a second low-frequency alarm threshold and a second high-frequency alarm threshold of the frequency sensor is judged at each div_clk clock edge, if the second low-frequency alarm threshold or the second high-frequency alarm threshold range is exceeded, the output frequency sensor corresponds to a high-frequency or low-frequency alarm signal, that is, if cnt is greater than the second low-frequency alarm threshold or cnt is smaller than the second high-frequency alarm threshold, the external clock sensor determines that the external clock corresponds to the high-frequency alarm signal.
If the alarm signal output by the frequency sensor is directly used as an actual alarm signal, a false alarm condition may exist, and the normal operation of the chip is affected. In order to prevent false alarm scenes, the embodiment of the invention also provides an alarm management method, which can manage alarm signals through external input and support functions of alarm signal shielding, configurable alarm frequency threshold, inquireable current alarm frequency state and the like.
The alarm signal shielding register is set for controlling the output of the alarm signal, the authority is readable and writable, default is 0, the alarm signal is output, and when the alarm signal shielding register writes 1, the alarm signal can be shielded, and the output of the alarm signal is forbidden.
The alarm frequency register is set as a readable register, and the frequency of the current frequency alarm is stored in the alarm frequency register, so that the state of the current frequency alarm can be read.
Setting an alarm signal frequency threshold register, wherein the authority is readable and writable, and defaults to 1, which means that an alarm signal is output only once alarm occurs, the alarm signal frequency threshold register can be configured by an external input signal through a bus, so that the false alarm probability is reduced, and when the system alarm frequency reaches a threshold value, the actual alarm is triggered again.
As shown in fig. 3, the input signals are the external clock (clock under test) test_clk of the security chip, the reset test_rst_n in the clock under test domain, the internal clock (reference clock) ref_clk, the reset ref_rst_n in the reference clock domain, the frequency sensor enable en, the frequency division coefficient div of the clock under test, the low frequency alarm threshold(I.e., second low frequency alarm threshold), high frequency alarm threshold(I.e., a second high frequency alarm threshold), an alarm mask signal alarm_mask, a low frequency alarm count threshold l_alarm_times_th, and a high frequency alarm count threshold h_alarm_times_th. The output signals are alarm times alarm_info, low-frequency alarm l_alarm and high-frequency alarm h_alarm.
The relation between the frequency sensor module and the alarm management module in the invention is shown in fig. 3, and the respective interface signal descriptions are shown in tables 1 and 2 respectively.
Table 1 frequency sensor module I/O interface signal list
Table 2 alarm management Module I/O interface Signal List
In this embodiment, as shown in the timing diagrams of fig. 5 and 6, the security chip with a detection operating frequency of 500M and an internal clock of 2M ring oscillation is shown in table 3, and all the register lists that can be configured by external input signals through the bus are shown in the table 3. The accuracy of the frequency sensor detection can be controlled by setting appropriate frequency division coefficients and thresholds, and the relationship between these parameters and the accuracy is shown in table 4. The measured clock frequencies are respectively set to be 440M and 560M in the test excitation, and when the measured clock frequency exceeds a threshold value, a corresponding alarm occurs. The feasibility of the method for detecting the working frequency abnormality of the chip external clock provided by the embodiment of the invention is proved.
Table 3 register list
TABLE 4 parameter configuration relationship Table
In summary, according to the method for detecting the abnormal working frequency of the external clock of the chip provided by the embodiment, the actual working frequency of the internal clock of the chip is determined according to the first low-frequency alarm threshold and the first high-frequency alarm threshold by determining the first low-frequency alarm threshold and the first high-frequency alarm threshold of the frequency sensor, so that the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor are determined, the calibration of the frequency sensor is realized, the working frequency of the external clock of the chip is detected by using the calibrated frequency sensor, and the precision and the accuracy of the detection of the working frequency of the external clock of the chip are improved.
Example 2
The embodiment provides a chip frequency anomaly detection method suitable for a security chip, which comprises the following steps: the detection result of whether the chip external clock operating frequency is abnormal, which is obtained by using the method for detecting abnormality of the chip external clock operating frequency described in embodiment 1, is used as the detection result of whether the chip frequency is abnormal.
Example 3
The same concept as that of embodiment 1 is based on the same invention, and this embodiment also provides a system for detecting abnormal operating frequency of an external clock of a chip, and since the principle of solving the problem of the system is similar to that of the foregoing method for detecting abnormal operating frequency of an external clock of a chip, the implementation of the system can be referred to the implementation of the method for detecting abnormal operating frequency of an external clock of a chip.
As shown in fig. 7, the chip external clock operating frequency abnormality detection system includes:
The first acquisition module 10 is configured to acquire an expected operating frequency of the external clock of the chip, an expected operating frequency of the internal clock of the chip, a frequency division coefficient of the frequency sensor, and frequency detection accuracy of the frequency sensor.
The first determining module 20 is configured to determine a first low-frequency alarm threshold and a first high-frequency alarm threshold of the frequency sensor according to an expected operating frequency of the external clock of the chip, an expected operating frequency of the internal clock of the chip, a frequency division coefficient of the frequency sensor, and frequency detection accuracy of the frequency sensor.
The second obtaining module 30 is configured to obtain an actual operating frequency of the external clock of the chip.
The second determining module 40 is configured to determine an actual operating frequency of the internal clock of the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual operating frequency of the external clock of the chip, and the frequency division coefficient of the frequency sensor.
The third determining module 50 is configured to determine a second low-frequency alarm threshold and a second high-frequency alarm threshold of the frequency sensor according to an actual operating frequency of the internal clock of the chip.
And a fourth determining module 60, configured to determine whether the operating frequency of the external clock of the chip is abnormal according to the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor.
Illustratively, the first determining module includes:
A first calculation unit for calculating a first low frequency alarm threshold L 1 and a first high frequency alarm threshold H 1 of the frequency sensor according to the following formula:
。
Wherein d is the frequency division coefficient of the frequency sensor; f 1 is the expected operating frequency of the chip internal clock; f 1 is the expected operating frequency of the chip external clock; p is the frequency detection accuracy of the frequency sensor.
Illustratively, the second determining module includes:
The second calculating unit is used for calculating the actual working frequency f 2 of the internal clock of the chip according to the following formula:
。
Wherein F 2 is the actual working frequency of the external clock of the chip; p is the frequency detection precision of the frequency sensor; d is the frequency division coefficient of the frequency sensor; l 1 is a first low-frequency alarm threshold of the frequency sensor; h 1 is the first high-frequency alarm threshold of the frequency sensor.
Illustratively, the second determining module further comprises:
the third calculation unit is configured to calculate the actual operating frequency f 2 of the internal clock of the chip according to the following formula:
。
wherein H 1 is a first high-frequency alarm threshold of the frequency sensor.
Illustratively, the third determination module includes:
A fourth calculation unit for calculating a second low-frequency alarm threshold L 2 and a second high-frequency alarm threshold H 2 of the frequency sensor according to the following formulas:
。
Wherein d is the frequency division coefficient of the frequency sensor; f 2 is the actual working frequency of the clock inside the chip; f 1 is the expected operating frequency of the chip external clock; p is the frequency detection accuracy of the frequency sensor.
Illustratively, the fourth determination module includes:
And the enabling unit is used for enabling the frequency sensor. Optionally, the enabling unit is configured to delay the enabling signal of the frequency sensor by two clock cycles under the clock domain inside the chip, and detect a rising edge of the enabling signal delayed by two clock cycles, and enable the frequency sensor at the rising edge of the enabling signal.
And the frequency dividing unit is used for dividing the frequency of the external clock of the chip after the frequency sensor is enabled to obtain a clock div_clk of the external clock of the chip after the frequency division of the external clock of the chip under the internal clock domain of the chip. Optionally, the frequency dividing unit is configured to, after the frequency sensor is enabled, start counting at a rising edge of each chip external clock by using a counter, and when counting to a preset frequency dividing coefficient, flip the clock after frequency division of the chip external clock and reset the counter to obtain a clock div_clk after frequency division of the chip external clock in the chip internal clock domain.
And the counting unit is used for counting the single pulse length of the div_clk to obtain the cycle number cnt of the internal clock of the chip contained in one single pulse length of the div_clk. Optionally, the counting unit is configured to detect a rising edge and a falling edge of the div_clk under the internal clock domain of the chip, set a counter, and count the single pulse length of the div_clk by using the internal clock of the chip to obtain a period number cnt including the internal clock of the chip in one single pulse length of the div_clk.
And the determining unit is used for determining the working frequency abnormality of the external clock of the chip according to the cycle number cnt. Optionally, the determining unit is configured to determine that the working frequency of the external clock of the chip is abnormal if cnt is greater than the second low-frequency alarm threshold or cnt is less than the second high-frequency alarm threshold.
For more specific working procedures of the above modules, reference may be made to the corresponding contents disclosed in embodiment 1, and no further description is given here.
Example 4
The embodiment provides a computer device comprising a processor and a memory; the processor executes the computer program stored in the memory to implement the method for detecting the abnormality of the operating frequency of the external clock of the chip according to embodiment 1.
For more specific procedures regarding the above method, reference may be made to the corresponding contents disclosed in embodiment 1, and no further description is given here.
Example 5
The present embodiment provides a computer-readable storage medium storing a computer program; the computer program when executed by a processor implements the steps of the method for detecting an abnormality in the operating frequency of the external clock of the chip described in embodiment 1.
For more specific procedures regarding the above method, reference may be made to the corresponding contents disclosed in embodiment 1, and no further description is given here.
Example 6
The present embodiment provides a computer program product, including computer executable instructions or a computer program, where the computer executable instructions or the computer program implement the steps of the method for detecting an abnormality of an operating frequency of an external clock of a chip according to embodiment 1 when the computer executable instructions or the computer program are executed by a processor.
For more specific procedures regarding the above method, reference may be made to the corresponding contents disclosed in embodiment 1, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the system, apparatus, storage medium and computer program product of the embodiment disclosure, the description is relatively simple, and relevant places refer to the description of the method section, since it corresponds to the method of the embodiment disclosure.
It will be apparent to those skilled in the art that the techniques of embodiments of the present invention may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in essence or what contributes to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the present invention.
In some embodiments, computer-executable instructions may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, in the form of programs, software modules, scripts, or code, and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.
As an example, computer-executable instructions may, but need not, correspond to files in a file system, may be stored in a portion of a file that holds other programs or data, such as in one or more scripts in a hypertext markup language (Hyper Text Markup Language, HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).
As an example, computer-executable instructions may be deployed to be executed on one electronic device or on multiple electronic devices located at one site or distributed across multiple sites and interconnected by a communication network.
The invention has been described in detail in connection with the specific embodiments and exemplary examples thereof, but such description is not to be construed as limiting the invention. It will be understood by those skilled in the art that various equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its embodiments without departing from the spirit and scope of the present invention, and these fall within the scope of the present invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. The method for detecting the abnormal working frequency of the external clock of the chip is characterized by comprising the following steps of:
Acquiring the expected working frequency of the external clock of the chip, the expected working frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
Determining a first low-frequency alarm threshold and a first high-frequency alarm threshold of the frequency sensor according to the expected working frequency of the chip external clock, the expected working frequency of the chip internal clock, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
acquiring the actual working frequency of an external clock of a chip;
Determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor;
Determining a second low-frequency alarm threshold and a second high-frequency alarm threshold of the frequency sensor according to the actual working frequency of the clock in the chip;
and determining whether the working frequency of the clock outside the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor.
2. The method for detecting abnormal operating frequency of an external clock of a chip according to claim 1, wherein determining the first low-frequency alarm threshold and the first high-frequency alarm threshold of the frequency sensor according to the expected operating frequency of the external clock of the chip, the expected operating frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor, and the frequency detection accuracy of the frequency sensor comprises:
the first low frequency alarm threshold L 1 and the first high frequency alarm threshold H 1 of the frequency sensor are calculated according to the following formulas:
；
Wherein d is the frequency division coefficient of the frequency sensor; f 1 is the expected operating frequency of the chip internal clock; f 1 is the expected operating frequency of the chip external clock; p is the frequency detection accuracy of the frequency sensor.
3. The method for detecting abnormal operating frequency of external clock of chip according to claim 1, wherein determining the actual operating frequency of internal clock of chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual operating frequency of external clock of chip and the frequency division coefficient of the frequency sensor comprises:
The actual operating frequency f 2 of the internal clock of the chip is calculated according to the following formula:
；
Wherein F 2 is the actual working frequency of the external clock of the chip; p is the frequency detection precision of the frequency sensor; d is the frequency division coefficient of the frequency sensor; l 1 is a first low-frequency alarm threshold of the frequency sensor.
4. The method for detecting abnormal operating frequency of external clock of chip according to claim 1, wherein determining the actual operating frequency of internal clock of chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual operating frequency of external clock of chip and the frequency division coefficient of the frequency sensor comprises:
The actual operating frequency f 2 of the internal clock of the chip is calculated according to the following formula:
；
Wherein F 2 is the actual working frequency of the external clock of the chip; p is the frequency detection precision of the frequency sensor; d is the frequency division coefficient of the frequency sensor; h 1 is the first high-frequency alarm threshold of the frequency sensor.
5. The method for detecting abnormal operating frequency of an external clock on a chip according to claim 3 or 4, wherein determining the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor according to the actual operating frequency of the internal clock on the chip comprises:
the second low frequency alarm threshold L 2 and the second high frequency alarm threshold H 2 of the frequency sensor are calculated according to the following formulas:
；
Wherein d is the frequency division coefficient of the frequency sensor; f 2 is the actual working frequency of the clock inside the chip; f 1 is the desired operating frequency of the chip external clock.
6. The method for detecting an abnormality of an operating frequency of an external clock of a chip according to claim 1, wherein the determining whether the operating frequency of the external clock of the chip is abnormal based on the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor includes:
Enabling the frequency sensor;
After enabling the frequency sensor, dividing the frequency of the external clock of the chip to obtain a clock div_clk of the external clock of the chip after the frequency division of the external clock of the chip in the internal clock domain of the chip;
Counting the single pulse length of div_clk to obtain the cycle number cnt of the internal clock of the chip contained in one single pulse length of div_clk;
And determining the abnormal working frequency of the external clock of the chip according to the cycle number cnt.
7. The method for detecting an abnormality of an operating frequency of an external clock of a chip according to claim 6, wherein determining whether the operating frequency of the external clock of the chip is abnormal based on the second low-frequency alarm threshold and the second high-frequency alarm threshold of the frequency sensor comprises:
Delaying the enabling signal of the frequency sensor for two clock cycles under the clock domain in the chip, detecting the rising edge of the enabling signal delayed for two clock cycles, and enabling the frequency sensor at the rising edge of the enabling signal;
And/or after enabling the frequency sensor, adopting a counter to start counting at the rising edge of each chip external clock, turning over the clock after the frequency division of the chip external clock and resetting the counter when the counting reaches a preset frequency division coefficient to obtain a clock div_clk after the frequency division of the chip external clock under the chip internal clock domain;
And/or detecting rising edges and falling edges of the div_clk under the internal clock domain of the chip, setting a counter, and counting the single pulse length of the div_clk by adopting the internal clock of the chip to obtain a cycle number cnt containing the internal clock of the chip in one single pulse length of the div_clk;
and/or determining that the working frequency of the clock outside the chip is abnormal under the condition that cnt is larger than the second low-frequency alarm threshold or cnt is smaller than the second high-frequency alarm threshold.
8. A method for detecting a chip frequency anomaly, comprising: the detection result of whether the operating frequency of the external clock of the chip is abnormal or not, which is obtained by the method for detecting the operating frequency abnormality of the external clock of the chip according to any one of claims 1 to 7, is used as the detection result of whether the operating frequency of the chip is abnormal or not.
9. An abnormality detection system for an operating frequency of an external clock of a chip, comprising:
The first acquisition module is used for acquiring the expected working frequency of the external clock of the chip, the expected working frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
the first determining module is used for determining a first low-frequency alarm threshold value and a first high-frequency alarm threshold value of the frequency sensor according to the expected working frequency of the external clock of the chip, the expected working frequency of the internal clock of the chip, the frequency division coefficient of the frequency sensor and the frequency detection precision of the frequency sensor;
The second acquisition module is used for acquiring the actual working frequency of the external clock of the chip;
the second determining module is used for determining the actual working frequency of the clock inside the chip according to the first low-frequency alarm threshold or the first high-frequency alarm threshold, the actual working frequency of the clock outside the chip and the frequency division coefficient of the frequency sensor;
The third determining module is used for determining a second low-frequency alarm threshold value and a second high-frequency alarm threshold value of the frequency sensor according to the actual working frequency of the clock in the chip;
And the fourth determining module is used for determining whether the working frequency of the clock outside the chip is abnormal according to the second low-frequency alarm threshold value and the second high-frequency alarm threshold value of the frequency sensor.
10. A computer-readable storage medium storing a computer program; the computer program, when executed by a processor, implements the steps of the method for detecting an abnormality of an operating frequency of an external clock of a chip as claimed in any one of claims 1 to 7.
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