CN118523624A

CN118523624A - Implementing active clamp flyback converter with improved efficiency

Info

Publication number: CN118523624A
Application number: CN202410174015.3A
Authority: CN
Inventors: R·卡里; H·莱; P·沙阿
Original assignee: Cypress Semiconductor Corp
Current assignee: Cypress Semiconductor Corp
Priority date: 2023-02-20
Filing date: 2024-02-07
Publication date: 2024-08-20

Abstract

An implementation of an active clamp flyback converter with improved efficiency is described. In one embodiment, an apparatus includes an Active Clamp Flyback (ACF) flyback converter. The ACF flyback converter comprises: a primary side including a High Side (HS) switch, a Low Side (LS) switch, and an ACF driver; and a secondary side including a secondary side controller configured to: obtaining at least one set of input parameters including a set of subsystem parameters associated with the subsystem and a set of system parameters associated with the initial configuration; determining a set of output parameters based on the set of input parameters; and controlling operation of the ACF flyback converter based on the set of output parameters.

Description

Implementing active clamp flyback converter with improved efficiency

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional application 63/447,008 filed on month 2 and 20 of 2023 and entitled "IMPLEMENTING ACTIVE CLAMP FLYBACK CONVERTERS WITH IMPROVED EFFICIENCY", the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to Integrated Circuits (ICs) that control power delivery to electronic devices.

Background

Flyback converters are systems that can generate some Direct Current (DC) output from a given input provided by a power supply. For example, the input may be an Alternating Current (AC) input provided by an AC source, and the flyback converter may be an AC-to-DC (AC-DC) flyback converter. As another example, the input may be a DC input provided by a DC source, and the flyback converter may be a DC-to-DC (DC-DC) flyback converter. Some flyback converters may be used to implement the power adapter. For example, the power adapter may be an AC-DC power adapter for converting an input AC current or voltage to a DC current or voltage that may be used by an electronic device (i.e., a load). As another example, the power adapter may be a DC-DC power adapter (e.g., by modifying an input DC current or voltage) for converting the input DC current or voltage into a DC current or voltage that may be used by the electronic device (e.g., to regulate the DC current). The power adapter may support power delivery for various types of electronic devices (e.g., smart phones, tablets, notebooks, laptops, hubs, chargers, adapters, etc.).

Drawings

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

Fig. 1 is a block diagram of a high-level overview of a flyback converter according to some embodiments.

Fig. 2 is a block diagram of a system implementing a flyback converter, according to some embodiments.

Fig. 3 is an illustration of a system level diagram showing generating a signal for a switch of a flyback converter, according to some embodiments.

Fig. 4 is a schematic diagram of exemplary secondary side circuitry of a power adapter, according to some embodiments.

Fig. 5 is a block diagram illustrating an Integrated Circuit (IC) system for power delivery in accordance with some embodiments.

Fig. 6 is a flow chart of a method of implementing an Active Clamp Flyback (ACF) type converter with improved efficiency, in accordance with some embodiments.

Detailed Description

Various embodiments of techniques for implementing an Active Clamp Flyback (ACF) flyback converter with improved efficiency are described herein. The flyback converter may include a primary side having a current input, the primary side including a power supply, at least one primary side capacitor, a primary side controller, and at least one primary side switch. For example, the power source may be an AC power source. The at least one primary side switch may comprise a power switch. In some embodiments, the power switch is a Field Effect Transistor (FET). The flyback converter may also include a secondary side having at least one secondary side switch and at least one secondary side capacitor, and may include or be coupled to a load. For example, the at least one secondary side switch may comprise a diode. Flyback transformers separate the primary side from the secondary side to achieve electrical isolation and prevent direct current from flowing from the primary side to the secondary side. More specifically, the flyback transformer may include a primary side winding and a secondary side winding.

The primary side may also include a primary side controller coupled to the power switch to control operation of the power switch (e.g., turn the power switch on and off). By controlling the operation of the power switch, the state of the flyback converter can be controlled, thereby switching on and off the power delivery. More specifically, the flyback converter may cycle between an on state and an off state.

For example, when the primary side controller closes the power switch (e.g., turns on the FET), the flyback converter is placed in an on state. When the flyback converter is in an on state, the primary side winding of the flyback transformer is connected to the power supply, and primary current from the power supply flows to the primary side winding of the flyback transformer. The primary current charges the primary side winding of the flyback transformer and increases the magnetic flux incident on the secondary side winding of the flyback transformer, which induces a negative electromotive force (emf) in the secondary side winding of the flyback transformer according to faraday's law. The diode on the secondary side prevents current flow from the flyback transformer due to reverse bias caused by the negative emf. Instead, at least one secondary side capacitor may deliver power to the load. When the primary side controller turns off the power switch (e.g., turns off the FET), the flyback converter is placed in an off state. When the flyback converter is in an off state, the primary side winding of the flyback transformer is disconnected from the power supply, and primary current from the power supply stops flowing to the primary side winding of the flyback transformer. This reduces the magnetic flux incident on the secondary side winding, which induces a positive emf in the secondary side winding of the flyback transformer according to faraday's law. The diode on the secondary side allows secondary current to flow from the flyback transformer due to forward bias caused by the positive emf. The secondary current is used to charge at least one secondary side capacitor and deliver power to the load.

In some implementations, the secondary side further includes a secondary side controller. The secondary side controller may include a signal generator to generate a signal. For example, the signal may include pulses (e.g., a signal having a fast rise time, followed by a constant voltage period, and followed by a fast fall time). In some implementations, the secondary side controller may utilize Pulse Width Modulation (PWM) to generate the PWM signal. PWM may be used to control (e.g., reduce) the amplitude of the pulses of the control signal.

In some embodiments, the secondary side controller may transmit a control signal to the primary side controller that may be used to control the power switch. More specifically, a signal transformer may be placed between the primary side and the secondary side, and the secondary side controller may transmit a control signal to the primary side controller via the signal transformer. For example, the signal transformer may be a pulse transformer. Thus, the signal transformer may act as a communication link between the primary side controller and the secondary side controller.

The secondary side controller may operate according to a switching frequency, which may be fixed (e.g., static) or variable (e.g., dynamic). The flyback converter may be configured to operate in one or more modes of operation based on an amount of time between receipt of the control signal according to the switching frequency. Flyback converters may need to be designed to support operation in one or more of the modes of operation.

One example of an operating mode is a Continuous Conduction Mode (CCM). The flyback converter operates in CCM if the primary side controller causes the power switch to change from open to closed before the primary side winding has sufficient time to fully discharge. In other words, the primary side controller receives a control signal for closing the open power switch before the full discharge of the primary side winding of the flyback transformer. Thus, when operating in CCM, the current in the primary side winding of the flyback transformer is never zero or near zero.

Another example of an operating mode is Discontinuous Conduction Mode (DCM). The flyback converter operates in DCM if the primary side controller causes the power switch to change from open to closed after an amount of time sufficient to fully discharge the primary side conductor. In other words, after a complete discharge of the primary side winding of the flyback transformer, the primary side controller receives a control signal for closing the open power switch. Thus, when operating in DCM, the current in the primary side winding of the flyback transformer is zero or near zero for at least a certain amount of time. DCM may occur if the duty cycle of the control signal is sufficiently short and/or the load is sufficiently small. Duty cycle refers to the amount of active period during a waveform (e.g., signal) or switching cycle of a system. The duty cycle may be determined based on a ratio of the active time to the total period. In some implementations, the duty cycle is expressed as a ratio (e.g., a fraction or decimal). In some embodiments, the duty cycle is expressed as a percentage. For example, the duty cycle of the waveform may be determined based on the ratio of the pulse width of the waveform to the total period of the signal.

Operation in DCM may be more efficient than, for example, in CCM due, at least in part, to reduced reverse recovery losses for the diode. Provided that the current through the primary side winding is efficiently delivered, improved efficiency may be achieved. For example, an appropriate duty cycle may be selected during DCM operation to improve power delivery efficiency. Furthermore, flyback converters operating in DCM employ Zero Current Switching (ZCS) and/or Zero Voltage Switching (ZVS), which may further improve efficiency. However, DCM may cause a greater amount of electromagnetic interference (EMI) and/or noise than CCM, and thus flyback converters operating in DCM may require additional circuitry to handle EMI and/or noise.

Yet another example of an operating mode is a critical conduction mode (CrCM). The flyback converter operates at CrCM if the primary side controller causes current to be delivered to the primary side winding of the flyback converter at the time of full discharge of the primary side winding of the flyback converter (e.g., once the current in the primary side winding of the flyback converter is zero). In other words, the power switch is closed (e.g., turned on) almost immediately after the primary side winding of the flyback converter is fully discharged. By employing a suitably selected duty cycle for the control signal CrCM, this may occur, which may be such that the current is fed to the primary side winding of the flyback converter at substantially the correct time after the power switch is turned off.

The switching frequency may be related to the size of the power supply that can be supported. For example, a higher switching frequency may correspond to a smaller power supply size. However, one problem that may exist is flyback transformer leakage inductance. At some point, the flyback transformer leakage inductance energy may be high enough to damage the flyback converter. Typically, the energy of the flyback transformer leakage inductance can be dissipated in a passively clamped snubber resistor on the primary side of the flyback converter.

In some embodiments, the flyback converter is an ACF flyback converter that includes an active clamp. For example, an ACF flyback converter may include a high-side (HS) switch (Q _HS) and a low-side (LS) switch (Q _LS). For example, the HS switch and the LS switch may each be a FET. More specifically, HS switches may be referred to as ACF switches and may be included in the active clamp, and LS switches may correspond to power switches. The ACF driver may be coupled to the HS switch to control operation of the HS switch. For example, the ACF driver may be a gate driver coupled to the gate of the HS switch.

The ACF converter may operate in ACF mode. When operating in ACF mode, the flyback converter may actively store the energy of the flyback converter leakage inductance in the active clamp. This stored energy may then be provided to the load during the switching cycle, which may improve flyback converter efficiency. Therefore, ACF flyback converters can reduce or eliminate snubber resistor losses.

The efficiency of the flyback converter may be further improved by implementing ZVS and/or ZCS. More specifically, ZVS and/or ZCS may achieve higher switching frequencies and smaller power supply sizes. Improved efficiency under a combination of line and load can be achieved by determining the optimal on-time of the HS switch. This may be difficult to determine in the secondary side controller because the secondary side controller has no direct access to the primary drain node, and the voltage at the primary drain node can be used to determine the optimal on-time of the HS switch. Lower on-times may not achieve ZVS and/or ZCS on the primary drain at lower VBUS, higher VIN, and may increase noise on the primary drain at higher VBUS. Because a larger on-time may increase transformer losses, it may reduce efficiency at higher VBUS. Furthermore, to achieve optimal efficiency at the on-line input/VBUS, the on-time may need to vary with the input line voltage and the output VBUS voltage. Using a fixed value of on-time optimized for a particular combination of wire and load can cause efficiency losses at other voltages. This is especially true in applications where the output VBUS voltage may vary from about 3V to about 30V and the AC input line may vary from about 80V to about 380V. Thus, flyback converter efficiency can be improved by optimizing the on-time of the HS switch without having to track the primary drain node voltage.

Various embodiments of techniques for implementing ACF flyback converters with improved efficiency are described herein. The embodiments described herein may implement an adaptive turn-on scheme for HS switches that may be used for ACF flyback converters capable of operating in ACF mode. The secondary side controller may use firmware to control the duration of the HS switch based on VBUS and V _IN. Equations for optimizing efficiency may be fed into the firmware, which may be used to optimize efficiency under on-line (V _IN) and load (VBUS) conditions.

Embodiments described herein may provide a secondary side controller that may implement a firmware-based HS switching pulse width scheme to improve efficiency at input and output voltages. For example, the secondary side controller may include a flyback controller operatively coupled to the subsystem and the firmware. In some embodiments, at least one of the subsystem or firmware is included in a flyback controller. The subsystem may include a line detection circuit, a VBUS measurement unit, a load current measurement unit, and a signal transformer driver (e.g., a pulse transformer driver). The subsystem may send a set of parameters to the firmware. In some embodiments, the set of parameters includes V _IN, load current, and V _OUT. In some embodiments, this set of parameters may be received on the fly to support real-time or near real-time processing.

In some embodiments, the secondary side controller may control the on time of the HS switch. The firmware may be programmed with an equation for the pulse width required to achieve ZVS. For example, the number of the cells to be processed,

Where T _{req_zvs} is the pulse width, L _pri is the primary inductance relative to the flyback transformer, C _pri is the equivalent capacitance relative to the primary drain node, N is the turns ratio corresponding to the flyback transformer, V _IN is the input voltage value corresponding to the AC voltage input, and V _OUT is the output DC voltage value. In some embodiments, V _IN is a Root Mean Square (RMS) value derived from the AC voltage input. IN some embodiments, V _OUT corresponds to VBUS_IN.

To improve efficiency, the LS switch should be turned on for a certain interval after the HS switch is turned off. Otherwise, the primary drain node may reach a high voltage and a short circuit condition may exist. The duration T _{dur_zvs} of the primary drain hold at 0V may be defined by the following equation:

the secondary side controller may use equation (2) to determine the dead time of the HS switch, which may be used to control when the LS switch (i.e., the power switch) is turned on/off. More specifically, dead time refers to the amount of time it takes for the HS switch to go from a positive (on) voltage to 0V. For example, equation (2) may be employed to program firmware to determine T _{dur_zvs}.

Flyback transformer loss (P _T) may be a function of HS switch on-time. ACF driver loss (P _D) may be fed into the firmware so that power loss due to switching action (P _Loss) may be determined as the sum of P _T and P _D. In addition, the power gain as a function of the line and load components as a function of the on-time of the HS switch may be stored in firmware as a function (P _ACF). In some embodiments, if the power loss due to the switching action of the HS switch is higher than the power gain at lower loads, the firmware may switch the HS switch once in multiple cycles to improve efficiency at low loads.

As described herein, advantages of implementing ACF flyback converters with improved efficiency include improved efficiency under on-line (V _IN) and load (VBUS) conditions, no changes in hardware across different client applications/boards, and the possibility of skipping HS pulses to improve efficiency for lower loads. Further details regarding the implementation of an ACF flyback converter with improved efficiency will be described below with reference to fig. 1-6.

In some embodiments, the flyback converter is implemented within a power adapter. For example, the power adapter may be an AC-DC power adapter. The embodiments described herein may also be implemented in other types of power adapters, power converters, power delivery circuits, and the like. The power adapters described herein may include a power control subsystem having hardware, firmware, or any combination thereof. The power adapters described herein may be coupled to an electronic device (e.g., a load) to enable power delivery. Examples of such electronic devices include, but are not limited to: personal computers (e.g., laptop computers, notebook computers, etc.), mobile computing devices (e.g., tablet computers, electronic reader devices, etc.), mobile communication devices (e.g., smart phones, cellular phones, personal digital assistants, messaging devices, pocket PCs, etc.), connection and charging devices (e.g., hubs, docking stations, adapters, chargers, etc.), audio/video/digital recording and/or playback devices (e.g., cameras, voice recorders, handheld scanners, monitors, etc.), and other similar electronic devices that may communicate, charge batteries, and/or power delivery using connectors (interfaces). Embodiments described herein may be used for AC-DC power adapters, gaN-based power adapters operating at 600kHz or at frequencies above 600kHz, power adapters with primary or secondary side controllers, power adapters operating in an operational mode (e.g., DCM, CCM, crCM, quasi-resonant mode (QR)), and the like.

In some embodiments, the power adapter is a Universal Serial Bus (USB) power delivery (USB-PD) power adapter configured to operate with a USB-enabled electronic device or system. The USB-enabled electronic device or system may conform to at least one release version of the USB specification. Examples of such USB specifications include, but are not limited to, USB specification revision 2.0, USB 3.0 specification, USB 3.1 specification, and/or various supplements thereof (e.g., on-The-Go or OTG), version and error tables. The USB specification typically defines the characteristics (e.g., attributes, protocol definitions, type of transaction, bus management, programming interfaces, etc.) required for the design and construction of standard communication systems and peripherals of a differential serial bus. For example, a USB-enabled peripheral device attaches to a USB-enabled host device through a USB port of the host device to form a USB-enabled system. The USB 2.0 port includes a 5V supply voltage line (denoted VBUS), a differential pair of data lines (denoted d+ or DP and D-or DN), a ground line (denoted GND) for power return. The USB 3.0 port also provides VBUS, D+, D-and GND lines to be backward compatible with USB 2.0. In addition, to support faster differential buses (USB ultra-high speed buses), the USB 3.0 port also provides a differential pair of transmitter data lines (denoted SSTX + and SSTX-), a differential pair of receiver data lines (denoted SSRX + and SSRX-), a power line for power (denoted DPWR), and a ground line for power return (denoted DGND). The USB 3.1 port provides the same line as the USB 3.0 port for backward compatible USB 2.0 and USB 3.0 communications. Moreover, it extends the performance of the ultra-high speed bus by a set of features called enhanced ultra-high speed.

The latest technology for USB connectors is defined in each release and/or version of the USB Type-C ^TM specification (e.g., release 1.0, release 1.1, etc.) (the so-called USB Type-C ^TM).USB Type-C^TM specification defines a Type-C ^TM socket capable of supporting USB communications and power delivery over newer USB power delivery protocols defined in each revision/version of the USB-PD specification), Type-C ^TM plug and Type-C ^TM cable. Examples of USB Type-C ^TM functions and requirements may include, but are not limited to, data and other communications according to USB 2.0 and USB 3.0/3.1/3.2, electro-mechanical definition and performance requirements for Type-C ^TM cables, electro-mechanical definition and performance requirements for Type-C ^TM sockets, and, The electromechanical definition and performance requirements of Type-C ^TM plug, the requirements of Type-C ^TM to legacy cable components and adapters, the requirements for Type-C ^TM based device detection and interface configuration, the requirements for optimized power delivery for Type-C ^TM connectors (also referred to as USB-C connectors), and the like. According to the USB Type-C ^TM specification, the Type-C ^TM ports provide VBUS, D+, D-, GND, SSTX+, SSTX-, SSRX + and SSRX-wires, etc. In addition, the Type-C ^TM port also provides a sideband usage (denoted SBU) line for signaling of sideband functions and a configuration channel (denoted CC) line for discovery, configuration and management of connections across Type-C ^TM cables. the Type-C ^TM port may be associated with a Type-C ^TM plug and/or a Type-C ^TM receptacle. The Type-C ^TM plug and Type-C ^TM receptacle are designed to be reversible pairs that operate regardless of plug-to-receptacle orientation, and thus are easy to use. thus, a standard USB Type-C ^TM connector configured as a standard Type-C ^TM plug or socket provides for four VBUS lines, four ground return (GND) lines, two D+ lines (DP 1 and DP 2), two D-lines (DN 1 and DN 2), two SSTX + lines (SSTXP and SSTXP 2), a connector for a connector, Pins of two SSTX-lines (SSTXN 1 and SSTXN), two SSRX + lines (SSRXP 1 and SSRXP 2), two SSRX-lines (SSRXN 1 and SSRXN), two CC lines (CC 1 and CC 2), two SBU lines (SBU 1 and SBU 2), and the like. The embodiments described herein may be used for a power adapter solution with Type-C ^TM PD functionality.

Some USB-enabled electronic devices may conform to a particular revision and/or version of the USB-PD specification (e.g., revision 1.0, revision 2.0, revision 3.0, etc., or later revisions/versions). The USB-PD specification defines a standard protocol designed to implement the maximum functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB Type-C ^TM cable via a USB Type-C ^TM port. The USB-PD specification also describes the architecture, protocols, power supply behavior, parameters, and wiring required to manage power delivery over USB Type-C ^TM cable at power up to 100W. According to the USB-PD specification, devices with USB Type-C ^TM ports (e.g., USB enabled devices) may negotiate more current and/or higher/lower voltages over the USB Type-C ^TM cable than allowed in the older USB specification (e.g., USB 2.0 specification, USB 3.1 specification, USB battery charging specification revision 1.1/1.2, etc.). For example, the USB-PD specification defines requirements for a PD agreement that may be negotiated between a pair of USB-enabled devices. The PD agreement may specify both a power level and a direction of power transfer that both devices are able to accommodate, and the power level and direction of power transfer may be dynamically renegotiated (e.g., without unplugging the device) upon request by either device and/or in response to various events and conditions (e.g., power role exchange, data role exchange, hard reset, power failure, etc.). According to the USB-PD specification, an electronic device is typically configured to deliver power to another device through a power path configured on a USB VBUS line.

Fig. 1 is a block diagram of a flyback converter 100 according to some embodiments. In some embodiments, flyback converter 100 is included in a power adapter. For example, the power adapter may be an AC-DC power adapter. For example, the power adapter may be a USB-PD power adapter. In some embodiments, other converters may be used, such as a switching converter, and the like.

Flyback converter 100 may include a primary side 110, a secondary side 120, a flyback transformer 130, and a signal transformer 140. In some embodiments, the signal transformer 140 is a pulse transformer. As shown, the primary side 110 may include a DC output component 112, an HS switch 114, a primary side controller 116, and an LS switch 118. In some embodiments, HS switch 114 and LS switch 118 are FETs. For example, the HS switch 114 may be an ACF switch and the LS switch 118 may be a power switch that can be controlled by the primary side controller 116. The HS switch 114 may be included in the active clamp of the flyback converter 100. For example, an ACF driver may be coupled to the HS switch 114 to control operation of the HS switch 114. In some embodiments, HS switch 114 is a FET and the ACF driver is a gate driver, and the gate of HS switch 114 may be coupled to the ACF driver. The secondary side 120 may include (or be coupled to) a load 122, a capacitor 124, and a secondary side controller 126. In some embodiments, load 122 represents an electronic device connected to flyback converter 100. For example, load 122 may represent an electronic device connected to a power adapter implementing flyback converter 100.

Flyback transformer 130 may have a primary side winding coupled to primary side 110 and a secondary side winding coupled to secondary side 120. For example, the DC output component 112 may be coupled to a first end of the primary side winding and the LS switch 118 may be coupled to a second end of the primary side winding. For example, if LS switch 118 is a FET, the second end of the primary winding of flyback transformer 130 may be coupled to the source/drain of LS switch 118. The signal transformer 140 may have a primary side winding coupled to the primary side 110 and a secondary side winding coupled to the secondary side 120.

An exemplary operation of flyback converter 100 will now be described. The DC output component 112 may receive AC input from an AC input source and convert the AC input to a corresponding DC output. For example, the DC output component 112 may include a rectifier to generate a DC output. In some embodiments, the rectifier is a bridge rectifier including a set of diodes. In some embodiments, the DC output component 112 includes an electromagnetic interference (EMI) filter. More details regarding the DC output section 112 are described below with reference to fig. 2.

The primary side controller 116 may control the operation of the LS switch 118 to control the state of the flyback converter 100. For example, when the primary side controller 116 closes the LS switch 118 (e.g., turns on the FET), the flyback converter 100 is placed in an on state. When flyback converter 100 is in an on state, the DC output generated by DC output component 112 flows to the primary side winding of flyback transformer 130. The DC output generated by the DC output section 112 charges the primary side winding of the flyback transformer 130 and increases the magnetic flux incident on the secondary side winding of the flyback transformer 130, which induces a negative emf in the secondary side winding of the flyback transformer 130 according to faraday's law. Diode 124 prevents current flow from flyback transformer 130 due to reverse bias caused by negative emf. Instead, capacitor 124 may deliver power to load 122. When the primary side controller 116 turns off the LS switch 118 (e.g., turns off the FET), the flyback converter 100 is placed in an off state. When flyback converter 100 is in an off state, the primary side winding of flyback transformer 130 is disconnected from the power supply and the DC output generated by DC output section 112 stops flowing to the primary side winding of flyback transformer 130. This reduces the magnetic flux incident on the secondary side winding of flyback transformer 130, which induces a positive emf in the secondary side winding of flyback transformer 130 according to faraday's law. Diode 124 allows current to flow from flyback transformer 130 due to forward bias caused by the positive emf. This secondary current is used to charge capacitor 124 and deliver power to load 122.

The secondary side controller 126 may include a signal generator to generate a signal. For example, the signal may comprise pulses. The pulses may have a fixed or variable width. In some embodiments, the secondary side controller 126 utilizes PWM to generate the PWM signal. In some embodiments, the secondary side controller 126 may transmit control signals to the primary side controller 116, which may be used to control the LS switch 118. More specifically, the secondary side controller 126 may transmit control signals to the primary side controller via the signal transformer 140.

The control signals generated by the secondary side controller 126 may, when received by the primary side controller 116, cause the primary side controller 116 to control the operation of the LS switch 118. For example, in response to receiving the on control signal, the primary side controller 116 may cause the LS switch 118 to close (e.g., turn on the FET). In response to receiving the off control signal, the primary side controller 116 may cause the LS switch 118 to open (e.g., turn off the FET). For example, if LS switch 118 is a FET, primary side controller 116 may apply an on voltage (e.g., a pulse) to the gate of LS switch 118 to turn on LS switch 118 (e.g., make the source/drain of LS switch 118 low). In some embodiments, the turn-on voltage is about 12V. The primary side controller 116 may apply an off voltage (e.g., a pulse) to the gate of the LS switch 118 to turn off the LS switch 118 (e.g., cause the source/drain of the LS switch 118 to go high).

In some embodiments, the primary side controller 116 includes a comparator or differential amplifier having a pair of input terminals connected to the signal transformer 140 and an output terminal connected to the LS switch 118. The comparator may generate an output signal based on a pair of input signals received from the signal transformer 140, which may be used to control the LS switch 118.

The secondary side controller 126 may send any combination of pulses indicative of a particular bit pattern to the primary side controller 116 without clock synchronization. In one embodiment, the secondary side controller 126 includes a state machine to synchronize each function of the primary side controller 116 that is to be programmed (e.g., calibrated, fine tuned, etc.). The secondary side controller 126 may store other information, such as user-defined settings. For example, user-defined settings related to primary side functions (e.g., over Voltage (OV), under Voltage (UV), over Current (OC), short circuit detection, over Temperature (OT), line voltage, peak current limit, etc.) may be stored in the non-volatile memory of the secondary side controller 126. The firmware of the secondary side controller 126 may transmit this information to the primary side controller 116 at an appropriate time (e.g., at start-up or at a later time at a particular time during operation of the converter) in a similar manner. During no-load conditions, no information about the turn-on of the LS switch 118 need be sent.

The secondary side controller 126 may generate the control signal according to a switching frequency, which may be fixed (e.g., static) or variable (e.g., dynamic). Flyback converter 100 may be configured to operate in one or more modes of operation based on an amount of time between receipt of control signals according to a switching frequency. In some embodiments, the control signal generated by the secondary side controller 126 is a signal sent to the primary side controller 116 via the signal transformer 140 to control the HS switch 114 and/or the LS switch 118 (e.g., to close or open). For example, the primary side controller 116 may include comparators connected to both ends of the primary side winding of the signal transformer 140, and the output of the comparators of the primary side controller 116 may control the HS switch 114 and/or the LS switch 118.

In some embodiments, the secondary side controller 126 implements a firmware-based pulse width scheme with respect to the HS switch 114 to improve efficiency at the input voltage (e.g., V _IN) and the output voltage (e.g., V _OUT). For example, as will be described in greater detail below with reference to fig. 2, the secondary side controller 126 may include a flyback controller that is operably coupled to the subsystem and the firmware. In some embodiments, at least one of the subsystem or firmware is included in a flyback controller. The subsystem may include a line detection circuit, a VBUS measurement unit, a load current measurement unit, and a signal transformer driver (e.g., a pulse transformer driver). The subsystem may send a set of parameters to the firmware. In some embodiments, the set of parameters includes V _IN, load current, and V _OUT. In some embodiments, this set of parameters may be received on the fly to support real-time or near real-time processing.

In some embodiments, the secondary side controller 126 may control the on time of the HS switch 114. The firmware may be programmed with an equation for the pulse width required to achieve ZVS. For example, the pulse width may be determined using equation (1).

To improve efficiency, the LS switch 118 should be turned on for a certain interval after the HS switch 114 is turned off. Otherwise, the primary drain node may reach a high voltage. For example, equation (2) may be used to determine the duration T _{dur_zvs} that the primary drain remains at 0V. The secondary side controller 126 may use T _{dur_zvs} to determine the dead time of the HS switch 114, which may be used to control when to close/open the LS switch 118. For example, equation (2) may be employed to program firmware to determine T _{dur_zvs}.

Flyback transformer loss (P _T) may be a function of the on-time of the HS switch 114. ACF driver loss (P _D) may be fed into the firmware so that power loss due to switching action (P _Loss) may be determined as the sum of P _T and P _D. In addition, the power gain as a function of the on-time of the line and load components with the HS switch 114 may be stored in firmware as a function (P _ACF). In some embodiments, if the power loss due to the switching action of the HS switch 114 is higher than the power gain at lower loads, the firmware may switch the HS switch 114 once in multiple cycles to improve efficiency at low loads. Further details regarding the implementation of an active clamp flyback converter with improved efficiency will now be described below with reference to fig. 2.

Fig. 2 is a block diagram of a system 200 according to some embodiments. In some embodiments, system 200 includes a power adapter. For example, system 200 may include a USB-PD power adapter. The system 200 includes a flyback converter, such as flyback converter 100. In some embodiments, flyback converter 100 is an ACF flyback converter that includes ACFs to operate in ACF mode.

For example, the system 200 may include a primary side 110, the primary side 110 having a DC output component 112, an HS switch (e.g., Q _HS) 114, a primary side controller 116, an LS switch (e.g., Q _LS) 118, and a Primary Drain Node (PDN) 210. In some embodiments, and as shown in fig. 2, HS switch 114 and LS switch 118 are FETs. The ACF driver 220 may be coupled to the HS switch 114 to form at least a portion of the active clamp of the flyback converter. In some embodiments, ACF driver 220 may be a gate driver coupled to the gate of HS switch 114 (e.g., if HS switch 114 is a FET). The system 200 may also include a secondary side 120, and the secondary side 120 may include a load 122, a capacitor 124, and a secondary side controller 126 or may be coupled to the load 122, the capacitor 124, and the secondary side controller 126. The secondary side 120 may also include a sense NODE (sr_node) 230 and a VBUS NODE 240. In some embodiments, the sense node 230 is a DRAIN node (srdrain). In this illustrative example, load 122 is a USB connector (e.g., USB Type-C ^TM connector).

In some embodiments, the DC output component 112 may be coupled to an AC source 202 that provides an AC input. For example, the DC output component 112 may include a rectifier 204 coupled to the AC source 202 to generate a DC output from an AC input received from the AC source 202. In some embodiments, rectifier 204 is a bridge rectifier that includes a set of diodes. In the illustrative example shown in fig. 2, rectifier 204 is a bridge rectifier that includes four diodes. However, such examples should not be considered limiting. In some embodiments, and as shown in fig. 2, the DC output component 112 may also include an EMI filter 206.

The system 200 may also include a flyback transformer 130 and a signal (e.g., pulse) transformer 140. Flyback transformer 130 may have any suitable polarity between its primary side winding and its secondary side winding. The polarity of the transformer may correspond to the phase offset implemented by the transformer between its primary side winding and its secondary side winding. In some embodiments, and as indicated by the point orientation, flyback transformer 130 implements a 180 ° phase offset between the primary side winding and the secondary side winding (i.e., the current/voltage of the two windings rise and fall together).

The signal transformer 140 may have any suitable polarity between its primary side winding and its secondary side winding. In some embodiments, and as indicated by the point orientation, the signal transformer 140 implements a 0 ° phase offset between the primary side winding and the secondary side winding (i.e., the current/voltage of one winding rises and the current/voltage of the other winding falls). Thus, in some embodiments, the system 200 includes an AC-DC power adapter that implements an AC-DC flyback converter.

In some embodiments, the secondary side controller 126 implements a firmware-based pulse width scheme with respect to the HS switch 114 to improve efficiency at the input voltage (e.g., V _IN) and the output voltage (e.g., V _OUT). V _IN is the input voltage value corresponding to AC source 202 and V _OUT is the output voltage value. In some embodiments, V _IN is an RMS value derived from the AC voltage input. IN some embodiments, V _OUT corresponds to VBUS_IN node 235.

More specifically, the firmware-based pulse width scheme may be implemented based on information derived from the sense node 230 and the VBUS node 240. For example, and as will now be described in greater detail below with reference to fig. 3, the secondary side controller 126 may include: a flyback controller operably coupled to the subsystem that can obtain a set of subsystem parameters including information derived from the sense node 230 and the VBUS node 240; and firmware that may maintain a set of functions for determining a set of output parameters based at least in part on the set of subsystem parameters.

Fig. 3 is a block diagram of an exemplary portion of the secondary side controller 126 showing a system level diagram for generating signals for a switch, in accordance with some embodiments. For example, the signal may be an ACF signal for ACFFET. As shown, the secondary side controller 126 may include a subsystem 310, firmware 320, and a flyback controller 330. In some embodiments, at least one of subsystem 310 or firmware 320 is included in flyback controller 330.

Subsystem 310 may include various components. For example, subsystem 310 may include a line detection circuit 312, a VBUS measurement component 314, a load current measurement component 316, and a signal (e.g., pulse) transformer driver 318. Subsystem 310 may send a set of subsystem parameters to firmware 320. In some embodiments, the set of subsystem parameters includes V _IN, load current, and V _OUT. In some embodiments, the set of subsystem parameters may be received on the fly to support real-time or near real-time processing.

Firmware 320 may also receive an initial configuration 340, where initial configuration 340 may include a set of system parameters 342. In some embodiments, the set of system parameters 342 includes L _pri、C_pri and N. L _pri is the primary inductance relative to the flyback transformer (e.g., flyback transformer 130), C _pri is the equivalent capacitance relative to the primary drain node (e.g., PDN 210), and N is the turns ratio corresponding to the flyback transformer (e.g., flyback transformer 130). Thus, the set of subsystem parameters and the set of system parameters 342 may together form a set of input parameters.

In some embodiments, the secondary side controller 126 may control the on-time of an HS switch of the flyback converter (e.g., the HS switch 114 in fig. 1-2). Firmware 320 may be programmed with a function, denoted by f (T _{req_zvs}), for determining T _{req_zvs} required to implement ZVS. For example, equation (1) may be employed to program firmware to determine T _{req_zvs}.

To improve efficiency, the LS switch of the flyback converter (e.g., LS switch 118 in fig. 1-2) should be turned on for a certain interval after the HS switch is turned off. Otherwise, the primary drain node (e.g., PDN 210) may reach a high voltage. Firmware 320 may be programmed with a function for determining T _{dur_zvs}, represented by f (T _{dur_zvs}). For example, equation (2) may be employed to program firmware 320 to determine that T _{dur_zvs}.T_{dur_zvs} may be used to determine the dead time of the HS switch, which may be used by the flyback controller to control the operation of the LS switch.

Flyback transformer loss (P _T) may be a function of the on-time of the HS switch. ACF driver loss (P _D) may be fed into firmware 320 so that power loss due to switching action (P _Loss) may be determined as the sum of P _T and P _D. In addition, the power gain as a function of the on-time of the line and load components with the HS switch may be stored in firmware 320 as a function, represented by f (power gain). In some embodiments, if the power loss due to the switching action of the HS switch 114 is higher than the power gain at lower loads, the firmware 320 may switch the HS switch once in multiple cycles to improve efficiency at low loads.

Fig. 4 is a schematic diagram of an exemplary portion of a system 400 implementing a flyback converter, according to some embodiments. More specifically, the portion of the system includes the secondary side of the flyback converter. In some embodiments, system 400 includes a power adapter. For example, system 400 may include a USB-PD power adapter. As shown, the system 400 may include the secondary side controller 126, the flyback and signal transformers 130, 140, the sr_node 230, and the load (e.g., USB connector) 122 as described above with reference to fig. 1-2. In addition, system 400 may also include a switching component 410. In some embodiments, the switching component 410 includes a diode (e.g., diode 124 in fig. 1-2). In addition, the switching component 410 may include a transistor (e.g., FET).

The secondary side controller 126 may be provided as an Integrated Circuit (IC) chip that includes subsystems configured in accordance with the ACF control techniques described herein. The secondary side controller 126 may negotiate a PD agreement with a consumer electronic device ("consumer device") (not shown) attached to the load 122 and control the desired VBUS voltage output from the flyback transformer 130 through an output pin ("pwm_drv"). The load 122 is typically associated with a plug (e.g., a USB Type-C ^TM plug), but it should be understood that in various embodiments, the load 122 may alternatively be associated with a socket (e.g., a USB Type-C ^TM socket).

The secondary side controller 126 may be coupled to the vbus_in line and configured to control the operation and state of the power switch by providing control signals to the gate of the switch when a fault condition is detected. The vbus_in line may include a provider switch configured to turn on/off a switching device controlled by a signal from an output pin ("vbus_control") of a gate driver IN the secondary side controller 126. The provider switch may comprise a FET. On one side of the provider switch, a power supply node on the vbus_in line may be coupled to a flyback transformer 130, the flyback transformer 130 being coupled to a bulk capacitor configured to remove the AC component of the power signal. The power supply node may be coupled to an input pin ("vbus_in" pin) of the secondary side controller 126. The output node on the vbus_in line is coupled to the load 122 and to another input pin of the secondary side controller 126 ("vbus_ctrl" pin).

IN operation, the direction of power flow on the vbus_in line is from flyback transformer 130 to consumer devices attached to load 122. When negotiating a PD agreement with the consumer device, the secondary side controller 126 may cause power to be provided to the consumer device at the negotiated voltage and/or current level (e.g., via the provider switch). The high-to-low voltage transition on the vbus_in line may be required when dynamically renegotiating the PD agreement to reduce VBUS voltage and/or current, for example, when the consumer device has completed charging its battery and now only needs power to operate.

Upon detection of a fault condition, a control signal may be sent to disconnect the load 122 from the flyback transformer 130. For example, the provider switch may be turned off by driving the output of VBUS_CTRL to zero. This disconnection may be caused by an overvoltage condition, an overcurrent condition, or other condition that may require disconnection of load 122 from flyback transformer 130 to protect a circuit coupled to load 122.

The embodiments described herein may be implemented in a power delivery system (e.g., a serial bus compatible power device). Examples of serial bus compatible power devices may include Serial Bus Power Delivery (SBPD) devices, USB compatible power devices, and the like. In some embodiments, SBPD devices are USB-PD devices compatible with the USB-PD standard or, more generally, the USB standard. For example, SBPD devices may provide an output voltage based on an input voltage. SBPD apparatus may include various embodiments described herein to facilitate communication between a primary side controller and a secondary side controller. SBPD devices may include a power converter (e.g., an AC-DC converter) and a power control analog subsystem (e.g., a USB-PD controller). The power control analog subsystem may include circuitry, functionality, or both for communicating information across an electrical isolation barrier as described herein. This information may include information for different functions such as OVP (overvoltage protection), UVP (undervoltage protection), OCP (over current protection), SCP (short circuit protection), PFC (power factor correction), SR (synchronous rectification), ACF (active clamp flyback), etc. The information may include fault information for any of these different functions.

In other embodiments, SBPD devices are connected to a power source, such as a wall outlet power source that provides input power. For example, the power source may be an AC source that provides an AC input. In other embodiments, the power source may be a different power source, such as a battery, and may provide DC power to the SBPD devices. The power converter may convert power received from a power source (e.g., convert the received power to VBUS). For example, the power converter may be an AC-DC converter and convert AC power from a power source to DC power. In some embodiments, the power converter is a flyback converter, such as a secondary-controlled flyback converter, that provides electrical isolation between an input (e.g., primary side) and an output (e.g., secondary side). For example, the secondary controlled flyback converter may be a single ended forward converter. In some embodiments, feed forward information on the secondary side may be used to limit the maximum duty cycle that can be transferred to the primary side FET. The maximum duty cycle may vary with the line voltage.

In some embodiments, SBPD devices provide VBUS to the sink device (e.g., via a Configuration Channel (CC) that specifies a specific output voltage and possibly output current). The SBPD device may also provide access to ground potential (e.g., ground) to the sink device. In some embodiments, the provision of VBUS is compatible with the USB-PD standard. The power control analog subsystem may receive VBUS from a power converter. The power control analog subsystem may output VBUS. In some embodiments, the power control analog subsystem is a USB Type-C ^TM controller compatible with the USB Type-C ^TM standard. The power control analog subsystem may provide a system interrupt in response to VBUS and/or vbus_ctrl.

In some embodiments, any of the components of SBPD devices may be part of an IC, or alternatively, any of the components of SBPD devices may be implemented in their own ICs. For example, the power converter and the power control analog subsystem may be discrete ICs with separate packages and pin configurations.

In some embodiments, SBPD devices may provide a complete USB Type-C ^TM and USB-PD port control solution for notebook computers, dongles, monitors, docking stations, power adapters, car chargers, charger kiosks, mobile adapters, and the like.

Embodiments using isolation or level shifters may require some driver circuitry. The driver circuit may be as simple as using the PWM output from the secondary side controller 126 to drive a capacitively coupled controller or optocoupler (also referred to as an optocoupler). When driving the signal transformer 140, the driver circuit may be a complex structure.

FIG. 5 is a block diagram illustrating an Integrated Circuit (IC) system 500 for a USB enabled device for use in USB power delivery, according to some embodiments. The system 500 may include a peripheral subsystem 510, the peripheral subsystem 510 including a plurality of components for use in USB power delivery (USB-PD). Peripheral subsystem 510 may include a peripheral interconnect 511 including a clock module and a Peripheral Clock (PCLK) 512 for providing clock signals to various components of peripheral subsystem 510. Peripheral interconnect 511 may be a peripheral bus, such as a single-level or multi-level advanced high performance bus (AHB), and may provide data and control interfaces between peripheral subsystem 510, central Processing Unit (CPU) subsystem 530, and system resources 540. Peripheral interconnect 511 may include controller circuitry, such as a Direct Memory Access (DMA) controller, that may be programmed to transfer data between peripheral blocks without requiring input, control, or burden from CPU subsystem 530.

Peripheral interconnect 511 may be used to couple components of peripheral subsystem 510 to other components of system 500. Coupled to peripheral interconnect 511 may be a plurality of general purpose input/output (GPIO) 515 for transmitting and receiving signals. GPIO 515 may include circuitry configured to implement various functions such as pull-up, pull-down, input threshold selection, input and output buffer enabling/disabling, single-pass multiplexing, and the like. Also, other functions may be implemented by GPIO 515. One or more timer/counter/pulse width modulator (TCPWM) 517 may also be coupled to the peripheral interconnect and include circuitry for implementing timing circuitry (timer), counters, pulse Width Modulator (PWM) decoders, and other digital functions that may operate on the I/O signals and provide digital signals to system components of system 500. The peripheral subsystem 510 may also include one or more Serial Communication Blocks (SCBs) 519 for implementing a serial communication interface (e.g., I2C, serial Peripheral Interface (SPI), universal asynchronous receiver/transmitter (UART), controller Area Network (CAN), clock expansion peripheral interface (CXPI), etc.).

For USB power delivery applications, peripheral subsystem 510 may include a USB power delivery subsystem 520, with USB power delivery subsystem 520 coupled to peripheral interconnect 511 and including a set of USB-PD modules 521 for use in USB power delivery. The USB-PD module 521 may be coupled to the peripheral interconnect 511 by a USB-PD interconnect 523. The USB-PD module 521 may include: an analog-to-digital conversion (ADC) module for converting various analog signals into digital signals; an error Amplifier (AMP) that regulates the output voltage on the vbus_in line according to the PD protocol; a High Voltage (HV) regulator for converting the supply voltage to a precise voltage (e.g., 3.5-5V) to power the system 500; a low-side voltage sense amplifier (LSCSA) for accurately measuring load current; an over-voltage protection (OVP) module and an over-current protection (OCP) module for providing over-current and over-voltage protection on vbus_in lines with configurable thresholds and response times; one or more gate drivers for external power Field Effect Transistors (FETs) used in USB power delivery in provider and consumer configurations; and a communication channel PHY (CC BB PHY) module for supporting Type-C ^TM Configured Channel (CC) on-line communication. The USB-PD module 521 may further include: a charger detection module for determining that a charging circuit is present and that the charging circuit is coupled to the system 500; and a VBUS discharge module for controlling discharge of a voltage on VBUS. The discharge control module may be configured to be coupled to a power supply node on the vbus_in line or to an output (power sink) node on the vbus_in line and to discharge the voltage on the vbus_in line to a desired voltage level (i.e., a voltage level negotiated IN the PD agreement). The USB power delivery subsystem 520 may also include pads 527 for external connections and electrostatic discharge (ESD) protection circuitry 529, which may be required on the Type-C ^TM port. The USB-PD module 521 may also include a communication module for retrieving and transmitting information, such as control signals from the secondary side controller to the primary side controller.

GPIO 515, TCPWM 517 and SCB 519 may be coupled to an input/output (I/O) subsystem 550, which input/output (I/O) subsystem 550 may include a High Speed (HS) I/O matrix 551 coupled to a plurality of GPIO pins 553. GPIO 515, TCPWM 517 and SCB 519 may be coupled to GPIO pins 553 through HS I/O matrix 551.

The system 500 may also include a Central Processing Unit (CPU) subsystem 530 for processing commands, storing program information, and storing data. CPU subsystem 530 may include one or more processing units 531 to execute instructions and read and write memory locations from and to multiple memories. The processing unit 531 may be a processor adapted to operate in an Integrated Circuit (IC) or a System On Chip (SOC) device. In some embodiments, the processing unit 531 may be optimized for low power operation with a large number of clock gates. In this embodiment, various internal control circuits may be implemented for the processing unit to operate in various power states. For example, processing unit 531 may include a Wake Interrupt Controller (WIC) configured to wake the processing unit from a sleep state, thereby allowing power to be turned off when the IC or SOC is in the sleep state. CPU subsystem 530 may include one or more processors that include flash memory 533, static Random Access Memory (SRAM) 535, and Read Only Memory (ROM) 537. Flash memory 533 may be non-volatile memory (NAND flash, NOR flash, etc.) configured to store data, programs, and/or other firmware instructions. Flash memory 533 may include a read accelerator and may be integrated within CPU subsystem 530 to improve access times. SRAM 535 may be a volatile memory configured to store data and firmware instructions accessible by processing unit 531. ROM 537 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of system 500. SRAM 535 and ROM 537 may have associated control circuitry. The processing unit 531 and memory may be coupled to a system interconnect 539 to route signals from the various components of the CPU subsystem 530 to other blocks or modules of the system 500. The system interconnect 539 may be implemented as a system bus, such as a single-level or multi-level AHB. The system interconnect 539 may be configured to interface to couple various components of the CPU subsystem 530 to one another. A system interconnect 539 may be coupled to peripheral interconnect 511 to provide a signal path between CPU subsystem 530 and components of peripheral subsystem 510.

The system 500 may also include a plurality of system resources 540, the system resources 540 including a power module 541, a clock module 543, a reset module 545, and a test module 547. The power module 541 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, a plurality of voltage References (REF), and PWRSYS modules. In some embodiments, power module 541 may include a controller that allows system 500 to draw power from and/or provide power to external sources at different voltage and/or current levels, and supports operation in different power states (e.g., active, low power, or sleep). In various embodiments, when system 500 inhibits operation, more power states may be implemented to achieve a desired power consumption or output. For example, a secondary side controller implemented on system 500 may access secondary electrical parameters on the secondary side. At low lines and light loads, the secondary side controller may determine the power state such that it is detrimental to turning on the HS switch (e.g., ACF switch). The clock module 543 may include a clock control module, a watchdog timer (WDT), an internal low speed oscillator (ILO), and an Internal Master Oscillator (IMO). The reset module 545 may include a reset control module and an external reset (XRES) module. The test module 547 may include a module for controlling a test mode and entering a test mode, and a test control module for analog and digital functions (digital test and analog DFT).

The system 500 may be implemented in a monolithic (e.g., single) semiconductor die. In other embodiments, various portions or modules of system 500 may be implemented on different semiconductor dies. For example, the memory modules of the CPU subsystem 530 may be on-chip or separate. In other embodiments, separate die circuits may be packaged into a multi-chip module.

The system 500 may be implemented in a number of application contexts to provide USB-PD functionality for it. In each application context, an IC controller or SOC implementing system 500 may be provided and configured in an electronic device (e.g., a USB-enabled device) to perform operations in accordance with the techniques described herein. In one exemplary embodiment, the system 500 may be provided and configured in a Personal Computer (PC) power adapter for a laptop, notebook, or the like. In another exemplary embodiment, the system 500 may be provided and configured in a power adapter (e.g., wall charger) for a mobile electronic device (e.g., smart phone, tablet, etc.). In another exemplary embodiment, the system 500 may be configured and arranged in a wall outlet that is powered through USB Type-A and/or Type-C ^TM ports. In another exemplary embodiment, the system 500 can be provided and configured in a charger baby that can be charged and then provide power to another electronic device through the USB Type-A or Type-C ^TM port. In other embodiments, a system (e.g., system 500) may be configured with power switch control circuitry and may be provided in various other USB-enabled electronic or electromechanical devices.

It should be appreciated that a system implemented on or as an IC controller (e.g., system 500) may be provided in different applications that may differ in the type of power source used and the direction in which power is delivered. For example, in the case of a mobile power adapter, the power source is an AC wall outlet. Further, in the case of a PC power adapter, the power delivery flow is from the provider device to the consumer device, while in the case of a charger baby, the power delivery flow may be bi-directional, depending on whether the charger baby operates as a power provider (e.g., to power another device) or as a power consumer (e.g., to have itself charged). For these reasons, the various applications of the system 500 should be regarded as illustrative rather than limiting.

Fig. 6 is a flow chart of a method 600 of implementing a flyback converter with improved efficiency according to some embodiments. Method 600 may be performed by processing logic that comprises hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software, firmware, or a combination thereof. In some embodiments, the secondary side controller of the flyback converter performs the method 600 (e.g., the secondary side controller 126 in fig. 1, 2, and 4). For example, method 600 may be performed by firmware of the secondary side controller. In some embodiments, peripheral subsystem 510 in FIG. 5 performs method 600.

At operation 610, processing logic obtains a set of input parameters associated with a flyback converter. In some embodiments, the flyback converter is an ACF flyback converter. In some embodiments, obtaining the set of input parameters includes: a set of subsystem parameters is received from a subsystem. For example, the set of subsystem parameters may indicate power loss due to switching actions of the HS switch on the primary side of the flyback converter. In some embodiments, obtaining the set of input parameters includes: a set of system parameters from an initial configuration is received. In some embodiments, the set of system parameters includes a primary inductance relative to the flyback transformer, an equivalent capacitance relative to the primary drain node, and a turns ratio corresponding to the flyback transformer.

At operation 620, the processing logic determines a set of output parameters based on the set of input parameters. In some embodiments, the set of output parameters may include at least one of: the pulse width (T _{req_zvs}), the duration of the primary drain hold at 0V (T _{dur_zvs}), or the power gain (P _ACF).T_{dur_zvs} may be used to determine the dead time of the HS switch) for achieving ZVS. For example, a function based on equation (1) may be used to determine the pulse width. For example, the duration may be determined using a function based on equation (2).

At operation 630, the processing logic controls operation of the flyback converter based on the set of output parameters. In some embodiments, controlling operation of the flyback converter includes: the on-time of the HS switch is controlled based on T _{req_zvs}. In some embodiments, controlling operation of the flyback converter includes: the duration of the primary drain being held at 0V is controlled based on T _{dur_zvs}. In some embodiments, controlling operation of the flyback converter includes: determining whether the power loss due to the switching action of the HS switch exceeds the power gain, and switching the HS switch once in a plurality of cycles in response to determining that the power loss due to the switching action of the HS switch exceeds the power gain. Further details regarding operations 610-630 are described above with reference to fig. 1-5.

In the foregoing description, portions of the detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "receiving," "adjusting," or the like, refer to the action and processes of a computing system, or similar electronic device, that manipulates and transforms data represented as physical (electronic) quantities within the device/system's registers and memories into other data similarly represented as physical quantities within the memories or registers or other such information storage, transmission or display devices.

The word "example" or "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word "example" or "exemplary" is intended to specifically present concepts. As used herein, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". Unless specified otherwise, or clear from context, "X includes a or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; x comprises B; or X includes both a and B, then "X includes a or B" is satisfied under any of the foregoing examples. In addition, the articles "a" and "an" as used in this disclosure and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Furthermore, the use of the terms "an embodiment" or "one embodiment" throughout are not intended to denote the same embodiment, unless described as such.

The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., in order to provide a better understanding of the various embodiments of the techniques described herein with respect to flyback converters that support ACF functionality (e.g., for use in USB power delivery applications). It will be apparent, however, to one skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the techniques described herein. Accordingly, the specific details set forth in the following description are merely exemplary. The specific embodiments may vary from these exemplary details and still be understood to be within the spirit and scope of the present application.

Reference throughout this specification to "an embodiment," "one embodiment," "an example embodiment," "some embodiments," and "various embodiments" means that a particular feature, structure, step, operation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Furthermore, the appearances of the phrases "an embodiment," "one embodiment," "an example embodiment," "some embodiments," and "various embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment.

The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate descriptions according to exemplary embodiments. These embodiments (which may also be referred to herein as "examples") are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. Embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be appreciated that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable one skilled in the art to practice, make and/or use the subject matter.

The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., in order to provide a better understanding of several embodiments of the present disclosure. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. An apparatus, comprising:

An Active Clamp Flyback (ACF) flyback converter, the Active Clamp Flyback (ACF) flyback converter comprising:

A primary side including a High Side (HS) switch, a Low Side (LS) switch, and an ACF driver; and

A secondary side comprising a secondary side controller configured to at least:

Obtaining a set of input parameters including a set of subsystem parameters associated with the subsystem and a set of system parameters associated with the initial configuration;

determining a set of output parameters based on the set of input parameters; and

Controlling operation of the ACF flyback converter based on the set of output parameters.

2. The apparatus of claim 1, wherein:

the set of output parameters includes a pulse width for achieving Zero Voltage Switching (ZVS); and

To control the operation of the ACF flyback converter, the secondary side controller is configured to control an on-time of the HS switch based on the pulse width for achieving ZVS.

3. The apparatus of claim 2, wherein:

the set of system parameters includes a primary inductance relative to a flyback transformer, an equivalent capacitance relative to a primary drain node, and a turns ratio corresponding to the flyback transformer; and

The pulse width for achieving ZVS is determined based on the primary inductance, the equivalent capacitance, and the turns ratio.

4. The apparatus of claim 1, wherein the set of output parameters comprises a duration for which a primary drain remains at zero volts.

5. The apparatus of claim 4, wherein to control the operation of the ACF flyback converter, the secondary side controller is configured to control the duration that the primary drain remains at zero volts.

6. The apparatus of claim 4, wherein to control the operation of the ACF flyback converter, the secondary side controller is configured to determine a dead time of the HS switch based on the duration that the primary drain remains at zero volts.

7. The apparatus of claim 4, wherein:

The duration that the primary drain remains at zero volts is determined based on the primary inductance, the equivalent capacitance, and the turns ratio.

8. The apparatus of claim 1, wherein:

The set of subsystem parameters is indicative of power loss due to switching actions of the HS switch;

the set of output parameters includes a power gain; and

To control the operation of the ACF flyback converter, the secondary-side controller is configured to:

Determining whether the power loss due to the switching action of the HS switch exceeds the power gain; and

The HS switch is switched once in a plurality of cycles in response to determining that the power loss due to the switching action of the HS switch exceeds the power gain.

9. The apparatus of claim 8, wherein the power loss due to the switching action of the HS switch is determined based on a flyback transformer loss and an ACF flyback driver loss.

10. The apparatus of claim 1, wherein the apparatus comprises a universal serial bus power transfer (USB-PD) power adapter.

11. The apparatus of claim 1, further comprising a rectifier coupled to an Alternating Current (AC) source to generate a Direct Current (DC) output based on an AC input received from the AC source.

12. A method, comprising:

Obtaining, by a secondary side controller of a secondary side of an Active Clamp Flyback (ACF) flyback converter, a set of input parameters including a set of subsystem parameters associated with a subsystem of the flyback converter and a set of system parameters associated with an initial configuration of the flyback converter, wherein the ACF flyback converter further includes a primary side including a high-side (HS) switch and a low-side (LS) switch;

Determining, by the secondary side controller, a set of output parameters based on the set of input parameters; and

Controlling, by the secondary side controller, operation of the ACF flyback converter based on the set of output parameters.

13. The method according to claim 12, wherein:

Controlling the operation of the ACF flyback converter includes: the on-time of the HS switch is controlled based on the pulse width for achieving ZVS.

14. The method according to claim 13, wherein:

15. The method according to claim 12, wherein:

The set of output parameters includes a duration for which the primary drain remains at zero volts; and

Controlling the operation of the flyback converter includes at least one of: the duration of the primary drain remaining at zero volts is controlled or a dead time of the HS switch is determined based on the duration of the primary drain remaining at zero volts.

16. The method according to claim 15, wherein:

17. The method according to claim 12, wherein:

the set of output parameters includes a power gain; and

Controlling the operation of the ACF flyback converter includes:

18. The method of claim 17, wherein the power loss due to the switching action of the HS switch is determined based on a flyback transformer loss and an ACF flyback driver loss.

19. A power adapter, comprising:

A rectifier coupled to an Alternating Current (AC) source configured to generate a Direct Current (DC) output based on an AC input received from the AC source; and

A primary side including a High Side (HS) switch, a Low Side (LS) switch, and an ACF driver;

A secondary side comprising a secondary side controller configured to at least:

Controlling operation of the ACF flyback converter based on the set of output parameters; and

A flyback transformer and a signal transformer, both coupled to the primary side and the secondary side.

20. The power adapter of claim 19, wherein the power adapter is a universal serial bus power delivery (USB-PD) power adapter.