CN118509392A - Network-on-chip system based on self-adaptive routing - Google Patents
Network-on-chip system based on self-adaptive routing Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
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Abstract
The invention relates to the technical field of embedded processors, in particular to a network-on-chip system based on self-adaptive routing. The system is based on input buffering, decoding logic, input state machine, read enable logic, station disable logic, primary round robin arbitration, output state machine, data station and packet level round robin arbitration, etc. The invention provides a feasibility scheme of self-adaptive routing, data of the same source node cannot be transmitted at the same time between two destination nodes, and the bandwidth utilization rate is improved; the data round robin arbitration with the weight is designed, the blocking probability of data is reduced, and the data transmission efficiency is improved.
Description
Technical Field
The invention relates to the technical field of embedded processors, in particular to a network-on-chip system based on self-adaptive routing.
Background
With the development and popularization of Multi-Core and many-Core chips with large bandwidth, a design framework of a Multi-processor system (Multi-Core Systems) on chip becomes a development trend of a modern embedded system, and is also the most widely applied ultra-large scale integrated circuit design. As the most potential architecture of the next-generation on-Chip multiprocessor system, a Network-on-Chip (NoC) -based many-core system interconnection structure capable of providing ultra-powerful parallel processing capability, high-bandwidth on-Chip data transmission capability, efficient computing and communication resource utilization and good system scalability has been widely applied to high-performance embedded systems, so a Network-on-Chip system scheme for optimizing and solving data transmission between on-Chip core and non-core hardware units is needed.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a network-on-chip system based on self-adaptive routing, solves the problem of data transmission between an on-chip core and a non-core hardware unit, and provides a feasibility scheme of the self-adaptive routing; the data round robin arbitration with the weight is designed, the blocking probability of data is reduced, and the bandwidth utilization rate is improved.
The invention is realized by the following technical scheme:
an on-chip network system based on self-adaptive routing comprises an input buffer, a decoding logic, an input state machine, a read enabling logic, a station invalidation logic, a first-level round robin arbitration, an output state machine, a data station and a packet-level round robin arbitration;
The input buffer is used for buffering data from a source node in the form of an asynchronous FIFO; the data channels between the network on chip and each node have only one physical channel, but are divided into a plurality of virtual channels, each virtual channel represents one type of data packet, the control architecture has three data packet formats, and each virtual channel is provided with a group of write enabling signals and read enabling signals;
The decoding logic decodes the data in the buffer, can know the destination node of the data according to the decoding result, and initiates a Req request to the destination node;
the input state machine controls the request transmission of the decoding logic;
the read enabling logic is used for controlling when the input port sends a read enabling signal to the source node, and the source node counts pulse signals to know the available depth value of the asynchronous FIFO of the input port;
the station invalidation logic selects one of the two destination nodes to transmit when the control data is transmitted by the two destination nodes, and the other destination node needs to be invalidated;
the first-level round-robin arbitration arbitrates requests initiated by different source nodes, and as long as the asynchronous FIFO is not empty, each beat has requests to participate in arbitration and generates an arbitration result when the beat;
The output state machine is used for controlling the priority of the round robin arbiter according to the state of the state machine after the transmission of the data packet of one source node is completed, and transmitting the data packet of the next source node;
the data station ensures that data transmission is in a pipeline design;
The packet-level round robin arbiter arbitrates data requests for different virtual channels, and the packet-level round robin arbiter has weights and arbitration enables. The weight is set according to the number of the packets, the priority is switched after 5 packets of Data are required to be transmitted for Data0, and each packet of Data1 is switched; arbitration enables are defined as writable lower level stations.
Preferably, the asynchronous FIFO has a depth of 8 and a width of 322 bits. Wherein the low 288 bits are data bits, containing 256 bits of data and 32 bits of ECC check; the upper 34 bits are sideband information, and include information such as SrcID (source node), dstID (destination node), data TYPE TYPE (data virtual channel TYPE), MAF number, even check of sideband information, and the like. The first of 2 packet formats contains 4 flits, each containing sideband information and data. The second type of packet includes 5 flits, specifically 1 packet header and 4 data, wherein the packet header only includes sideband information without data, and the data bit is all 0; the data contains no sideband information and only data, the sideband information bit is all 0.
Preferably, the decoding module is configured to know the destination node of the buffered data according to DstID and TYPE fields of the sideband information of the data.
Preferably, the input state machine controls the sending of the virtual channel data request of the source node, and includes three states of ARB, TRANS1 and TRANS 2. Decoding the Req request in the ARB state; in the TRANS1 state, when the asynchronous FIFO is not empty, the whole packet data decoded in the ARB state is to be transmitted; FIFO space time, no data transmission; at most one flit is transmitted in this state; in the TRANS2 state, the remaining data is transmitted.
Preferably, the read enable logic initiates a read enable pulse to the source node when the round robin arbiter of the output port outputs arbitration grant to the input port, and the source node adds 1 to the credit value every time the source node receives a pulse signal, and the source node initial credit value is the depth of the input port asynchronous FIFO, and simultaneously generates the read enable signal 1, which indicates that the read enable signal is valid and the read pointer of the FIFO adds 1.
Preferably, the first-level round-robin arbitration arbitrates the requests of the same virtual channel from different source nodes, and only if the data of the last source node is arbitrated, the priority is switched if the whole packet data of the source node is transmitted completely; in addition, the round robin arbiter has an arbitration enable defined as writable to the lower level stations.
Preferably, the output state machine indicates states of data transmission of virtual channels of two destination nodes, including three states of ARB, TRANS1 and TRANS 2. In the ARB state, arbitrating the packet header; in the TRANS1 state, for the invalid destination node, the current data in the state is not actually transmitted to the destination node; for the non-invalid destination node, the rest data of the data packet is always transmitted in the state; in the TRANS2 state, the destination node which is set to be invalid in the TRANS1 state transmits the whole packet data of the next source node.
Preferably, the data station ensures that the data transmission is designed in a pipeline manner, the data packet from one source node needs to be continuously transmitted before the data packet of the next source node is transmitted, and each virtual channel of each node output port is provided with a station.
Preferably, the packet level round robin arbitration arbitrates data packets of 2 different virtual channels, and requests output arbitration results when they are in a beat. With the arbiter enabled, each beat will participate in the arbitration. When no bubble is transmitted, requesting to output an arbitration grant signal when the request is received; when there is a bubble, no arbitration grant is generated. When arbitrating the data of the last virtual channel, a counter is needed to count the number of the data packet transmissions of the virtual channel, and only if the counter reaches the weight of the data packet of the virtual channel, the data of the next virtual channel can be switched. In addition, the round robin arbiter has an arbitration enable defined as writable to the lower level stations.
The beneficial effects of the invention are as follows:
1) And the self-adaptive routing mechanism can not transmit data of the same source node at the same time between two destination nodes, and the invalid port can transmit data of other source nodes, so that the bandwidth utilization rate is improved.
2) And the data with weight is subjected to round robin arbitration, so that the blocking probability of the data is reduced, and the efficiency of data transmission is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is an overall schematic diagram of a data adaptive routing according to the present invention;
FIG. 2 is a state diagram of an input state machine according to the present invention;
FIG. 3 is a schematic diagram of station disabling logic according to the present invention;
FIG. 4 is a state diagram of an output state machine according to the present invention;
FIG. 5 is a schematic diagram of a one-stage round-robin arbiter according to the present invention;
fig. 6 is a schematic diagram of a station according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the present invention provides a network-on-chip system based on adaptive routing, which is characterized by input buffering, decoding logic, input state machine, read enable logic, station disable logic, primary round robin arbitration, output state machine, data station and packet level round robin arbitration.
An input buffer for buffering data from the source node in the form of an asynchronous FIFO; the data channel between the network on chip and each node has only one physical channel, but is divided into a plurality of virtual channels, each virtual channel represents one type of data packet, the control architecture has three data packet formats, and each virtual channel is provided with a group of write enable signals and read enable signals. When the source node writes a data to the asynchronous FIFO, the write enable is valid and the asynchronous FIFO write pointer is incremented by 1; when arbitration grant output by the round robin arbiter of the virtual channel of the output port is valid, the read enable of the asynchronous FIFO is valid and the read pointer of the asynchronous FIFO is incremented by 1.
Decoding logic, which is used for knowing the destination node of the data according to DstID and TYPE domains of the sideband information of the asynchronous FIFO data; and the decoding is effective, and a Req request of a corresponding type can be initiated to the destination node. For the second data packet, the packet head only contains sideband information without data, and the data bit is all 0; the data contains no sideband information and only data, the sideband information bit is all 0. So when the header decoding is valid, the Req request is latched by a register under the control of the state machine, and is valid at all times in both TRANS1 and TRANS2 states.
As shown in fig. 2, the input state machine controls the transmission of the source node virtual channel data request, including the three states ARB, TRANS1 and TRANS 2. In the ARB state, decoding is carried out according to the side information; in the TRANS1 and TRANS2 states, the request is latched. In the TRANS1 state, the first data except the header is to be transmitted; in the TRANS2 state, the remaining data is transferred, and the state is switched to the ARB state until the counter expires, otherwise the state is maintained. The actual requests issued by the input ports are the hold signal and asynchronous FIFO non-empty signal phases.
The round-robin arbiter of each virtual channel of the output port outputs an arbitration result to the input port, and signals generated after all arbitration grant signals pass through one OR gate are the initiation of a read enable pulse to a source node, and the credit value is increased by 1 when the source node receives one pulse signal; meanwhile, when the generated signal is 1, the read pointer of the asynchronous FIFO is increased by 1.
As shown in fig. 3, station invalid logic control data is selected for transmission when both destination nodes can transmit. When the primary round-robin arbiter of the Data0 virtual channel of both Dst0 and Dst1 output ports arbitrates the Data0 request initiated on Src0, the Dst0 and Dst1 output ports return respective c_dst2Srci _data_grant signals to the Src0 input port. Considering the timing tension, two cjdst Srci _data_grant are beaten at the Src0 input port, then one Dst is selected for transmission according to src0_dst_ptr (when the pointer is used for both dsts, 0 means Dst0 is selected, 1 means Dst1 is selected, and the initial value is 0) Dst0 is selected for Data transmission, and c_sr02 dst1_data_grant_grant is set to 1 and output to Dst1.
As shown in fig. 4 and 5, the primary round-robin arbiter arbitrates requests from the same virtual channel from different source nodes. Assuming that the requests input by the output ports of the Dst0 and the Dst1 are 3'b101, and in the ARB state of the output state machine, the arbitration grant signals output by the primary round-robin arbiters of the Dst0 and the Dst1 when the beats are 3' b001; in the TRANS1 state, the Data in the asynchronous FIFO will be written to the stations of Dst0 and Dst1 at the same time, but at this time c_src02dst1_data_grant_invalid is set to 1, the signal is inverted and the station Valid signal phase is 0 after that, so the Data will not be written to Dst1; meanwhile, the Dst1 port arbitrates the header of the next source node and jumps to the TRANS2 state. For Dst0, data except the packet header is continuously transmitted, the transmission is skipped to an ARB state, and the state is maintained when the transmission is not completed; in the TRANS2 state, the Dst1 port transmits data of the next source node, and the data is skipped to the ARB state after transmission, and is kept in the ARB state after transmission.
As shown in fig. 6, the data stations ensure that the data transmission is pipelined. Stage_wr_en is Valid to indicate that data can be written to the station, and the station Valid bit stage_valid is 1. When stage_valid is 0, no request is indicated to participate in arbitration. When stage_wr_en and stage_rd_en are 1 at the same time, data is streamed.
Packet-level round robin arbitration arbitrates data from different virtual channel stations at the output port. The packet-level round robin arbiter has an arbitration enable defined to be writable to the lower level stations and a weight set according to the Data virtual channel type, e.g. Data0 set to 5 and Data1 set to 1. When no bubble is transmitting Data, for Data0, a beat SendSucc signal is generated for each complete Data packet transmitted, and the counter counts the signal, and only when the set weight value is reached, the round robin priority is switched to transmit Data of another virtual channel. For Data1, the round robin priority is switched every time a complete packet is transmitted. When there is bubble transmission, the round-robin priority is switched normally. The arbitration grant signal output by the packet-level round robin arbiter is used as a write enable signal of the corresponding data virtual channel to be transmitted to the next stage along with the data of the corresponding virtual channel.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The utility model provides a network system on chip based on self-adaptation route, the network system on chip have the data round robin arbitration of weight, reduced the jam probability of data, its characterized in that: the method comprises the steps of input buffering, decoding logic, an input state machine, reading enabling logic, station invalidation logic, primary round robin arbitration, output state machine, data station and packet level round robin arbitration;
The input buffer is used for buffering data from a source node in the form of an asynchronous FIFO; the data channels between the network on chip and each node have only one physical channel, but are divided into a plurality of virtual channels, each virtual channel represents one type of data packet, the control architecture has three data packet formats, and each virtual channel is provided with a group of write enabling signals and read enabling signals; the first packet format has only 1 flow control unit, and contains sideband information and data; the second data packet format comprises 5 flow control units, specifically 1 packet header and 4 data, wherein the packet header only comprises sideband information without data, and the data bit is all 0; the data does not contain sideband information and only contains data, and the sideband information bit is all 0; the third packet format comprises 4 flow control units, each of which contains sideband information and data;
The decoding logic is used for decoding the data in the asynchronous FIFO, acquiring a destination node of the data according to a decoding result, and initiating a Req request to the destination node;
the input state machine controls the request transmission of the decoding logic;
the read enabling logic is used for controlling when the input port sends a read enabling signal to the source node, and the source node counts pulse signals to know the available depth value of the asynchronous FIFO of the input port;
The station invalidation logic selects one of the two destination nodes to transmit when the control data is transmitted by the two destination nodes, and the other destination node needs to be invalidated;
the first-level round-robin arbitration arbitrates requests initiated by different source nodes, and as long as the asynchronous FIFO is not empty, each beat has requests to participate in arbitration and generates an arbitration result when the beat;
The output state machine is used for controlling the priority of the round robin arbiter according to the state of the state machine after the transmission of the data packet of one source node is completed, and transmitting the data packet of the next source node;
the data station ensures that data transmission is in a pipeline design;
The packet-level round robin arbitration arbitrates data requests of different virtual channels, and the packet-level round robin arbiter has weights and arbitration enabling; the weight is set according to the number of the packets, the priority is switched after Data0 is divided into 5 packets of Data to be transmitted, and each packet of Data1 is switched; arbitration enables are defined as writable lower level stations.
2. An adaptive routing based network on chip system according to claim 1, wherein said asynchronous FIFO has a depth of 8 and a width of 322 bits; wherein the low 288 bits are data bits, containing 256 bits of data and 32 bits of ECC check; the upper 34 bits are sideband information, including even check of SrcID, dstID, data TYPE TYPE, MAF number and sideband information; 2 packet formats are provided, the first of which contains 4 flits, each flit containing sideband information and data; the second type of packet includes 5 flits, specifically 1 packet header and 4 data, wherein the packet header only includes sideband information without data, and the data bit is all 0; the data contains no sideband information and only data, the sideband information bit is all 0.
3. An adaptive routing based network on chip system as recited in claim 1, wherein said decode logic is configured to learn the destination node of the asynchronous FIFO data based on DstID and TYPE fields of the sideband information of the data; and the decoding is effective, so that a Req request can be initiated to the destination node.
4. The network-on-chip system based on adaptive routing of claim 1, wherein the input state machine controls transmission of source node virtual channel data requests, comprising three states, ARB, TRANS1 and TRANS 2; decoding the Req request in the ARB state; in the TRANS1 state, when the asynchronous FIFO is not empty, the whole packet data decoded in the ARB state is to be transmitted; FIFO space time, no data transmission; at most one flit is transmitted in this state; in the TRANS2 state, the remaining data is transmitted.
5. The adaptive routing based network on chip system of claim 1, wherein the read enable logic initiates a read enable pulse to a source node when the round robin arbiter of an output port outputs an arbitration grant signal to the input port, the credit value being incremented by 1 for each pulse signal received by the source node; the source node initial credit value is the depth of the FIFO in the input port, and when the generated signal is 1 valid, the read pointer of the FIFO is increased by 1.
6. The adaptive routing-based network-on-chip system of claim 1, wherein the station invalidation logic is configured to invalidate one of the arbitration grant signals returned from the output ports of the two destination nodes after the two destination nodes have beaten the arbitration grant signal when both destination nodes transmit data from the same source node, and wherein the entire packet is transmitted only on the destination node for which the arbitration grant is valid.
7. The adaptive routing-based network-on-chip system of claim 1, wherein the first-level round-robin arbitration arbitrates requests from the same virtual channel of different source nodes, and only if the data of a previous source node is arbitrated, priority is switched if the whole packet of data of the source node is completely transmitted; in addition, the round robin arbiter has an arbitration enable defined as writable to the lower level stations.
8. The adaptive routing-based network-on-chip system of claim 1, wherein the output state machine indicates states of virtual channel transmission data of two destination nodes, including three states of ARB, TRANS1 and TRANS 2; in the ARB state, arbitrating the packet header; in the TRANS1 state, for the invalid destination node, the current data in the state is not actually transmitted to the destination node; for the non-invalid destination node, the rest data of the data packet is always transmitted in the state; in the TRANS2 state, the destination node which is set to be invalid in the TRANS1 state transmits the whole packet data of the next source node.
9. An adaptive routing based network on chip system according to claim 1, wherein the stations ensure that data transmission is pipelined, data packets from one source node need to be continuously transmitted before the next source node is transmitted, and one station is provided for each virtual channel of each node output port.
10. The network-on-chip system based on adaptive routing of claim 1, wherein the packet-level round robin arbiter arbitrates data packets of 2 different virtual channels, requests to output arbitration results when the requests are in a beat; under the condition that the arbiter is enabled, each beat participates in arbitration; when no bubble is transmitted, requesting to output an arbitration grant signal when the request is received; when bubbles exist, no arbitration grant is generated; when arbitrating the data of a last virtual channel, a counter is needed to count the number of the data packet transmissions of the virtual channel, and only if the counter reaches the weight of the data packet of the virtual channel, the data of the next virtual channel can be switched; in addition, the round robin arbiter has an arbitration enable defined as writable to the lower level stations.
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