CN118509392A - Network-on-chip system based on self-adaptive routing - Google Patents

Abstract

The present invention relates to the field of embedded processor technology, and in particular to an on-chip network system based on adaptive routing. The system is based on input buffer, decoding logic, input state machine, read enable logic, station invalid logic, first-level round-robin arbitration, output state machine, data station and packet-level round-robin arbitration logic. The present invention provides a feasible solution for adaptive routing, in which data of the same source node will not be transmitted at two destination nodes at the same time, thereby improving bandwidth utilization; a data round-robin arbitration with weights is designed, which reduces the probability of data congestion and improves data transmission efficiency.

Description

A Network-on-Chip System Based on Adaptive Routing

Technical Field

The present invention relates to the technical field of embedded processors, and in particular to an on-chip network system based on adaptive routing.

Background Art

With the development and popularization of high-bandwidth multi-core and many-core chips, the design framework of multi-core systems on a chip has become the development trend of modern embedded systems and the most widely used VLSI design. As the most promising next-generation multi-processor system on a chip architecture, the many-core system interconnection structure based on the network-on-chip (NoC) can provide super-powerful parallel processing capabilities, high-bandwidth on-chip data transmission capabilities, efficient computing and communication resource utilization, and good system scalability. It has been widely used in high-performance embedded systems, so there is an urgent need for an on-chip network system solution that optimizes the data transmission between the core and non-core hardware units on a chip.

Summary of the invention

In view of the shortcomings of the prior art, the present invention provides an on-chip network system based on adaptive routing, which solves the problem of data transmission between core and non-core hardware units on a chip and provides a feasible solution for adaptive routing; a data round-robin arbitration with weights is designed to reduce the probability of data congestion and improve bandwidth utilization.

The present invention is achieved through the following technical solutions:

An on-chip network system based on adaptive routing includes an input buffer, a decoding logic, an input state machine, a read enable logic, a station invalidation logic, a first-level round-robin arbitration, an output state machine, a data station, and a packet-level round-robin arbitration;

The input buffer caches data from the source node in the form of an asynchronous FIFO; the data channel between the on-chip network and each node has only one physical channel, but is divided into multiple virtual channels, each virtual channel represents a type of data packet, the control architecture has a total of three data packet formats, and each virtual channel is set with a set of write enable and read enable signals;

The decoding logic decodes the data in the buffer, and the destination node of the data can be known according to the decoding result, and a Req request is initiated to the destination node;

The input state machine controls the request sending of the decoding logic;

The read enable logic controls when the input port sends a read enable signal to the source node. The source node counts the pulse signal to know the available depth value of the asynchronous FIFO of the input port;

The station invalidation logic controls the data to be transmitted to two destination nodes, and selects one of them for transmission, and the other destination node needs to be invalidated;

The first-level round-robin arbitration arbitrates requests initiated by different source nodes. As long as the asynchronous FIFO is not empty, there are requests participating in the arbitration in each beat and the arbitration result is generated in the beat;

The output state machine controls the priority of the round-robin arbiter to transmit the data packet of the next source node after the data packet transmission of a source node is completed according to the state of the state machine;

The data station ensures that data transmission is a pipeline design;

The packet-level round-robin arbitration arbitrates data requests of different virtual channels, and the packet-level round-robin arbiter has weights and arbitration enable. The weight is set according to the number of packets, for example, Data0 needs to switch priority after transmitting 5 packets of data, and Data1 switches priority for each packet; the arbitration enable is defined as being writable to the lower-level station.

Preferably, the asynchronous FIFO has a depth of 8 and a width of 322 bits. The lower 288 bits are data bits, including 256 bits of data and 32 bits of ECC check; the upper 34 bits are sideband information, including SrcID (source node), DstID (destination node), data type TYPE (data virtual channel type), MAF number, and even check of sideband information. This article contains 2 data packet formats. The first contains 4 flits, and each flit contains sideband information and data. The second contains 5 flits, specifically 1 header and 4 data, where the header only contains sideband information but not data, and the data bits are all 0; the data does not contain sideband information but only data, and the sideband information bits are all 0.

Preferably, the decoding module can know the destination node of the data according to the DstID and TYPE fields of the buffered data sideband information.

Preferably, the input state machine controls the sending of the source node virtual channel data request, including three states: ARB, TRANS1 and TRANS2. In the ARB state, the Req request is decoded; in the TRANS1 state, when the asynchronous FIFO is not empty, the whole packet of data decoded in the ARB state is to be transmitted; when the FIFO is empty, no data is transmitted; in this state, at most one flit is transmitted; in the TRANS2 state, the remaining data is transmitted.

Preferably, the read enable logic initiates a read enable pulse to the source node when the round-robin arbitrator of the output port outputs an arbitration authorization to the input port. The credit value of the source node increases by 1 each time the source node receives a pulse signal. The initial credit value of the source node is the depth of the asynchronous FIFO of the input port. When the read enable signal generated at the same time is 1, it indicates that the read enable signal is valid, and the read pointer of the FIFO increases by 1.

Preferably, the first-level round-robin arbitration arbitrates requests for the same virtual channel from different source nodes. As long as the data of the previous source node is arbitrated, the priority will be switched only when the entire packet of data of the source node is transmitted; in addition, the round-robin arbitrator has an arbitration enable, and the arbitration enable is defined as being writable to the lower-level station.

Preferably, the output state machine indicates the state of data transmission of the virtual channels of the two destination nodes, including three states: ARB, TRANS1 and TRANS2. In the ARB state, the arbitration packet header; in the TRANS1 state, for the invalidated destination node, the current data will not actually be transmitted to the destination node in this state; for the non-invalidated destination node, the remaining data of the data packet will be transmitted in this state; in the TRANS2 state, the invalidated destination node in the TRANS1 state transmits the entire packet data of the next source node.

Preferably, the data station ensures that data transmission is a pipeline design, and the data packets from one source node need to be transmitted continuously before the data packets of the next source node are transmitted, and a station is set for each virtual channel of each node output port.

Preferably, the packet-level round-robin arbitration arbitrates data packets of two different virtual channels, and the arbitration result is output when the request is made. When the arbitrator is enabled, each beat will participate in the arbitration. When there is no bubble transmission, the arbitration authorization signal is output when the request is made; when there is a bubble, no arbitration authorization is generated. When arbitrating the data of a virtual channel, a counter is required to count the number of data packets transmitted on the virtual channel. Only when the counter reaches the weight of the data packet of the virtual channel will the data of the next virtual channel be switched. In addition, the round-robin arbitrator has arbitration enable, and the arbitration enable is defined as being writable to the lower-level station.

The beneficial effects of the present invention are:

1) Adaptive routing mechanism: data from the same source node will not be transmitted to two destination nodes at the same time. Invalidating ports can transmit data from other source nodes, thus improving bandwidth utilization.

2) Weighted data round-robin arbitration reduces the probability of data congestion and improves the efficiency of data transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is an overall schematic diagram of data adaptive routing according to the present invention;

FIG2 is a schematic diagram of the state of the input state machine according to the present invention;

FIG3 is a schematic diagram of the station invalid logic of the present invention;

FIG4 is a state diagram of an output state machine according to the present invention;

FIG5 is a schematic diagram of a primary round-robin arbiter according to the present invention;

FIG. 6 is a schematic diagram of a station according to the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

As shown in FIG1 , the present invention provides a network-on-chip system based on adaptive routing, characterized by being based on input buffer, decoding logic, input state machine, read enable logic, station invalidation logic, first-level round-robin arbitration, output state machine, data station and packet-level round-robin arbitration.

Input buffer, using asynchronous FIFO to cache data from source nodes; the data channel between the on-chip network and each node has only one physical channel, but is divided into multiple virtual channels, each virtual channel represents a type of data packet, the control architecture has three data packet formats, and each virtual channel is set with a set of write enable and read enable signals. When the source node writes a data to the asynchronous FIFO, the write enable is valid and the asynchronous FIFO write pointer is incremented by 1; when the arbitration authorization output by the round-robin arbiter of the output port virtual channel is valid, the read enable of the asynchronous FIFO is valid and the read pointer of the asynchronous FIFO is incremented by 1.

The decoding logic can know the destination node of the data according to the DstID and TYPE fields of the asynchronous FIFO data sideband information; if the decoding is valid, the corresponding type of Req request can be initiated to the destination node. For the second type of data packet, since the packet header only contains the sideband information but not the data, the data bits are all 0; the data does not contain the sideband information but only the data, and the sideband information bits are all 0. Therefore, when the packet header decoding is valid, the Req request needs to be latched through the register under the control of the state machine. In the TRANS1 and TRANS2 states, the Req request is always valid.

As shown in Figure 2, the input state machine controls the sending of the source node virtual channel data request, including three states: ARB, TRANS1 and TRANS2. In the ARB state, decoding is performed according to the sideband information; in the TRANS1 and TRANS2 states, the request is latched. In the TRANS1 state, the first data except the packet header is to be transmitted; in the TRANS2 state, the remaining data is transmitted until the counter is full before switching to the ARB state, otherwise it remains in this state. The request actually sent by the input port is the AND of the hold signal and the asynchronous FIFO non-empty signal.

Read enable logic, the round-robin arbiter of each virtual channel of the output port will output the arbitration result to the input port. The signal generated after all arbitration authorization signals pass through an OR gate is the read enable pulse initiated to the source node. The credit value increases by 1 for each pulse signal received by the source node; at the same time, when the generated signal is valid, the read pointer of the asynchronous FIFO increases by 1.

As shown in Figure 3, when the station invalid logic controls data to be transmitted at both destination nodes, one of them is selected for transmission. When the first-level round-robin arbitrators of the Data0 virtual channel of the Dst0 and Dst1 output ports both arbitrate the Data0 request initiated by Src0, the Dst0 and Dst1 output ports will return their respective c_Dst2Srci_Data_Grant signals to the Src0 input port. Considering the tight timing, the two c_Dst02Srci_Data_Grants will be tapped at the Src0 input port, and then Dst0 will be selected for data transmission according to Src0_Dst_Ptr (this pointer is used to select one of the Dsts for transmission when both Dsts are available, 0 means selecting Dst0, 1 means selecting Dst1, and the initial value is 0). At this time, c_Src02Dst1_Data_Grant_Invalid is set to 1 and output to Dst1.

As shown in Figures 4 and 5, the first-level round-robin arbiter arbitrates requests for the same virtual channel from different source nodes. Assuming that the requests input to the output ports of Dst0 and Dst1 are both 3'b101, in the ARB state of the output state machine, the arbitration grant signals output by the first-level round-robin arbiters of Dst0 and Dst1 are both 3'b001; In the TRANS1 state, the data in the asynchronous FIFO will be written to the platforms of Dst0 and Dst1 at the same time, but at this time c_Src02Dst1_Data_Grant_Invalid is set to 1, and the signal is negated and ANDed with the platform Valid signal to 0, so the data will not be written to Dst1; At the same time, the Dst1 port will arbitrate the packet header of the next source node and jump to the TRANS2 state. For Dst0, data other than the packet header will continue to be transmitted, and it will jump to the ARB state after the transmission is completed, and it will remain in this state if it is not transmitted; in the TRANS2 state, the Dst1 port transmits the data of the next source node, and it will jump to the ARB state after the transmission is completed, and it will remain in this state if it is not transmitted;

As shown in Figure 6, the data stage ensures that data transmission is pipelined. When Stage_Wr_En is valid, it means that data can be written to the stage. At this time, the stage valid bit Stage_Valid is 1. When Stage_Valid is 0, it indicates that there is no request to participate in arbitration. When Stage_Wr_En and Stage_Rd_En are 1 at the same time, data is pipelined.

Packet-level round-robin arbitration, arbitrating the data of different virtual channel stations on the output port. The packet-level round-robin arbiter has arbitration enable and weight. Arbitration enable is defined as the ability to write to the lower-level station. The weight value is set according to the data virtual channel type, for example, Data0 is set to 5 and Data1 is set to 1. When there is no bubble to transmit data, for Data0, a SendSucc signal will be generated for each complete data packet transmitted. The counter counts the signal, and only when the set weight value is reached will the round-robin priority be switched to transmit the data of another virtual channel. For Data1, the round-robin priority will be switched for each complete data packet transmitted. When there is bubble transmission, the round-robin priority is switched normally. The arbitration authorization signal output by the packet-level round-robin arbiter is used as the write enable signal of the corresponding data virtual channel and is transmitted to the next level along with the data of the corresponding virtual channel.

The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A network-on-chip system based on adaptive routing, wherein the network-on-chip system has a weighted data round-robin arbitration, which reduces the probability of data congestion, and is characterized by comprising an input buffer, a decoding logic, an input state machine, a read enable logic, a station invalidation logic, a first-level round-robin arbitration, an output state machine, a data station, and a packet-level round-robin arbitration; The input buffer caches data from the source node in the form of an asynchronous FIFO; the data channel between the on-chip network and each node has only one physical channel, but is divided into multiple virtual channels, each virtual channel represents a type of data packet, and the control architecture has three data packet formats, and each virtual channel is set with a set of write enable and read enable signals; the first data packet format has only one flow control unit, and the data packet format contains sideband information and data; the second data packet format contains five flow control units, specifically one packet header and four data, wherein the packet header only contains sideband information but no data, and the data bits are all 0; the data does not contain sideband information but only data, and the sideband information bits are all 0; the third data packet format contains four flow control units, each of which contains sideband information and data; The decoding logic decodes the data in the asynchronous FIFO, can know the destination node of the data according to the decoding result, and initiates a Req request to the destination node; The input state machine controls the request sending of the decoding logic; The read enable logic controls when the input port sends a read enable signal to the source node. The source node counts the pulse signal to know the available depth value of the asynchronous FIFO of the input port; The station invalidation logic controls the data to be transmitted to two destination nodes, and selects one of them for transmission, while the other destination node needs to be invalidated; The first-level round-robin arbitration arbitrates requests initiated by different source nodes. As long as the asynchronous FIFO is not empty, there are requests participating in the arbitration in each beat and the arbitration result is generated in the beat; The output state machine controls the priority of the round-robin arbiter to transmit the data packet of the next source node after the data packet transmission of a source node is completed according to the state of the state machine; The data station ensures that data transmission is a pipeline design; The packet-level round-robin arbitration arbitrates data requests of different virtual channels, and the packet-level round-robin arbiter has weights and arbitration enables; the weights are set according to the number of packets, and are divided into Data0, which needs to transmit 5 packets of data before switching priorities, and Data1 switches priorities for each packet; the arbitration enable is defined as being writable to the lower-level station. 2. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the asynchronous FIFO has a depth of 8 and a width of 322 bits; the lower 288 bits are data bits, including 256 bits of data and 32 bits of ECC check; the upper 34 bits are sideband information, including SrcID, DstID, data type TYPE, MAF number and even check of sideband information; there are 2 data packet formats in this article, the first one includes 4 flits, each flit includes sideband information and data; the second one includes 5 flits, specifically 1 header and 4 data, wherein the header only includes sideband information but not data, and the data bits are all 0; the data does not include sideband information but only data, and the sideband information bits are all 0. 3. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the decoding logic can know the destination node of the data based on the DstID and TYPE fields of the asynchronous FIFO data sideband information; and a Req request can be initiated to the destination node if the decoding is valid. 4. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the input state machine controls the sending of virtual channel data requests of the source node, and includes three states: ARB, TRANS1 and TRANS2; in the ARB state, the Req request is decoded; in the TRANS1 state, when the asynchronous FIFO is not empty, the whole packet data decoded in the ARB state is to be transmitted; when the FIFO is empty, no data is transmitted; in this state, at most one flit is transmitted; in the TRANS2 state, the remaining data is transmitted. 5. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that when the round-robin arbitrator of the output port outputs an arbitration authorization signal to the input port, the read enable logic initiates a read enable pulse to the source node, and the credit value increases by 1 each time the source node receives a pulse signal; the initial credit value of the source node is the depth of the FIFO in the input port, and when the generated signal is valid, the read pointer of the FIFO increases by 1. 6. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the station invalidation logic, when two destination nodes transmit data from the same source node, after the arbitration authorization signals returned by the output ports of the two destination nodes are matched, one of the arbitration authorization signals is set invalid, and the entire data packet can only be transmitted on the destination node with valid arbitration authorization. 7. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the first-level round-robin arbitration arbitrates requests for the same virtual channel from different source nodes, and only when the data of the previous source node is arbitrated, the priority will be switched only after the entire packet of data of the source node is transmitted; in addition, the round-robin arbitrator has an arbitration enable, and the arbitration enable is defined as being writable to the lower-level station. 8. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the output state machine indicates the state of data transmission of the virtual channels of two destination nodes, including three states: ARB, TRANS1 and TRANS2; in the ARB state, the arbitration packet header; in the TRANS1 state, for the invalidated destination node, the current data will not actually be transmitted to the destination node in this state; for the non-invalidated destination node, the remaining data of the data packet will be transmitted in this state; in the TRANS2 state, the invalidated destination node in the TRANS1 state transmits the entire packet data of the next source node. 9. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the station ensures that data transmission is a pipeline design, and the data packets from a source node need to be transmitted continuously before the data packets of the next source node are transmitted, and a station is set for each virtual channel of each node output port. 10. A network-on-chip system based on adaptive routing as described in claim 1, characterized in that the packet-level round-robin arbitrator arbitrates data packets of two different virtual channels, and outputs the arbitration result when requesting a beat; when the arbitrator is enabled, each beat will participate in the arbitration; when there is no bubble transmission, the arbitration authorization signal is output when requesting a beat; when there is a bubble, no arbitration authorization is generated; when arbitrating the data of a virtual channel, a counter is required to count the number of data packets transmitted in the virtual channel, and only when the counter reaches the weight of the data packet of the virtual channel will the data of the next virtual channel be switched; in addition, the round-robin arbitrator has arbitration enable, and the arbitration enable is defined as being writable to the lower-level platform.