CN118508933A

CN118508933A - Time sequence adjusting circuit, delay path determining method and terminal equipment

Info

Publication number: CN118508933A
Application number: CN202410587877.9A
Authority: CN
Inventors: 蒋伟华; 张欣; 简卫; 邹小龙; 芶春梅
Original assignee: Shenzhen Flying Fairy Intelligent Technology Co ltd
Current assignee: Shenzhen Flying Fairy Intelligent Technology Co ltd
Priority date: 2024-05-11
Filing date: 2024-05-11
Publication date: 2024-08-16

Abstract

The embodiment of the application is suitable for the technical field of integrated circuits, and provides a time sequence adjusting circuit, a delay path determining method and terminal equipment, wherein the time sequence adjusting circuit comprises: at least two levels of sequential elements; a clock selection module; a first delay selection module, configured to select a data delay path corresponding to a functional mode signal according to the functional mode signal, and connect the data delay path into a data path between the two levels of sequential elements; and/or a second delay selection module, which is connected to the clock input end of any time sequence element, and is used for selecting a clock delay path corresponding to the functional mode signal according to the functional mode signal and accessing the clock delay path to the clock input end of the time sequence element. The time sequence adjusting circuit provided by the embodiment can reduce the design difficulty of the circuit, thereby improving the research and development efficiency of the chip.

Description

Time sequence adjusting circuit, delay path determining method and terminal equipment

Technical Field

The embodiment of the application belongs to the technical field of integrated circuits, and particularly relates to a time sequence adjusting circuit, a delay path determining method and terminal equipment.

Background

With the rapid development of semiconductor technology, more and more functional modes and test modes can be realized on the same chip. When there are a plurality of different functional modes on one chip, since different circuit modules are required to perform different processing on data to realize the different functional modes, a plurality of different logic circuits can be connected between a source register and a destination register of the chip. When a user sends out a function switching instruction, the chip automatically selects a logic circuit corresponding to the function switching instruction to process data, and the generated data processing result is transmitted to a destination register through the same delay circuit. Because the data processing speed of each logic circuit is different, a developer needs to spend much extra effort to determine the total delay time length on the delay circuit, so that the delay effect of the delay circuit meets the timing convergence requirement of all circuit modules. When the chip scale is large and the logic circuits between the source register and the destination register are more, a developer often needs to spend a great deal of time to design a delay link, so that the research and development speed of the chip is reduced, and the research and development efficiency is low.

Disclosure of Invention

In view of the above, the embodiments of the present application provide a timing adjustment circuit, a method for determining a delay path, and a terminal device for improving the research and development efficiency of a chip.

A first aspect of an embodiment of the present application provides a timing adjustment circuit, including:

at least two levels of sequential elements;

The clock selection module is used for receiving a plurality of clock source signals and outputting clock signals corresponding to the functional mode signals to the time sequence element according to the functional mode signals.

The first delay selection module is connected between two levels of time sequence elements, and is used for selecting a data delay path corresponding to the functional mode signal according to the functional mode signal and connecting the data delay path into the data path between the two levels of time sequence elements; and/or

The second delay selection module is connected to the clock input end of any time sequence element and is used for selecting a clock delay path corresponding to the functional mode signal according to the functional mode signal and accessing the clock delay path to the clock input end of the time sequence element.

In a possible implementation manner of the first aspect, the method further includes:

The time sequence elements comprise N time sequence elements which are connected in series, wherein the first N-1 time sequence elements which are connected in series are respectively correspondingly connected with one first delay selection module and/or one second delay selection module; and N is a positive integer greater than or equal to 2. In a possible implementation manner of the first aspect, the timing element includes a first timing element and a second timing element, and a data output terminal of the first timing element is connected to a data input terminal of the second timing element;

The clock selection module comprises a first clock selector, wherein the clock output end of the first clock selector is connected with the clock input end of the first time sequence element and is used for outputting a first clock signal corresponding to the functional mode signal to the first time sequence element according to the functional mode signal;

Correspondingly, the second delay selection module is connected between the first clock selector and the first time sequence element, and is used for selecting a clock delay path corresponding to the functional mode signal according to the functional mode signal and connecting the clock delay path to the clock input end of the first time sequence element; and/or

The clock selection module comprises a second clock selector, wherein the clock output end of the second clock selector is connected with the clock input end of the second time sequence element and is used for outputting a second clock signal corresponding to the functional signal to the second time sequence element according to the functional signal;

Correspondingly, the second delay selection module is connected between the second clock selector and the second time sequence element, and is used for selecting a clock delay path corresponding to the functional mode signal according to the functional mode signal and accessing the clock delay path into a clock input end of the second time sequence element.

In a possible implementation manner of the first aspect, the first delay selection module includes a plurality of data delay paths and a first selector; the second delay selection module includes a plurality of clock delay paths and a second selector:

at least one delay unit is arranged on any data delay path;

The first selector is used for connecting the data delay path corresponding to the functional mode signal into a data path between the time sequence elements of the two levels;

at least one delay unit is arranged on any clock delay path;

the second selector is used for connecting the clock delay path corresponding to the functional mode signal into the clock path between the time sequence elements of the two levels.

A second aspect of an embodiment of the present application provides a method for determining a delay path, including:

determining a time sequence path according to a functional mode signal input by a user;

If the time sequence path has time sequence violation conditions, acquiring the path time difference of the time sequence path;

And determining a corresponding delay path of the time sequence path according to the path time difference and the unit delay time length.

In a possible implementation manner of the second aspect, the acquiring the path time difference of the timing path if the timing path has a timing violation includes:

Acquiring the data signal establishment time and the data signal holding time of each intermediate time sequence element in the time sequence path; the intermediate timing elements are the remaining timing elements in the timing path except for the first level timing element;

For any intermediate time sequence element, if the data signal establishing time and/or the data signal maintaining time meet the preset time sequence violation conditions, determining that the time sequence violation condition exists in any intermediate time sequence element;

The path time difference between any intermediate time sequence element and the time sequence element of the last level corresponding to any intermediate time sequence element is calculated.

In a possible implementation manner of the second aspect, the determining, according to the path time difference and the unit delay duration, a corresponding delay path of the timing path includes:

and determining a delay path between any intermediate time sequence element and a time sequence element of the last level corresponding to any intermediate time sequence element based on the path time difference and the unit delay time length.

In a possible implementation manner of the second aspect, the timing violation cases include a setup time violation case and a hold time violation case;

The acquiring the data signal setup time and the data signal hold time of each intermediate sequential element in the sequential path includes:

acquiring a first delay time required by a previous-level time sequence element corresponding to any intermediate time sequence element to receive a clock signal, an internal jump time of the previous-level time sequence element when processing a data signal, a data transmission time required by the data signal to be transmitted from the previous-level time sequence element to any intermediate time sequence element, a data signal establishment time after any intermediate time sequence element receives the data signal, a second delay time required by any intermediate time sequence element to receive the clock signal, a clock period corresponding to any intermediate time sequence element, and a data signal retention time after any intermediate time sequence element receives the clock signal;

for any intermediate timing element, if the data signal setup time and/or the data signal hold time meet a preset timing violation condition, determining that a timing violation condition exists in any intermediate timing element includes:

determining a first time length based on the first delay time, the internal transition time, the data transmission time, and the data signal setup time;

Determining a second duration based on the second delay time and the period duration;

If the first time length is longer than the second time length, determining that the setup time violation condition exists in any intermediate time sequence element;

determining a third duration based on the first delay time, the internal transition time, the data transmission time, and the data signal retention time;

and if the third duration is smaller than the second delay time, determining that the holding time violation condition exists in any intermediate time sequence element.

In a possible implementation manner of the second aspect, the determining, based on the path time difference and the unit delay duration, a delay path between the any intermediate timing element and a last level timing element corresponding to the any intermediate timing element includes:

For any intermediate time sequence element with the establishment time violation condition, determining a path time difference corresponding to the any intermediate time sequence element based on the data signal establishment time corresponding to the any intermediate time sequence element and a preset clock margin;

for any intermediate time sequence element with a holding time violation condition, determining a path time difference corresponding to the any intermediate time sequence element based on the data signal holding time corresponding to the any intermediate time sequence element and a preset clock margin;

And determining the target unit type and the number of delay units corresponding to the target unit type on the delay path based on the path time difference and the unit delay time length corresponding to each delay unit type.

A third aspect of an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the method for determining a delay path according to the second aspect.

A fourth aspect of the embodiments of the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements a method of determining a delay path as described in the second aspect above.

A fifth aspect of embodiments of the present application provides a computer program product, which when run on a computer causes the computer to perform the method of determining a delay path as described in the second aspect above.

Compared with the prior art, the embodiment of the application has the following advantages:

In the timing adjustment circuit of the embodiment of the application, the first delay selection module can connect the data delay path into the data path according to the received functional mode signal, and in addition, the second delay selection module can connect the clock delay path into the clock path according to the received functional mode signal. Therefore, when a circuit is designed, a researcher only needs to design a data delay path and/or a clock delay path corresponding to each functional mode signal respectively, and a delay circuit meeting the timing sequence convergence requirement of all the functional mode signals is not needed to be designed. Therefore, the timing adjustment circuit provided by the embodiment can reduce the design difficulty of the research personnel when designing the circuit, thereby improving the research and development speed and efficiency of the chip.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a timing closure diagram according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a timing violation provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a prior art timing repair provided by an embodiment of the present application;

fig. 4 is a schematic diagram of a timing adjustment circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 9 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

FIG. 12 is a schematic diagram of another timing adjustment circuit according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a delay selection module according to an embodiment of the present application;

fig. 14 is a schematic diagram of a method for determining a delay path according to an embodiment of the present application;

FIG. 15 is a schematic diagram of another method for determining a delay path according to an embodiment of the present application;

FIG. 16 is a timing path diagram according to an embodiment of the present application;

Fig. 17 is a schematic diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations. Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.

It should also be appreciated that references to "one embodiment" or "some embodiments" or the like described in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The sequential elements in the sequential circuit can receive the data signal and the clock signal and perform corresponding data processing operation on the data signal according to the received clock signal. In particular, the sequential elements generally perform corresponding data processing operations on the data signal when the rising edge of the clock signal arrives, and in order to ensure that the sequential elements can perform data processing on the data signal according to the clock signal, the data signal needs to arrive at the sequential elements before the rising edge signal.

Referring to fig. 1, a timing convergence diagram provided by an embodiment of the present application is shown. As shown in fig. 1, the period duration of the data signal transmission of the timing element is kept unchanged, wherein the period duration of the data signal transmission of the timing element is the period from the time when the timing element receives the data signal to the time when the timing element outputs the data signal. The time sequence element needs to keep the data signal stable after receiving the data signal and before the rising edge time of the clock signal arrives, and the time when the data signal is kept stable by the time sequence element can be expressed as the data signal establishment time. The timing element performs transmission processing on the data signal after the rising edge of the clock signal, and at this time, the timing element needs to keep the data signal stable and unchanged, and the time for keeping the data signal stable and unchanged by the timing element can be expressed as the data signal keeping time.

Further, in order to ensure that the data signal hold time and the data signal setup time meet the timing convergence requirement, a developer may add a clock margin during the period duration of the data signal when designing the timing circuit. The clock margin added before the data signal setup time may be the first time Zhong Yuliang, and the clock margin added after the data signal hold time may be the second clock margin. When the period duration of data signal transmission is exactly equal to the sum of the data signal holding time and the data signal establishing time, the situation of unstable data transmission still may occur, so by adding the first clock Zhong Yuliang and the second clock margin, the period duration can be ensured to be longer than the sum of the data signal holding time and the data signal establishing time, thereby further ensuring the transmission stability of the data signal.

Since a plurality of combinational logic circuits may exist on the data paths between the sequential elements of adjacent hierarchy levels in the sequential path, when a user switches the functional mode signal, the sequential elements may transmit the data signal through the combinational logic circuit corresponding to the functional mode signal to perform the data processing operation corresponding to the functional mode signal on the data signal. For example, when a certain functional mode signal is to perform logic function calculation on a data signal, the sequential elements may be connected through a plurality of decoders to form a combinational logic circuit capable of performing the logic function calculation operation to transmit the data signal. For another example, when a certain functional mode signal is a combination logic circuit which is required to determine whether two input data signals are equal and output a comparison result, the sequential element can be connected through a plurality of comparators to perform a data signal comparison operation to transmit the data signals. It can be seen that the transmission time of the data signal on the data path may be different in different functional modes. When a user switches the functional mode signal, a timing violation may occur between timing elements of adjacent levels due to a change in the transmission duration of the data signal on the data path.

Referring to fig. 2, a schematic diagram of a timing violation provided by an embodiment of the present application is shown. The timing violations in the timing path may include a hold time violation and a setup time violation, among others. When the time between the arrival of the data signal at the sequential element and the arrival of the rising edge of the clock signal is smaller than the necessary data signal setup time of the sequential element, a setup time violation occurs on the sequential element. When the time between the rising edge of the clock signal and the arrival of the new data signal after reaching the time sequence element is smaller than the data signal holding time necessary for the time sequence element, the holding time violation condition occurs on the time sequence element. As shown in fig. 2 (a), when the user switches the functional mode signal, the transmission time of the data signal on the data path may be prolonged, and since the period of the data signal is fixed after the data signal arrives at the timing element, the second clock margin may be prolonged when the data signal arrives at the timing element, that is, the time after the data signal holding time is prolonged, thereby resulting in insufficient setup time of the data signal and occurrence of a setup time violation. As shown in fig. 2 (b), when the user switches the functional mode signal, the transmission time of the data signal on the data path may be shortened, and since the time when the data signal arrives at the timing element may be advanced, and since the period time of the data signal is fixed, when the time when the data signal arrives at the timing element is advanced, the first time Zhong Yuliang is lengthened, that is, the time between the setup times of the data signal is lengthened, thereby resulting in insufficient retention time of the data signal, and a retention time violation condition occurs.

When a certain integrated circuit comprises a plurality of different functional modes, in order to make the timing paths in all the functional modes meet timing convergence, a developer needs to analyze the timing paths corresponding to the functional modes one by one to find out the timing paths with timing violations in the functional modes. Referring to fig. 3, a schematic diagram of a prior art timing repair is shown according to an embodiment of the present application. Referring to fig. 3, wherein D in fig. 3 may represent a data signal input of the sequential element; q may represent a data signal output of the sequential element; t may represent the clock input of the sequential element; CLK1 may represent a first clock source signal input port in the selector; CLKn may represent the nth clock source signal input port in the selector; the INPUT may represent a functional mode signal INPUT in the selector. After determining the timing path of the timing violation, the developer can make the timing path meet timing convergence by changing the delay unit number of the clock delay circuit or the delay unit number of the data delay circuit of the timing path.

Because the clock delay circuits or the data delay circuits of the time sequence elements of two adjacent layers are fixed, a researcher needs to traverse all the functional modes when designing the circuits, and determines the number of delay units of the clock delay paths or the number of delay units on the data delay paths corresponding to all the functional modes so that the designed clock delay circuits or data delay circuits meet the delay requirements of all the functional modes. When the delay value requirement of two or more modes in the integrated circuit on a delay circuit is large, a developer may not be able to directly make the timing path meet the timing convergence by changing the number of delay units, at this time, the developer needs to change the command netlist through engineering to logically adjust the circuit so that all the timing paths in the integrated circuit meet the timing convergence. Therefore, in the prior art, when the scale of the integrated circuit is larger and the functional modes that the integrated circuit can realize are more, the research personnel often need to spend a great deal of time to design the delay circuit, thereby reducing the research and development speed of the chip and leading to lower research and development efficiency.

Based on the above, the embodiment of the application provides a timing adjustment circuit. In the timing adjustment circuit provided in this embodiment, the first delay selection module may access a data delay path corresponding to the functional mode signal to the data path to adjust a transmission duration of the data signal. In addition, the second delay selection module may access a clock delay path corresponding to the functional mode signal into the clock path to adjust a transmission duration of the clock signal. When a developer designs a circuit, only a clock delay path and/or a data delay path meeting each functional mode signal need to be respectively designed. The research personnel does not need to design a delay path capable of meeting the delay requirements of all functional mode signals, so that the research personnel does not need to carry out repeated iterative adjustment on the time sequence path during design, the time cost of carrying out time sequence adjustment on the time sequence path is reduced, the efficiency of carrying out time sequence adjustment on the time sequence circuit is improved, and the research and development efficiency of the integrated circuit is further improved. In addition, in the time sequence adjusting circuit provided by the embodiment, since the first time delay selecting module and the second time delay selecting module can directly determine the data delay path and/or the clock delay path which need to be accessed into the time sequence path according to the functional mode signal, a user does not need to input an extra signal to control the first time delay selecting module and the second time delay selecting module, the control operation of the circuit is simplified, and the control efficiency is improved.

The following describes a timing adjustment circuit provided by an embodiment of the present application by means of a specific embodiment and with reference to the accompanying drawings:

Referring to fig. 4, a schematic diagram of a timing adjustment circuit according to an embodiment of the present application is shown. The timing adjustment circuit may include N different levels of timing elements connected in series and a first delay selection module 21. Where N may be a positive integer greater than or equal to 2 (the case where N is equal to 2 is shown as an example in fig. 4). The hierarchical structure between different sequential elements may refer to a hierarchical distribution between sequential elements, and the hierarchy between each sequential element may be dependent on the order in which the data signals are transferred. For example, the data signal is transferred to the first level timing element and then transferred from the first level timing element to the second level timing element, where the first level timing element is a previous level timing element of the second level timing element, and the second level timing element is a next level timing element of the first level timing element.

As shown in fig. 4, the timing adjustment circuit may include a level 1 timing element 111, a level 2 timing element 121, a first delay selection module 21, and a clock selection module 4. Wherein D in the sequential element may represent a data signal input on the sequential element; t in the sequential element may represent a clock input on the sequential element; q on the sequential element may represent the data signal output on the sequential element. The level 1 timing element 111 and the level 2 timing element 121 may be any of the existing electronic components that require the clock signal and the data signal to be applied simultaneously, such as a register, a memory, and the like.

There may be a plurality of different combinational logic circuits between the level 1 sequential element 111 and the level 2 sequential element 121, and at least one circuit device may be connected to any one combinational logic circuit. In particular, the circuit devices on the combinational logic circuit may include, but are not limited to, adders, half-adders, encoders, decoders, and the like. The level 1 timing element 111 may select a combinational logic circuit corresponding to the functional mode signal according to the functional mode signal input by the user, and access the combinational logic circuit corresponding to the functional mode signal into the data path, so as to process the data signal through the combinational logic circuit.

The clock selection module 4 may have a clock output terminal out_put1 connected to the clock input terminal T of the level 1 sequential element 111 and the clock input terminal T of the level 2 sequential element 121, respectively. The clock input of the clock selection module 4 may receive a plurality of clock source signals. Wherein CLK1 in fig. 4 may represent the clock input of the first clock source signal; CLKn in fig. 4 may represent the clock input of the nth clock source signal. The third signal input in_put3 of the clock selection module 4 may be used for receiving a functional mode signal entered by a user. The clock selection module 4 may select a clock signal corresponding to the functional mode signal according to the received functional mode signal, and output the clock signal corresponding to the functional mode signal to the 1 st layer timing element 111 and the 2 nd layer timing element 121 through the clock output terminal.

The first delay selection module 21 may be connected between the level 1 timing element 111 and the level 2 timing element 121. Specifically, the first delay selection module 21 may include a plurality of data delay paths therein. The first delay selection module 21 may receive a functional mode signal input by a user through the first signal input terminal in_put 1. The first delay selection module 21 may select a data delay path corresponding to the functional mode signal according to the functional mode signal after receiving the functional mode signal. The first delay selection module 21 may access a data delay path corresponding to the functional mode signal into a data path between the 1 st layer timing element 111 and the 2 nd layer timing element 121. After the first delay selection module 21 accesses the data delay path corresponding to the functional mode signal to the data path, the level 1 timing element 111 may transmit the data signal to the level 2 timing element 121 through the data delay path corresponding to the functional mode signal.

Referring to fig. 5, a schematic diagram of a timing adjustment circuit according to a second embodiment of the present application is shown. As shown in fig. 5, the timing adjustment circuit may include a level 1 timing element 111, a level 2 timing element 121, a first delay selection module 21, and a clock selection module 41.

Specifically, the first delay selection module 21 may be connected on a data path between the 1 st-level timing element 111 and the 2 nd-level timing element 121.

The clock selection module 41 may have a clock output terminal connected to the clock input terminal T of the 1 st stage timing element 111 to output a clock signal corresponding to the functional mode signal to the 1 st stage timing element 111 according to the functional mode signal. The first clock selection module 41 may include a clock selector 411 therein. The third signal input port in_put3 of the clock selector 411 may receive a functional mode signal input by a user and output a first clock signal corresponding to the functional mode signal to the 1 st-stage timing element 111 according to the received functional mode signal.

Referring to fig. 6, a schematic diagram of a timing adjustment circuit according to a third embodiment of the present application is shown. As shown in fig. 6, the timing adjustment circuit may include a level 1 timing element 111, a level 2 timing element 121, a first delay selection module 21, and a clock selection module 42.

The clock selection module 42 may have a clock output terminal connected to the clock input terminal T of the 2 nd stage timing element 121 to output a clock signal corresponding to the functional mode signal to the 2 nd stage timing element 121 according to the functional mode signal. The first clock selection module 42 may include a clock selector 421 therein. The third signal input port in_put3 of the clock selector 421 may receive the functional mode signal input by the user and output the first clock signal corresponding to the functional mode signal to the 2 nd stage timing element 121 according to the received functional mode signal.

When there are a plurality of different clock source signals in the 2 nd layer timing element 121, since delays before the respective clock source signals reach the clock selection module are inconsistent, timing violations may occur in the timing path when the clock source signals are switched along with the functional mode signal. Further, because the delays before the respective clock source signals reach the clock selection module are not uniform, the different clock source signals have different requirements on the length of the clock delay path to be inserted. The timing adjustment circuit provided in this embodiment can switch the clock delay path on the clock path through the functional mode signal, so that the timing path still satisfies timing convergence even after the clock source is switched. By the time sequence adjusting circuit provided by the embodiment, a researcher does not need to adjust the delay of different clock sources, so that the time cost for adjusting the clock sources is saved, the research and development time of the integrated circuit is reduced, and the research and development efficiency of the integrated circuit is improved.

Referring to fig. 7, a schematic diagram of a timing adjustment circuit according to a fourth embodiment of the present application is shown. As shown in fig. 7, the timing adjustment circuit may include a1 st timing element 111, a 2 nd hierarchy timing element 121, a first delay selection module 21, a clock selection module 41, and a clock selection module 42.

The first delay selection module 21 may be connected to a data path between the 1 st timing element 111 and the 2 nd layer timing element 121.

Referring to fig. 8, a schematic diagram of a timing adjustment circuit according to a fifth embodiment of the present application is shown. As shown in fig. 8, the timing adjustment circuit may include a1 st timing element 111, a 2 nd level timing element 121, a second delay selection module 31, a clock selection module 41, and a clock selection module 42.

The second delay selection module 31 may be connected to the clock input T of the level 1 timing element 111. Specifically, the second delay selection module 31 may include a plurality of clock delay paths therein. The second delay selection module 31 may receive the functional mode signal input by the user through the second signal input terminal in_put 2. The second delay selection module 31 may select a clock delay path corresponding to the functional mode signal according to the functional mode signal after receiving the functional mode signal, and access the clock delay path corresponding to the functional mode signal into the clock path of the 1 st-level timing element 111. After the second delay selection module 31 accesses the clock delay path corresponding to the functional mode signal to the clock path, the 1 st layer timing element 111 may receive the clock signal through the clock delay path corresponding to the functional mode signal.

The clock output terminal of the first clock selection module 41 may be connected to the clock input terminal T of the level 1 timing element 111. The first clock selection module 41 may include a clock selector 411 therein. The third signal input port in_put3 of the clock selector 411 may receive a functional mode signal input by a user and output a first clock signal corresponding to the functional mode signal to the 1 st-stage timing element 111 according to the received functional mode signal.

Accordingly, the second delay selection module 31 in the timing adjustment circuit may be connected to the clock path between the first clock selection module 41 and the 1 st stage timing element 111, for connecting the clock delay path corresponding to the functional mode signal to the clock path between the first clock selection module 41 and the 1 st stage timing element 111.

The clock output of the second clock selection module 42 may be connected to the clock input T of the level 2 sequential element 121. The second clock selection module 42 may include a clock selector 421 therein. The third signal input port in_put3 of the clock selector 421 may receive the functional mode signal input by the user and output the second clock signal corresponding to the functional mode signal to the 2 nd stage timing element 121 according to the received functional mode signal.

Referring to fig. 9, a schematic diagram of a timing adjustment circuit according to a sixth embodiment of the present application is shown. As shown in fig. 9, the timing adjustment circuit may include a1 st timing element 111, a 2 nd hierarchy timing element 121, a second delay selection module 32, a clock selection module 41, and a clock selection module 42.

The second delay selection module 32 may be connected to the clock input T of the level 2 sequential element 121. Specifically, the second delay selection module 32 may include a plurality of clock delay paths therein. The second delay selection module 32 may receive the functional mode signal input by the user through the second signal input terminal in_put 2. The second delay selection module 32 may select a clock delay path corresponding to the functional mode signal according to the functional mode signal after receiving the functional mode signal, and access the clock delay path corresponding to the functional mode signal into the clock path of the 2 nd layer sequential element 121. After the second delay selection module 32 accesses the clock delay path corresponding to the functional mode signal to the clock path, the 2 nd layer timing element 121 may receive the clock signal through the clock delay path corresponding to the functional mode signal.

The clock output terminal of the first clock selection module 41 may be connected to the clock input terminal T of the level 1 timing element 111.

The clock output of the second clock selection module 42 may be connected to the clock input T of the level 2 sequential element 121.

Referring to fig. 10, a schematic diagram of a timing adjustment circuit according to a seventh embodiment of the present application is shown. As shown in fig. 10, the timing adjustment circuit may include a level 1 timing element 111, a level 2 timing element 121, a first clock selection module 41, a second clock selection module 42, a first delay selection module 21, and a second delay selection module 31.

In the embodiment shown in fig. 10, a first delay selection module 21 may be connected to the data path between the 1 st timing element 111 and the 2 nd level timing element 121. In addition, the clock input terminal T of the 1 st timing element 111 may be further connected to the second delay selection module 31.

The clock input T of the level 1 timing element 111 may be connected to the clock output of the first clock selection module 41.

The clock input T of the level 2 sequential element 121 may be connected to the clock output of the second clock selection module 42.

Accordingly, the second delay selection module 31 may be connected to the clock path between the first clock selection module 41 and the 1 st stage timing element 111, for accessing the clock delay path corresponding to the functional mode signal to the clock path between the first clock selection module 41 and the 1 st stage timing element 111.

Referring to fig. 11, a schematic diagram of a timing adjustment circuit according to an eighth embodiment of the present application is shown. As shown in fig. 11, 2 levels of sequential elements may be present in the timing adjustment circuit. Wherein M sequential elements may be connected in parallel in level 1. Wherein M may be a positive integer greater than or equal to 2. (an example is shown in fig. 11 where M is equal to 3.)

Specifically, as shown in fig. 11, a first delay selection module 21 may be connected in the data path between the first 1 st-tier timing element 111 and the 2 nd-tier timing element 121. In addition, the clock input terminal T of the first 1 st-level timing element 111 may be connected to the first and second delay selection modules 31. The clock input T of the second 1 st tier timing element 112 may be connected to a second delay selection module 32. A second first delay selection module 22 may be connected in the data path between the third level 1 timing element 113 and the first level 2 timing element 121.

Referring to fig. 12, a schematic diagram of a timing adjustment circuit according to a ninth embodiment of the present application is shown. As shown in fig. 12, 2 levels of sequential elements may be present in the timing adjustment circuit. Wherein M sequential elements may be connected in parallel in level 1. Wherein M may be a positive integer greater than or equal to 2. (an example is shown in fig. 12 where M is equal to 3.)

Specifically, as shown in fig. 12, for a plurality of parallel 1 st-level sequential elements, a first delay selection module 21 may be connected in a data path between a first 1 st-level sequential element 111 and a2 nd-level sequential element 121. In addition, the clock input terminal T of the first 1 st-level timing element 111 may be connected to the first and second delay selection modules 31. The clock input T of the second 1 st tier timing element 112 may be connected to a second delay selection module 32. A second first delay selection module 22 may be connected in the data path between the third level 1 timing element 113 and the level 2 timing element 121.

For the level 2 sequential element 121, the clock input terminal T of the level 2 sequential element 121 may be connected to the third second delay selection module 33.

Referring to fig. 13, a schematic structural diagram of a delay selection module according to an embodiment of the present application is shown. The delay selection module may be a data delay selection module or a clock delay selection module. As shown in fig. 13 (a), when the delay selection module is connected to the data paths of the two different levels of sequential elements, the delay selection module may be a data delay selection module between the two different levels of sequential elements. The data delay selection module may include a plurality of data delay paths and a first selector. Each data delay path in the data delay selection module can comprise at least one delay unit. The first selector can select a data delay path corresponding to the functional mode signal according to the received functional mode signal to be connected to a data path between two time sequence elements of different levels so as to change the transmission time length of the data signal on the data path.

As shown in fig. 13 (b), when the delay selection module is connected to the clock input terminal T of a certain timing element, that is, the delay selection module is connected to the clock path of a certain timing element, the delay selection module may be the clock delay selection module of the timing element. The clock delay selection module may include a plurality of clock delay paths and a second selector. Wherein each clock delay path in the clock delay selection module may include at least one delay element. The second selector can select a clock delay path corresponding to the functional mode signal according to the received functional mode signal to be connected to the clock path of the time sequence element so as to change the transmission time length of the clock signal on the clock path.

Referring to fig. 14, a schematic diagram of a method for determining a delay path according to an embodiment of the present application is shown. The method can be applied to the terminal equipment provided with the chip design software or the chip design script. Specifically, the terminal device may be a large server, a computer, a smart phone, a tablet computer, and other devices. The method for determining the delay path specifically includes the following steps:

s1401, determining a timing path according to a function mode signal input by a user.

In this embodiment, when a developer needs to determine a delay path corresponding to each timing circuit in a certain functional mode, the developer may first input a functional mode signal corresponding to the functional mode in which the delay path needs to be determined to the terminal device. Because the combination logic circuits are different in the required use of each functional mode in the time sequence adjusting circuit, after the terminal equipment receives the functional mode signals input by the research personnel, the terminal equipment can determine the combination logic circuits which need to be connected among all time sequence elements according to the received functional mode signals, so that the time sequence path under the current functional mode is determined. Wherein at least two levels of sequential elements may be present in the sequential path.

S1402, if the time sequence path has time sequence violation, acquiring the path time difference of the time sequence path.

In this embodiment, after determining the timing path corresponding to a certain functional mode signal, the terminal device may input a clock signal to the clock input terminal of the timing element through the clock source signal, and input a data signal to the data signal input terminal of the first-level timing element in the clock path. Wherein the timing path may include at least two different levels of timing elements. In the embodiment of the present application, the description of the timing element is consistent with that of the timing adjustment circuit, please refer to the content of the timing adjustment circuit, and the description is omitted herein.

The terminal device may determine whether a timing violation exists on each timing path based on the transmission of the clock signal and the data signal in each timing element. If any time sequence path in the current functional mode has time sequence violation conditions, the terminal equipment can acquire the path time difference of the time sequence path with the time sequence violation conditions.

If no timing violation exists in all the timing paths in the current functional mode, the terminal device can automatically acquire the next functional mode signal and judge whether the timing violation exists in the timing paths of the next functional mode signal. Or the terminal device may generate the first prompt information and display the first prompt information through a preset display device. The first prompt information can be used for indicating that no time sequence violation exists in the current functional mode, so that a delay path is not required to be determined.

S1403, determining a delay path corresponding to the time sequence path according to the path time difference and the unit delay time length.

In this embodiment, after determining the path time difference corresponding to the timing path, the terminal device may determine the delay path corresponding to the timing path according to the path time difference corresponding to the timing path and the unit delay duration of the delay unit. Specifically, the terminal device may include a plurality of delay units of different delay unit types, where the delay units of different delay unit types have different unit delay durations. After determining the path time difference corresponding to the time sequence path, the terminal equipment firstly queries a delay unit type table according to the input current value corresponding to the current time sequence adjusting circuit and the load capacity of devices connected subsequently to the time sequence adjusting circuit so as to determine the candidate unit type corresponding to the current time sequence path from all delay unit types. Then, the terminal device can determine the target unit type corresponding to the current time sequence path and the number of delay units corresponding to each target unit type according to the path time difference corresponding to the current time sequence path and the unit delay time length of each candidate unit type. The terminal device may generate a delay path corresponding to the timing path in the current functional mode according to the target unit type and the number of delay units corresponding to each target unit type.

For example, the candidate unit types determined by the terminal device according to the input current value corresponding to the current timing adjustment circuit and the load capacity of the device connected to the subsequent timing adjustment circuit may include a first unit type, a second unit type and a third unit type. The unit delay time length corresponding to the first unit type may be 10 milliseconds, the unit delay time length corresponding to the second unit type may be 5 milliseconds, and the unit delay time length corresponding to the third unit type may be 2 milliseconds. When the path time difference corresponding to a certain timing path is 9 ms, the terminal device may determine that the second unit type and the third unit type are the target unit type corresponding to the timing path. The number of delay units corresponding to the second unit type may be 1, and the number of delay units of the third unit type may be 2.

In this embodiment, when a timing path with timing violations occurs in a certain functional mode, the terminal device may automatically generate a delay path corresponding to the timing path in the current functional mode according to a path time difference corresponding to the timing path. The delay selection module can automatically access the delay paths corresponding to the functional mode signals into the time sequence paths according to the input functional mode signals by accessing the delay paths corresponding to the time sequence paths under different functional modes into the delay selection module. The method provided by the embodiment not only can ensure that a research and development personnel does not need to design a delay path meeting the delay requirements of all functional modes when designing the chip, but also can automatically generate the delay path under each functional mode signal, so that the method provided by the embodiment can greatly reduce the research and development difficulty of the chip, thereby improving the research and development speed and the research and development efficiency of the chip.

Fig. 15 is a flowchart showing a specific implementation of another delay path determining method S1402 according to an embodiment of the present application. Referring to fig. 15, compared to the embodiment of fig. 14, in a method for determining a delay path provided in this embodiment, S1402 includes: s14021 to S14023 are specifically described below:

S14021, acquiring data signal establishment time and data signal retention time of each intermediate time sequence element in the time sequence path; the intermediate sequential elements are the rest of the sequential elements except the first-level sequential elements in the sequential path.

In this embodiment, after receiving the functional mode signal input by the user, the terminal device may determine, according to the functional mode signal, a combinational logic circuit to be connected between each sequential element, so as to determine a sequential path corresponding to the current functional mode signal. After determining the timing sequence path corresponding to the functional mode signal, the terminal device may input a data signal and a clock signal to the timing sequence path to obtain a data signal setup time and a data signal hold time of each intermediate timing sequence element in the timing sequence path under the current circuit structure. The intermediate sequential elements may be the rest of the sequential elements except the first-level sequential elements in the sequential path. Illustratively, when there are 3 levels of sequential elements in the sequential path, the intermediate sequential elements may be the second level sequential element and the third level sequential element.

For a certain intermediate sequential element, the corresponding data signal establishing time can be the time length of the interval between the data signal transmitted by the sequential element of the previous layer and the received clock valid signal, namely the total time length of the data signal which is kept stable before the clock valid signal arrives. For a certain intermediate sequential element, the corresponding data signal holding time may be the time interval between the reception of the clock valid signal and the output of the data signal to the sequential element of the next hierarchy, i.e. the total time interval for the intermediate sequential element to keep the data signal stable after the reception of the clock valid signal. In particular, the clock valid signal may be a rising edge signal of the clock or a falling edge signal of the clock.

In one possible implementation, in order to determine whether a timing violation occurs in the timing path, the terminal device may respectively obtain a data signal transmission condition and a clock signal transmission condition of each intermediate timing element on the timing path.

Fig. 16 is a schematic diagram of a timing path according to an embodiment of the present application. Referring to fig. 16, in the timing path, for any one intermediate timing element, the total time required for the data signal before reaching the intermediate timing element may include a first delay time required for the last-level timing element corresponding to the current intermediate timing element to receive the clock signal, an internal transition time of the last-level timing element corresponding to the current intermediate timing element when processing the data signal, and a data transfer time required for the data signal to be transferred from the last-level timing element corresponding to the current intermediate timing element; in the clock path, for any one of the intermediate timing elements, the total time period required for the clock signal before reaching that intermediate timing element may include the second delay time required for that intermediate timing element to receive the clock signal. The terminal device may determine whether the current intermediate timing element has a clock violation according to the acquired data signal setup time, the data signal hold time, the first delay time, the internal transition time, the data transmission time, the second delay time, and the clock period corresponding to the current intermediate timing element.

S14022, for any intermediate time sequence element, if the data signal setup time and/or the data signal hold time meet the preset time sequence violation conditions, determining that the time sequence violation condition exists in any intermediate time sequence element.

In this embodiment, for any intermediate timing element in the timing path, if the data signal setup time and/or the data signal hold time corresponding to the intermediate timing element meet the timing violation conditions preset by the developer, the terminal device may determine that the current intermediate timing element has a timing violation condition.

In one possible implementation, for the data signal, the total time required for transmitting to the intermediate timing element includes a first delay time required for the last level timing element corresponding to the current intermediate timing element to receive the clock signal, an internal transition time of the last level timing element corresponding to the current intermediate timing element when processing the data signal, and a data transmission time required for transmitting the data signal from the last level timing element corresponding to the current intermediate timing element, that is, the total time required for transmitting the data signal to the intermediate timing element is equal to a sum of the first delay time, the internal transition time, and the data transmission time. And the total time required for the clock signal to propagate to the intermediate timing element is equal to the sum of the clock period of the clock signal and the time required for the clock signal to propagate on the clock path, i.e. the sum of the clock period and the second delay time.

The timing violations may include, among other things, hold time violations and setup time violations. When the time between the arrival of the data signal at the sequential element and the arrival of the rising edge of the clock signal is smaller than the necessary data signal setup time of the sequential element, a setup time violation occurs on the sequential element. When the time between the rising edge of the clock signal and the arrival of the new data signal after reaching the time sequence element is smaller than the data signal holding time necessary for the time sequence element, the holding time violation condition occurs on the time sequence element. The current timing violation condition may include a first timing constraint formula and a second timing constraint formula. The first timing constraint formula may be used to determine whether a setup time violation condition occurs on the timing element. Specifically, when the setup time of the data signal corresponding to the timing element does not satisfy the first timing constraint formula, the terminal device may determine that a setup time violation condition occurs on the current timing element. When the retention time of the data signal corresponding to the time sequence element does not meet the second time sequence constraint formula, the terminal equipment can determine that the retention time violation condition occurs on the current time sequence element.

In one possible implementation, the first timing constraint formula may be as follows:

Tclk_{delay_FF1}+Tc_FF1+Tcomb_logic+Tsetup≤Tclk_FF2+Tperiod

wherein Tclk _{delay_FF1} may represent a first delay time required for the last level sequential element corresponding to the current intermediate sequential element to receive the clock signal. Tc _FF1 may represent the internal transition time of the last level sequential element corresponding to the current intermediate sequential element when processing the data signal. Tcomb _logic may represent the data transfer time required for a data signal to be transferred from the last-level sequential element corresponding to the current intermediate sequential element. Tsetup may represent a data signal setup time after the current sequential element receives the data signal. Tclk _FF2 may represent a second delay time required for the current intermediate sequential element to receive the clock signal. Tperiod may represent the clock period corresponding to the current intermediate sequential element.

In one possible implementation, the second timing constraint formula may be as follows:

Tclk_FF1+Tc_FF1+Tcomb_logic-Thold≥Tclk_FF2

Wherein Tclk _{delay_FF1} may represent a first delay time required for the last level sequential element corresponding to the current intermediate sequential element to receive the clock signal. Tc _FF1 may represent the internal transition time of the last level sequential element corresponding to the current intermediate sequential element when processing the data signal. Tcomb _logic may represent the data transfer time required for a data signal to be transferred from the last-level sequential element corresponding to the current intermediate sequential element. Thold may represent the data signal hold time after the clock signal is received by the current sequential element. Tclk _FF2 may represent a second delay time required for the current intermediate sequential element to receive the clock signal.

For any intermediate timing element, a setup time violation occurs when the arrival time of the data signal is later than the arrival time of the clock valid signal. Therefore, the terminal device may calculate the first duration according to the first delay time, the internal transition time, the data transmission time, and the data signal establishment time, and calculate the second duration according to the second delay time and the period duration. When the first time length is longer than the second time length, that is, the current data signal setup time does not meet the first time constraint formula, the terminal device can determine that the total time length required by the data signal to be transmitted to the intermediate time sequence element is longer than the total time length required by the clock signal to be transmitted to the intermediate time sequence element, and when the arrival time of the data signal is later than the arrival time of the clock valid signal, it can be understood that the intermediate time sequence element has a setup time violation condition.

For any intermediate timing element, when a new data signal collected by a timing element of a previous hierarchy reaches the current intermediate timing element too soon, the original correct data may be flushed, so that the new data signal must be allowed to reach after a certain time. When the new data signal collected by the timing element of the previous hierarchy reaches the current middle timing element too fast, namely the middle timing element has a setup time violation condition. Therefore, the terminal device may calculate the third duration based on the first delay time, the internal transition time, the data transmission time, and the data signal hold time. Specifically, the third duration may be equal to a sum of the first delay time, the internal transition time, and the data transmission time minus the data signal hold time. When the third duration is less than the second delay time, that is, the current data signal holding time does not satisfy the second timing constraint formula, the terminal device may determine that the setup time violation condition occurs in the intermediate timing element.

In this embodiment, the time sequence violation conditions in the terminal device include a setup time violation condition and a hold time violation condition, and different judging methods are adopted for the two time sequence violation conditions respectively, so the accuracy of judging the time sequence violation can be improved by the method provided in this embodiment.

S14023, calculating the path time difference between any intermediate time sequence element and the time sequence element of the upper layer corresponding to any intermediate time sequence element.

In this embodiment, when a timing violation occurs in any one of the intermediate timing elements in the timing path, the terminal device may calculate the path time difference between the intermediate timing element and the timing element of the previous level corresponding to the intermediate timing element.

In one possible implementation manner, when a setup time violation occurs in a certain intermediate timing element in the timing path, the terminal device may determine a path time difference corresponding to the any intermediate timing element according to the setup time of the data signal corresponding to the intermediate timing element and a clock margin preset by a developer. Specifically, the terminal device may determine, in time Zhong Yuliang, a path time difference corresponding to the any intermediate timing element according to a difference between the first duration and the second duration calculated by the data signal setup time. The specific method for calculating the first duration and the second duration is shown in the content of the embodiment S14022, and will not be described herein.

In one possible implementation manner, when a hold time violation occurs in a certain intermediate time sequence element in the time sequence path, the terminal device may determine a path time difference corresponding to the any intermediate time sequence element according to a data signal hold time corresponding to the intermediate time sequence element and a clock margin preset by a developer. Specifically, the terminal device may determine, in time Zhong Yuliang, a path time difference corresponding to the any intermediate timing element according to a difference between the third duration and the second delay time calculated by the data signal hold time. The method for determining the third duration and the second delay time is shown in the content of the embodiment S14022, and will not be described herein.

S14024, determining a delay path between any intermediate time sequence element and the time sequence element of the last level corresponding to any intermediate time sequence element based on the path time difference and the unit delay time length.

In this embodiment, after determining the path time difference corresponding to the intermediate timing element of the timing violation, the terminal device may query the delay unit type table according to the input current value corresponding to the current timing adjustment circuit and the load capacity of the device connected to the subsequent timing adjustment circuit, so as to determine the candidate unit type corresponding to the current timing adjustment circuit from all the delay unit types. Then, the terminal device can determine the target unit type corresponding to the current time sequence path and the number of delay units corresponding to each target unit type according to the path time difference corresponding to the current intermediate time sequence element and the unit delay time length of each candidate unit type. The terminal equipment can generate a delay path corresponding to the current intermediate time sequence element according to the determined target unit type and the number of delay units corresponding to each target unit type.

Specifically, for any intermediate time sequence unit with a time sequence violation condition, the terminal device may sort the candidate unit types according to the unit delay duration corresponding to each candidate unit type from large to small, so as to determine the type order corresponding to each candidate unit type. Then, the terminal device may divide the path time difference by the longest unit delay period first, and divide the calculated remainder by the unit delay period corresponding to the candidate unit type of the next type order when there is a remainder, until the calculated remainder is 0. When the quotient calculated by a certain candidate unit type is greater than 0, the terminal device can determine that the candidate unit type is the delay unit number corresponding to the intermediate sequential element corresponding to the target unit type, and takes the calculated quotient as the delay unit number corresponding to the target unit type.

In one possible implementation, when a setup time violation occurs in a certain intermediate timing element, the terminal device may connect the determined delay path to the clock path of the intermediate timing element, i.e. the terminal device may connect the clock delay path to the clock input of the intermediate timing element, so that the intermediate timing element satisfies the timing convergence. When a hold time violation occurs in a certain intermediate timing element, the terminal device may connect the determined delay path to the data path of the intermediate timing element, that is, the terminal device may connect the data delay path to the data path between the intermediate timing element and the corresponding last-level timing element, so that the intermediate timing element satisfies timing convergence. For the intermediate time sequence element with the hold time violation condition, the terminal equipment can also connect the determined delay path to the clock path of the corresponding last-level time sequence element, that is, the terminal equipment can connect the clock delay path to the clock input end of the corresponding last-level time sequence element, so that the intermediate time sequence element meets the time sequence convergence.

In this embodiment, the terminal device may determine whether the intermediate timing element has a timing violation condition according to the data signal setup time and the data signal hold time, respectively, so the method provided in this embodiment may ensure accuracy when the terminal device determines the timing violation.

It should be noted that, the sequence number of each step in the above embodiment does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiment of the present application in any way.

Referring to fig. 17, a schematic diagram of a terminal device provided by an embodiment of the present application is shown. As shown in fig. 17, a terminal apparatus 1700 in an embodiment of the present application includes: a processor 1710, a memory 1720, and a computer program 1721 stored in the memory 1720 and executable on the processor 1710. The processor 1710, when executing the computer program 1721, implements the steps in the respective embodiments of the delay path determination method described above, for example, steps S1401 to S1403 shown in fig. 14.

Illustratively, the computer program 1721 may be partitioned into one or more modules/units that are stored in the memory 1720 and executed by the processor 1710 to accomplish the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which may be used to describe the execution of the computer program 1721 in the terminal device 1700.

The terminal device 1700 may include, but is not limited to, a processor 1710, a memory 1720. It will be appreciated by those skilled in the art that fig. 17 is merely an example of a terminal device 1700 and is not intended to limit the terminal device 1700, and may include more or less components than illustrated, or may combine certain components, or different components, e.g., the terminal device 1700 may also include input and output devices, network access devices, buses, etc.

The Processor 1710 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, input signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), off-the-shelf Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 1720 may be an internal storage unit of the terminal device 1700, such as a hard disk or a memory of the terminal device 1700. The memory 1720 may also be an external storage device of the terminal device 1700, such as a plug-in hard disk provided on the terminal device 1700, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD), or the like. Further, the memory 1720 may also include both internal storage units and external storage devices of the terminal device 1700. The memory 1720 is used to store the computer program 1721 and other programs and data required by the terminal device 1700. The memory 1720 may also be used to temporarily store data that has been output or is to be output.

The embodiment of the application also discloses a terminal device which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the processor realizes the method for determining the delay path in each embodiment when executing the computer program.

The embodiments of the present application also disclose a computer readable storage medium storing a computer program which, when executed by a processor, implements the method of determining a delay path as described in the previous embodiments.

The embodiment of the application also discloses a computer program product which enables a computer to execute the method for determining the delay path according to the previous embodiments when the computer program product runs on the computer.

The above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto. Although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A timing adjustment circuit, comprising:

at least two levels of sequential elements;

The clock selection module is used for receiving a plurality of clock source signals and outputting clock signals corresponding to the functional mode signals to the time sequence element according to the functional mode signals;

2. The timing adjustment circuit of claim 1, further comprising:

The time sequence elements comprise N time sequence elements which are connected in series, wherein the first N-1 time sequence elements which are connected in series are respectively correspondingly connected with one first delay selection module and/or one second delay selection module; and N is a positive integer greater than or equal to 2.

3. The timing adjustment circuit of claim 1, further comprising:

the time sequence elements of any level can comprise M time sequence elements connected in parallel, and the M time sequence elements connected in parallel are respectively and correspondingly connected with one first time delay selection module and/or second time delay selection module, wherein M is a positive integer greater than or equal to 2.

4. The timing adjustment circuit of claim 1, wherein the timing element comprises a first timing element and a second timing element, the data output of the first timing element being connected to the data input of the second timing element;

5. The timing adjustment circuit of any one of claims 1-4, wherein the first delay selection module comprises a plurality of data delay paths and a first selector; the second delay selection module includes a plurality of clock delay paths and a second selector:

at least one delay unit is arranged on any data delay path;

at least one delay unit is arranged on any clock delay path;

6. A method of determining a delay path, comprising:

And determining a delay path corresponding to the time sequence path according to the path time difference and the unit delay time length.

7. The method of claim 6, wherein the obtaining the path time difference for the timing path if the timing path has a timing violation comprises:

8. The method of claim 7, wherein the determining the corresponding delay path of the timing path based on the path time difference and the unit delay duration comprises:

9. The method of claim 7, wherein the timing violation conditions include a setup time violation condition and a hold time violation condition;

10. The method of claim 9, wherein the determining a delay path between the any intermediate timing element and a last level timing element corresponding to the any intermediate timing element based on the path time difference and the unit delay duration comprises:

11. Terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method of determining a delay path according to any of claims 6 to 10 when executing the computer program.

12. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the method of determining a delay path according to any one of claims 6 to 10.