CN118507535A - P-I-N heterojunction terminal and preparation method thereof - Google Patents
P-I-N heterojunction terminal and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000009830 intercalation Methods 0.000 claims abstract description 38
- 230000002687 intercalation Effects 0.000 claims abstract description 37
- 238000002161 passivation Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000009616 inductively coupled plasma Methods 0.000 claims description 10
- 238000001704 evaporation Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 238000004943 liquid phase epitaxy Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 83
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 31
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
The invention relates to a P-I-N heterojunction terminal and a preparation method thereof, belonging to the technical field of microelectronics. The terminal sequentially comprises a Ni ohmic electrode, a SiC substrate, an n + -SiC buffer layer and an n-SiC layer from bottom to top, wherein AlN intercalation layers are respectively arranged on the two sides of the n-SiC layer, a p-GaN cap layer is arranged on the upper side of the AlN intercalation layers, ni Schottky electrodes are arranged on the upper sides of the p-GaN cap layer and the n-SiC layer, au electrodes are arranged on the upper sides of the Ni Schottky electrodes, and SiO 2 passivation layers are arranged on the upper sides of the Au electrodes, the side sides of the Ni Schottky electrodes, the side sides of the p-GaN cap layer, the side sides of the AlN intercalation layers and the upper sides of the n-SiC layer. The SiC SBD can effectively improve the performance of the SiC SBD, and has the advantages of high breakdown voltage, high reliability and the like.
Description
Technical Field
The invention relates to a P-I-N heterojunction terminal and a preparation method thereof, belonging to the technical field of microelectronics.
Background
The traditional power electronic system mainly comprises a semiconductor material silicon (Si) base device, but with the high-speed development of electric automobiles, high-speed railways and 5G communication, the silicon base material is about to reach a physical limit, and cannot meet the working conditions of high power and high current. Silicon carbide (SiC) belongs to a third-generation semiconductor, and compared with a traditional silicon-based material, the silicon-based material has the advantages of wider forbidden band, higher electron saturation drift velocity, higher thermal conductivity, higher critical breakdown voltage and the like, and a semiconductor device prepared from the silicon carbide has great potential in a large-scale power electronic system, and a power device prepared from the silicon-based material mainly comprises a P-I-N diode, a schottky diode (SBD) and the like.
Silicon carbide schottky diodes (SBDs) are commercially available silicon carbide power devices of a certain scale, which have the characteristics of high operating power and high breakdown voltage. However, the boundary termination problem of SiC SBD limits its development, and structural defects at the edge of schottky metal play a decisive role in the breakdown voltage of the device due to the electric field spike discharge effect, so the termination structure of SiC SBD greatly affects its breakdown voltage, which is an urgent problem to be solved in SiC SBD development. For this purpose, the present invention is proposed.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the P-I-N heterojunction terminal which can effectively improve the performance of the SiC SBD and has the advantages of high breakdown voltage, high reliability and the like.
The invention also provides a preparation method of the P-I-N heterojunction terminal
The technical scheme of the invention is as follows:
The P-I-N heterojunction terminal sequentially comprises a Ni ohmic electrode, a SiC substrate, an N + -SiC buffer layer and an N-SiC layer from bottom to top, wherein an AlN intercalation layer is arranged on the outer side of the N-SiC layer, a P-GaN cap layer is arranged on the upper side of the AlN intercalation layer, ni Schottky electrodes are arranged on the upper side of the P-GaN cap layer and the upper side of the N-SiC layer, au electrodes are arranged on the upper side of the Ni Schottky electrodes, and SiO 2 passivation layers are arranged on the upper side of the Au electrodes, the side of the Ni Schottky electrodes, the side of the P-GaN cap layer, the side of the AlN intercalation layer and the upper side of the N-SiC layer.
According to the present invention, the SiC substrate preferably has a thickness of 350 to 500. Mu.m, more preferably 350. Mu.m;
The thickness of the n + -SiC buffer layer is 0.2-2 mu m, and the thickness of the n + -SiC buffer layer is 1 mu m;
the thickness of the n-SiC layer is 1 to 100. Mu.m, preferably, the thickness of the n-SiC layer is 10. Mu.m;
the thickness of the AlN intercalation is 1-1000 nm, preferably, the thickness of the AlN intercalation is 100nm;
The thickness of the p-GaN cap layer is 1-2000 nm, and the thickness of the p-GaN cap layer is 100nm preferably;
The thickness of the Ni ohmic electrode is 10to 1000nm, and preferably the thickness of the Ni ohmic electrode is 200nm.
According to the invention, the doping source of the N + -SiC layer is N element, the N-type doping concentration is 1×10 16～1×1019cm-3, and the N-type doping concentration of the N + -SiC buffer layer is 1×10 17cm-3;
the doping source of the N-SiC layer is N element, the doping concentration of the N-SiC layer is 1 multiplied by 10 15～1×1017cm-3, and the doping concentration of the N-SiC layer is 5 multiplied by 10 15cm-3 preferably;
The doping source of the p-GaN cap layer is Mg element, the doping concentration of the p-GaN cap layer is 1 multiplied by 10 17～1×1020cm-3, and the doping concentration of the p-GaN cap layer is preferably 1 multiplied by 10 19cm-3.
The preparation method of the P-I-N heterojunction terminal comprises the following steps:
S1, sequentially epitaxially growing an n + -SiC layer and an n-SiC layer on a SiC substrate;
S2, growing an AlN intercalation layer and a p-GaN cap layer above the n-SiC layer;
s3, removing part of the AlN intercalation and the p-GaN cap layer through dry etching;
S4, evaporating a metal Ni ohmic electrode below the SiC substrate, and annealing to form ohmic contact;
S5, evaporating a metal Ni Schottky electrode and a metal Au electrode above the n-SiC layer, the AlN intercalation layer and the p-GaN cap layer to form Schottky contact;
S6, growing a SiO 2 passivation layer on the upper side of the n-SiC layer, the side of the AlN intercalation layer, the side of the p-GaN cap layer, the side of the Ni Schottky electrode and the upper side of the Au electrode;
s7, forming holes in the SiO 2 passivation layer.
In step S1, the n + -SiC buffer layer and the n-SiC layer are preferably grown by a high-quality film forming method such as Liquid Phase Epitaxy (LPE), chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE), and preferably Chemical Vapor Deposition (CVD).
According to a preferred embodiment of the present invention, in step S2, the growth method of the AlN intercalation and the p-GaN cap layer is a high quality film forming method such as a Metal Organic Chemical Vapor Deposition (MOCVD) method or a Molecular Beam Epitaxy (MBE) method, preferably a Metal Organic Chemical Vapor Deposition (MOCVD) method.
According to a preferred embodiment of the present invention, in step S3, the dry etching is inductively coupled plasma etching (ICP) or Reactive Ion Etching (RIE), preferably inductively coupled plasma etching (ICP).
According to the invention, in the step S4 and the step S5, the evaporation method of the Ni ohmic electrode, the Ni Schottky electrode and the Au electrode is electron beam evaporation or magnetron sputtering, preferably magnetron sputtering;
In step S4, the Ni ohmic electrode is annealed at 950 ℃ in N 2 for 40S.
In a preferred embodiment of step S6, the SiO 2 passivation layer is grown by Low Pressure Chemical Vapor Deposition (LPCVD).
The invention has the beneficial effects that:
1. Higher breakdown voltage:
Compared with the conventional SiC SBD, the P-I-N heterojunction terminal structure is formed by the P-GaN/AlN/N-SiC, so that a space charge region is formed, a grid fringe electric field is offset to a certain extent, the breakdown voltage of the SiC SBD is improved, meanwhile, due to the existence of AlN intercalation, the space charge region is widened, and the breakdown voltage of the SiC SBD is further improved.
The SiC, gaN and AlN materials used in the invention have larger difference in energy band height, so that larger band step difference is formed between n-SiC/AlN/p-GaN, and larger potential barrier height is formed at the interface of the n-SiC/AlN/p-GaN, thereby greatly improving the breakdown voltage of the device.
Meanwhile, the AlN intercalation improves the interface quality of n-SiC/AlN/p-GaN, reduces the material defects at the junction of three materials, and can also improve the breakdown voltage of the device.
2. High reliability:
Compared with the conventional SiC SBD which is subjected to ion implantation to obtain P-SiC or is subjected to passivation and field plate technology to form a device structure to cause material damage and reduce the reliability of the device, the invention greatly improves the reliability of the device by using the N-SiC/AlN/P-GaN P-I-N structure as a terminal junction and the growth quality of the material is far superior to that of a passivation layer formed by deposition.
3. The product yield is improved:
According to the invention, alN intercalation is added in the n-SiC layer and the p-GaN cap layer, so that p-GaN is easy to grow on a wafer, the material quality of the p-GaN is greatly improved, the reliability of a device is increased, and the yield of the device is improved. In addition, the invention adopts the epitaxial growth P-GaN to replace the ion implantation process, the SiC ion implantation is realized by carrying out repeated implantation at high temperature, the equipment requirement and the process requirement are high, the N-SiC/AlN/P-GaN P-I-N structure adopted by the invention is avoided, the ion implantation process is avoided, the yield of products is improved, and the preparation cost of devices is reduced.
Drawings
FIG. 1 is a schematic view of the structure of a SiC substrate of the present invention;
FIG. 2 is a schematic diagram of the structure of the product in step S1 according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of the structure of the product in step S2 according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of the structure of the product in step S3 according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of the structure of the product in step S4 according to the embodiment of the present invention;
FIG. 6 is a schematic diagram of the structure of the product in step S5 according to the embodiment of the present invention;
FIG. 7 is a schematic diagram of the structure of the product in step S6 according to the embodiment of the present invention;
FIG. 8 is a schematic diagram of the structure of the product in step S7 according to the embodiment of the present invention;
FIG. 9 is a space charge block diagram obtained by conventional dead-end-free SiC SBD simulation;
FIG. 10 is a space charge region layout simulated by an embodiment of the present invention;
FIG. 11 is a diagram of a simulated energy band structure of an embodiment of the present invention;
FIG. 12 is a graph of breakdown voltage comparison of a simulated unterminated SiC SBD with an embodiment of the invention;
Wherein: 101. a SiC substrate; 102. n + -SiC buffer layer; 103. an n-SiC layer; 104. an AlN intercalation; 105. a p-GaN cap layer; 106. a Ni ohmic electrode; 107. a Ni Schottky electrode; 108. an Au electrode; 109. and a SiO 2 passivation layer.
Detailed Description
The invention will now be further illustrated by way of example, but not by way of limitation, with reference to the accompanying drawings.
Example 1:
The embodiment provides a P-I-N heterojunction terminal, which sequentially comprises a Ni ohmic electrode 106, a SiC substrate 101, an N + -SiC buffer layer 102 and an N-SiC layer 103 from bottom to top, wherein an AlN intercalation 104 is arranged on the outer side of the N-SiC layer 103, a P-GaN cap layer 105 is arranged on the upper side of the AlN intercalation 104, ni Schottky electrodes 107 are arranged on the upper side of the P-GaN cap layer 105 and the upper side of the N-SiC layer 103, au electrodes 108 are arranged on the upper side of the Ni Schottky electrodes 107, siO 2 passivation layers 109 are arranged on the side of the Ni Schottky electrodes 107, the side of the P-GaN cap layer 105, the side of the AlN intercalation 104 and the upper side of the N-SiC layer 103. The SiC substrate 101, the N + -SiC buffer layer 102, the N-SiC layer 103, the AlN intercalation 104 and the P-GaN cap layer 105 form a P-I-N heterojunction; the SiC substrate 101, the n + -SiC buffer layer 102, the n-SiC layer 103, the Ni ohmic electrode 106, the metal Ni Schottky electrode 107, the metal Au electrode 108 and the SiO 2 passivation layer 109 form a Schottky diode.
The SiC substrate has a thickness of 350 μm, the n + -SiC buffer layer has a thickness of 1 μm, the n-SiC layer has a thickness of 10 μm, the AlN intercalating layer has a thickness of 100nm, the p-GaN cap layer has a thickness of 100nm, and the Ni ohmic electrode has a thickness of 200nm.
The doping source of the N + -SiC layer is N element, and the N-type doping concentration is 1 multiplied by 10 17cm-3;
The doping source of the N-SiC layer is N element, and the doping concentration of the N-SiC layer is 5 multiplied by 10 15cm-3;
the doping source of the p-GaN cap layer is Mg element, and the doping concentration of the p-GaN cap layer is 1 multiplied by 10 19cm-3.
The preparation method of the P-I-N heterojunction terminal comprises the following steps:
s1, sequentially epitaxially growing an n + -SiC layer and an n-SiC layer on a SiC substrate by adopting Chemical Vapor Deposition (CVD);
s2, growing an AlN intercalation layer and a p-GaN cap layer above the n-SiC layer by adopting a Metal Organic Chemical Vapor Deposition (MOCVD);
s3, removing part of the AlN intercalation and the p-GaN cap layer through Inductively Coupled Plasma (ICP);
S4, evaporating a metal Ni ohmic electrode below the SiC substrate by adopting magnetron sputtering, and annealing to form ohmic contact, wherein the annealing treatment mode is annealing for 40S at 950 ℃ in N 2;
s5, evaporating a metal Ni Schottky electrode and a metal Au electrode above the n-SiC layer, the AlN intercalation layer and the p-GaN cap layer by adopting magnetron sputtering to form Schottky contact;
S6, growing a SiO 2 passivation layer on the upper side of the n-SiC layer, the side of the AlN intercalation, the side of the p-GaN cap layer, the side of the Ni Schottky electrode and the upper side of the Au electrode by adopting a Low Pressure Chemical Vapor Deposition (LPCVD);
S7, perforating a SiO 2 passivation layer, wherein the method comprises the following specific steps of: and (3) coating photoresist on the epitaxial material obtained in the step S6, exposing a SiO 2 passivation layer area needing to be opened by utilizing a photoetching development technology on the photoresist, etching the SiO 2 passivation layer by utilizing an ICP device, and then removing the coated photoresist by utilizing a chemical solution to realize the opening of the SiO 2 passivation layer.
In step S3, the specific steps of inductively coupled plasma etching (ICP) are as follows:
And (2) coating photoresist on the epitaxial material obtained in the step (S2), exposing a region to be etched on the photoresist by utilizing a photoetching development technology, etching the AlN intercalation and the p-GaN cap layer by using an ICP device, and removing the coated photoresist by using a chemical solution.
Fig. 9 is a space charge area distribution diagram obtained by conventional dead-end SiC SBD simulation, and fig. 10 is a space charge area distribution diagram obtained by example simulation, and it can be seen from comparison of fig. 9 and 10 that the P-I-N structure composed of P-GaN/AlN/N-SiC of the present invention greatly expands the space charge area.
Fig. 11 is a diagram showing a simulated band structure of an embodiment, and as can be seen from fig. 11, the band difference between the AlN intercalation and the n-SiC layer is 4.19eV, which makes a large barrier height exist at the interface between the AlN intercalation and the n-SiC layer.
Fig. 12 is a graph comparing breakdown voltages of the non-terminated SiC SBD obtained by simulation with those of the embodiment, and as can be seen from fig. 12, the breakdown voltage of the non-terminated SiC SBD is 1255V, the breakdown voltage of the P-I-N structure composed of N-SiC-AlN-P-GaN of the embodiment is 1959V, which improves by 56%, and proves the effectiveness of the embodiment for improving breakdown voltage.
The foregoing is illustrative of the present invention and is not to be construed as limiting thereof, but rather as various modifications, equivalent arrangements, improvements, etc., which fall within the spirit and principles of the present invention.
Claims (9)
1. The P-I-N heterojunction terminal is characterized by sequentially comprising a Ni ohmic electrode, a SiC substrate, an N + -SiC buffer layer and an N-SiC layer from bottom to top, wherein an AlN intercalation layer is arranged on the outer side of the N-SiC layer, a P-GaN cap layer is arranged on the upper side of the AlN intercalation layer, ni Schottky electrodes are arranged on the upper side of the P-GaN cap layer and the upper side of the N-SiC layer, au electrodes are arranged on the upper side of the Ni Schottky electrodes, and SiO 2 passivation layers are arranged on the upper side of the Au electrodes, the side of the Ni Schottky electrodes, the side of the P-GaN cap layer, the side of the AlN intercalation layer and the upper side of the N-SiC layer.
2. The P-I-N heterojunction termination of claim 1, wherein the SiC substrate has a thickness of 350-500 μm;
The thickness of the n + -SiC buffer layer is 0.2-2 mu m;
The thickness of the n-SiC layer is 1-100 mu m;
the thickness of AlN intercalation is 1-1000 nm;
The thickness of the p-GaN cap layer is 1-2000 nm;
the thickness of the Ni ohmic electrode is 10-1000 nm.
3. The P-I-N heterojunction termination of claim 2, wherein the N + -SiC layer has a doping source of N element and an N-type doping concentration of 1x10 16～1×1019cm-3;
The doping source of the N-SiC layer is N element, and the doping concentration of the N-SiC layer is 1 multiplied by 10 15～1×1017cm-3;
The doping source of the p-GaN cap layer is Mg element, and the doping concentration of the p-GaN cap layer is 1 multiplied by 10 17～1×1020cm-3.
4. A method for preparing a P-I-N heterojunction terminal as claimed in claim 3, characterized by the steps of:
S1, sequentially epitaxially growing an n + -SiC layer and an n-SiC layer on a SiC substrate;
S2, growing an AlN intercalation layer and a p-GaN cap layer above the n-SiC layer;
s3, removing part of the AlN intercalation and the p-GaN cap layer through dry etching;
S4, evaporating a metal Ni ohmic electrode below the SiC substrate, and annealing to form ohmic contact;
S5, evaporating a metal Ni Schottky electrode and a metal Au electrode above the n-SiC layer, the AlN intercalation layer and the p-GaN cap layer to form Schottky contact;
S6, growing a SiO 2 passivation layer on the upper side of the n-SiC layer, the side of the AlN intercalation layer, the side of the p-GaN cap layer, the side of the Ni Schottky electrode and the upper side of the Au electrode;
s7, forming holes in the SiO 2 passivation layer.
5. The method of claim 4, wherein in the step S1, the N + -SiC buffer layer and the N-SiC layer are grown by liquid phase epitaxy, chemical vapor deposition or molecular beam epitaxy.
6. The method for fabricating a P-I-N heterojunction terminal as claimed in claim 4, wherein in step S2, the growth method of the AlN intercalation and the P-GaN cap layer is a metal organic chemical vapor deposition method or a molecular beam epitaxy method.
7. The method of manufacturing a P-I-N heterojunction terminal as claimed in claim 4, wherein in step S3, the dry etching is inductively coupled plasma etching or reactive ion etching.
8. The method for preparing a P-I-N heterojunction terminal as claimed in claim 4, wherein in the step S4 and the step S5, the evaporation method of the Ni ohmic electrode, the Ni schottky electrode and the Au electrode is electron beam evaporation or magnetron sputtering;
In step S4, the Ni ohmic electrode is annealed at 950 ℃ in N 2 for 40S.
9. The method of claim 4, wherein in step S6, the SiO 2 passivation layer is grown by low pressure chemical vapor deposition.
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