CN118467239A - Data acquisition method, hard disk and readable storage medium - Google Patents

Abstract

The present application relates to the field of storage technologies, and in particular, to a data acquisition method, a hard disk, and a readable storage medium, where the method includes: acquiring an error correction voltage set of a hard disk, wherein the error correction voltage set comprises a plurality of offset voltage values; verifying the error correction voltage set based on a plurality of original data to be verified read under a plurality of offset voltage values; when the error correction voltage set passes the verification, reading original data of a target page in the hard disk flash memory based on the error correction voltage set, wherein the original data to be verified is part of the original data; storing the read plurality of original offset data into different buffer areas, wherein the original offset data read under each offset voltage value are placed in the same buffer area; and sequentially acquiring corresponding original offset sub-data from different cache areas respectively for error correction so as to acquire a plurality of target data. The application can save a great deal of time when acquiring the target data in the hard disk.

Description

Data acquisition method, hard disk and readable storage medium

Technical Field

The present application relates to the field of storage technology, and in particular to a data acquisition method, a hard disk and a readable storage medium.

Background Art

Existing hard disk data decoding usually adopts hard decoding, soft decoding or a combination of hard and soft decoding. Soft decoding is now mostly used for error correction. This is because soft decoding has stronger error correction capabilities than hard decoding. However, during the soft decoding process, since the data size of each error correction is limited, each page of data needs to be read and exported multiple times to complete multiple error corrections, which greatly increases the time consumed by the error correction process.

Summary of the invention

In view of the above problems, the present application proposes a data acquisition method, a hard disk and a readable storage medium.

The present application embodiment provides a data acquisition method, including:

Acquire an error correction voltage set of a hard disk, wherein the error correction voltage set includes a plurality of offset voltage values;

Verifying the error correction voltage set based on a plurality of original to-be-verified data read at the plurality of offset voltage values;

When the error correction voltage set is verified, original data of a target page in the hard disk flash memory is read based on the error correction voltage set, wherein the original data to be verified is part of the original data;

storing the read multiple original offset data in different buffer areas, wherein the original offset data read at each offset voltage value is placed in the same buffer area;

The corresponding original offset sub-data are sequentially obtained from the different buffer areas for error correction to obtain a plurality of target data.

Furthermore, in the above data acquisition method, the error correction voltage set includes a main bias voltage value, a left bias voltage value and a right bias voltage value, and the original offset data includes original main bias data, original left bias data and original right bias data; and reading the original data of the target page in the hard disk flash memory based on the error correction voltage set includes:

The original data of the target page is read based on the main bias voltage value, the left bias voltage value and the right bias voltage value respectively, and the original main bias data, the original left bias data and the original right bias data are obtained accordingly.

Further, in the above data acquisition method, each of the original offset data is divided into a plurality of original offset sub-data of the same size, each of the original offset sub-data corresponds to a sub-portion of the original data, and all the original offset sub-data corresponding to the same sub-portion correspond to each other; the original offset sub-data includes original main offset sub-data, original left offset sub-data and original right offset sub-data; the corresponding original offset sub-data are sequentially acquired from the different buffer areas for error correction to acquire a plurality of target data, including:

Sequentially acquiring mutually corresponding original offset sub-data from the different buffer areas for error correction;

When the bit error rate of the original main bias sub-data does not fall within the first preset range, the original main bias sub-data is used as the target data;

When the bit error rate of the original main bias sub-data belongs to the first preset range, and the bit error rate of the original left bias sub-data does not belong to the first preset range, the original left bias sub-data is used as the target data;

When the bit error rates of the original main bias sub-data and the original left bias sub-data both belong to the first preset range, and the bit error rate of the original right bias sub-data does not belong to the first preset range, the original right bias sub-data is used as the target data;

When the bit error rates of the original main bias sub-data, the original left bias sub-data, and the original right bias sub-data all belong to the first preset range, it is confirmed that the error correction has failed.

Furthermore, in the above data acquisition method, it also includes:

The data volume of the original offset sub-data and the data volume of the original data to be verified are both less than or equal to the maximum data volume that can be corrected at one time.

Furthermore, in the above data acquisition method, the verification of the error correction voltage set based on the multiple original data to be verified read under the multiple offset voltage values includes:

The original data to be verified are read using the main bias voltage value, the left bias voltage value and the right bias voltage value respectively, and main bias verification data, left bias verification data and right bias verification data are obtained correspondingly;

The error correction voltage set is verified based on the main bias verification data, the left bias verification data and the right bias verification data.

Further, in the above data acquisition method, the verifying the error correction voltage set based on the main bias verification data, the left bias verification data and the right bias verification data includes:

When the bit error rate of the main bias verification data, the left bias verification data or the right bias verification data does not fall within a second preset range, it is confirmed that the error correction voltage set verification has passed;

When the bit error rates of the main bias verification data, the left bias verification data, and the right bias verification data all belong to the second preset range, it is confirmed that the error correction voltage set verification has failed.

Furthermore, in the above data acquisition method, it also includes:

When the original offset sub-data is corrected, the original data of the next target page in the hard disk flash memory is also read based on the error correction voltage set to obtain the target data corresponding to the next target page until the target data of all target pages are obtained.

Furthermore, in the above data acquisition method, it also includes:

When the error correction fails or the error correction voltage set verification fails, the process returns to the step of obtaining the error correction voltage set of the hard disk, and uses the obtained new voltage value as the error correction voltage set.

Another embodiment of the present application further proposes a hard disk, including a storage unit and a processing unit, wherein the storage unit stores a computer program, and the processing unit executes the steps of the above-mentioned data acquisition method by calling the computer program stored in the storage unit.

Another embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor to execute the steps of the above-mentioned data acquisition method.

The embodiments of the present application have the following beneficial effects:

The embodiment of the present application proposes a data acquisition method, including: obtaining an error correction voltage set of a hard disk, the error correction voltage set including multiple offset voltage values; verifying the error correction voltage set based on multiple original data to be verified read under multiple offset voltage values; when the error correction voltage set is verified, reading the original data of the target page in the flash memory of the hard disk based on the error correction voltage set, wherein the original data to be verified is part of the original data; storing the multiple original offset data read in different cache areas, wherein the original offset data read under each offset voltage value is placed in the same cache area; respectively obtaining the corresponding original offset sub-data from different cache areas in turn for error correction to obtain a number of target data. The present application saves a lot of time by reading all the data of each page at one time according to different offset voltages, and there is no need to read different data in each page multiple times before subsequent error correction, but directly obtaining the corresponding data from the cache area for error correction.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope of protection of the present application. In each of the drawings, similar components are numbered similarly.

FIG1 shows a first schematic diagram of a data acquisition method in some embodiments of the present application;

FIG2 shows a second flow chart of the data acquisition method in some embodiments of the present application;

FIG3 shows a third flow chart of the data acquisition method in some embodiments of the present application;

FIG4 is a schematic diagram showing a target page structure of a data acquisition method in some embodiments of the present application;

FIG5 is a schematic diagram showing the structure of a data acquisition system according to some embodiments of the present application.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing items.

Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

Generally, during the soft decoding process, since the amount of data to be corrected each time is limited, each page of data needs to be read multiple times, with a portion of the data on each page being read each time, and the error is corrected each time until the page of data is corrected. When multiple pages or even more pages of data need to be corrected, the entire process takes longer.

Therefore, in order to solve the above problem, the present application proposes a data acquisition method.

Please refer to Figure 1, which is a flow chart of a data acquisition method proposed in an embodiment of the present application. Exemplarily, the data acquisition method is applied to a solid state drive.

In some embodiments, as shown in FIG1 , the data acquisition method includes:

S110, obtaining an error correction voltage set of the hard disk, where the error correction voltage set includes a plurality of offset voltage values.

Specifically, since hard disks have corresponding parameter tables when they leave the factory, the error correction voltage set of the corresponding hard disk can be obtained through these tables or other methods. The offset voltage value in the error correction voltage set can be set to read data from the hard disk. The data read at the same hard disk position will be different using different offset voltage values.

S210 , verifying the error correction voltage set based on a plurality of original to-be-verified data read at a plurality of offset voltage values.

Specifically, since the same page of data can basically use the same offset voltage to complete the error correction operation, but different pages of data may require different offset voltages, in order to reduce the reading time, it is necessary to determine whether the currently selected offset voltage set is correct before correcting the entire page of data. Therefore, it is necessary to use the current offset voltage set to verify a portion of the data in the current target page (as the original data to be verified), and then determine whether the current error correction voltage set is available.

In some embodiments of the data acquisition method, as shown in FIG. 2 , based on a plurality of original to-be-verified data read at a plurality of offset voltage values, the error correction voltage set is verified, including:

S211 , respectively using the main bias voltage value, the left bias voltage value and the right bias voltage value to read the original data to be verified in the target page, and correspondingly obtaining the main bias verification data, the left bias verification data and the right bias verification data.

S212, verifying the error correction voltage set based on the main bias verification data, the left bias verification data, and the right bias verification data.

Specifically, if the original data to be verified passes error correction, it means that the currently selected offset voltage set is available, and the offset voltage set can be used to correct all data in the current target page. If the original data to be verified fails to be corrected, it means that the currently selected offset voltage set is not available, and a new offset voltage set needs to be obtained to correct the current target page. In this embodiment, before correcting each page, some data in the current target page is corrected to determine whether the currently selected offset voltage set has passed verification, so as to update the offset voltage set in time.

S310, when the error correction voltage set verification passes, the original data of the target page in the hard disk flash memory is read based on the error correction voltage set, wherein the original data to be verified is part of the original data; and the read multiple original offset data are stored in different cache areas, wherein the original offset data read under each offset voltage value is placed in the same cache area.

Specifically, the data stored in the hard disk flash memory is called raw data, and the raw data is read with different offset voltages, and the read data is used as the raw offset data. The reason for distinguishing raw data and raw offset data is that the stored data and the read data are not necessarily the same. Since the amount of data read each time is large, there will be errors in some data, so it is necessary to read with multiple voltages, and different data will be obtained by reading with different voltages, and then error correction is performed according to the raw offset data obtained by each voltage. In order to improve the reading efficiency, this embodiment no longer divides the raw data into multiple sub-parts according to the traditional method, and then only reads one of the sub-parts each time and then corrects the errors of the read sub-parts, and cycles in sequence until all the raw data are corrected. For example, if only 16K raw data needs to be corrected, if the traditional method is to read and correct the errors with 1K each time, it needs to be read 16 times. If according to this embodiment, it is only necessary to read 16K data once and put it into the cache area, and store different raw offset data in different cache areas. Obviously, the number of reads in this embodiment is greatly reduced.

It should be noted that cache is different from flash memory. The time to read data from flash memory is much longer than the time to read from cache. Therefore, it will be faster to put the original offset data in the cache and then read the data from the cache for error correction.

In some embodiments of the data acquisition method, the error correction voltage set includes a main bias voltage value, a left bias voltage value, and a right bias voltage value, and the original offset data includes original main bias data, original left bias data, and original right bias data; the original data of the target page in the hard disk flash memory is read based on the error correction voltage set, and the read multiple original offset data are stored in different cache areas, including:

The original data of the target page is read based on the main bias voltage value, the left bias voltage value and the right bias voltage value, respectively, to obtain original main bias data, original left bias data and original right bias data accordingly.

Specifically, the error correction voltage set includes but is not limited to a main bias voltage value, a left bias voltage value, and a right bias voltage value. The main bias voltage value is a reference voltage for reading original data, and the left bias voltage value and the right bias voltage value are both obtained by floating up and down based on the main bias voltage value. In addition, the same error correction voltage set may include multiple left bias voltage values and/or multiple right bias voltage values, which are not limited here.

In some embodiments of the data acquisition method, verifying the error correction voltage set based on the main bias verification data, the left bias verification data, and the right bias verification data includes:

When the bit error rate of the main bias verification data, the left bias verification data or the right bias verification data does not belong to the second preset range, it is confirmed that the error correction voltage set verification has passed.

When the bit error rates of the main bias verification data, the left bias verification data, and the right bias verification data all belong to the second preset range, it is confirmed that the error correction voltage set verification has failed.

Specifically, the second preset range is a range where the bit error rate fails. For example, if the second preset range is not less than 30%, if the bit error rates of the main bias verification data, the left bias verification data, or the right bias verification data are not less than 30%, that is, the bit error rate is greater than or equal to 30%, then the use of the error correction voltage set results in a too high bit error rate, indicating that the current error correction voltage set verification has failed. As long as the bit error rate of any one of the main bias verification data, the left bias verification data, or the right bias verification data does not fall within the second preset range, it means that there is an offset verification data (such as the main bias verification data, the left bias verification data, or the right bias verification data) in the current error correction voltage set that can make the accuracy of reading the original data meet the requirements, that is, it means that the current error correction voltage set verification has passed.

It should be noted that the reason why multiple offset voltages are selected for error correction is that when the data read with the current offset voltage is unsuccessful, that is, when the bit error rate does not pass, the data successfully read with other offset voltages can be used for subsequent decoding operations. Therefore, when the data read with the first offset voltage is unsuccessful, it will be determined whether the data read with the second offset voltage is successful, until successful data is obtained.

S410, obtaining corresponding original offset sub-data from different buffer areas in sequence for error correction to obtain a plurality of target data.

Exemplarily, if the first buffer stores the first type of original offset data, the second buffer stores the second type of original offset data, and the third buffer stores the third type of original offset data, and the first type of original offset data includes the first type of sub-data a, the first type of sub-data b, ..., the first type of sub-data n; the second type of original offset data includes the second type of sub-data a, the second type of sub-data b, ..., the second type of sub-data n; and the third type of original offset data includes the third type of sub-data a, the third type of sub-data b, ..., the third type of sub-data n. Then the first type of sub-data a, the second type of sub-data a, and the third type of sub-data a are acquired for the first time, and error correction is performed through the three types of sub-data, and the corresponding target data a is obtained after the error correction is completed; the first type of sub-data b, the second type of sub-data b, and the third type of sub-data b are acquired for the second time, and error correction is performed through the three types of sub-data, and the corresponding target data b is obtained after the error correction is completed; and the error correction is continued in sequence until all the original offset data are corrected and all the corresponding target data are obtained.

In the data acquisition method of some embodiments, as shown in FIG3 , each original offset data is divided into a plurality of original offset sub-data of the same size, each original offset sub-data corresponds to a sub-portion of the original data, and all original offset sub-data corresponding to the same sub-portion correspond to each other; the original offset sub-data include original main offset sub-data, original left offset sub-data, and original right offset sub-data; the corresponding original offset sub-data are sequentially acquired from different buffer areas for error correction to acquire a plurality of target data, including:

S411, sequentially obtaining corresponding original offset sub-data from different buffer areas for error correction.

Exemplarily, if the original main bias data is stored in the first buffer area, the original left bias data is stored in the second buffer area, and the original right bias data is stored in the third buffer area, and the original main bias data includes original main bias sub-data a, original main bias sub-data b, ..., original main bias sub-data n; the original left bias data includes original left bias sub-data a, original left bias sub-data b, ..., original left bias sub-data n; the original right bias data includes original right bias sub-data a, original right bias sub-data b, ..., original right bias sub-data n. If the original main bias sub-data, the original left bias sub-data, and the original right bias sub-data are read from the same sub-portion of the original data by different offset voltage values, then the original main bias sub-data, the original left bias sub-data, and the original right bias sub-data correspond to each other. For example, if the original main bias sub-data a, the original left bias sub-data a, and the original right bias sub-data a are read from the same sub-portion by different voltages, then the original main bias sub-data a, the original left bias sub-data a, and the original right bias sub-data a correspond to each other. The error correction process is the process of determining the bit error rate of each original offset sub-data, and the purpose of error correction is to obtain target data.

S412: When the bit error rate of the original main bias sub-data does not fall within the first preset range, the original main bias sub-data is used as the target data.

S413, when the bit error rate of the original main bias sub-data belongs to the first preset range, and the bit error rate of the original left bias sub-data does not belong to the first preset range, the original left bias sub-data is used as the target data.

S414, when the bit error rates of the original main bias sub-data and the original left bias sub-data both belong to the first preset range, and the bit error rate of the original right bias sub-data does not belong to the first preset range, the original right bias sub-data is used as the target data.

S415, when the bit error rates of the original main bias sub-data, the original left bias sub-data and the original right bias sub-data all belong to the first preset range, it is confirmed that the error correction has failed.

Specifically, the bit error rates of the original main bias sub-data, the original left bias sub-data and the original right bias sub-data corresponding to each other are judged in sequence to obtain the corresponding target data.

Exemplarily, if the bit error rates of the corresponding original main bias sub-data c, original left bias sub-data c and original right bias sub-data c are 10%, 8% and 1% respectively, and the first preset range is not less than 2%, then it is limited to judge that the bit error rate of the original main bias sub-data c is 10% and belongs to the first preset range, and continue to judge that the bit error rate of the original left bias sub-data c is 8%, and it is found that it still belongs to the first preset range, and continue to judge that the bit error rate of the original right bias sub-data c is 1% and does not belong to the first preset range, then the original right bias sub-data is used as the target data of the sub-portion of the corresponding original data, and continue to obtain the target data of the next sub-portion of the original data until all the target data are obtained. Of course, the above judgment order is only an example, and it can also be other orders, which are not limited here. For example, the order can be original left bias sub-data, original main bias sub-data and original right bias sub-data, etc.

In some embodiments, the data acquisition method further comprises:

When correcting the original offset sub-data, the original data of the next target page in the hard disk flash memory is also read based on the error correction voltage set to obtain the target data corresponding to the next target page until the target data of all target pages are obtained.

Specifically, the above-mentioned process is only a process of obtaining target data for the same target page. In practical applications, target data is often obtained for multiple target pages and the target data is decoded. Therefore, this embodiment proposes that when correcting the error of the current target page, the original data of the next target page will also be read at the same time, and the multiple original offset data of the original data will be stored in different buffer areas, which greatly saves the reading time.

In some embodiments, the data acquisition method further comprises:

When the error correction fails or the error correction voltage set verification fails, the process returns to the step of obtaining the error correction voltage set of the hard disk, and uses the obtained new voltage value as the error correction voltage set.

Specifically, error correction failure refers to the error correction failure result that occurs when the corresponding original offset sub-data are obtained from different cache areas for error correction. Among them, error correction failure means that the error correction voltage set verification has not passed. Failure of error correction voltage set verification generally occurs in two scenarios of the above scheme. The first is the process of verifying the error correction voltage set based on the original data to be verified; the second is the process of sequentially obtaining the corresponding original offset sub-data from different cache areas for error correction. Regardless of the scenario, as long as the error correction voltage set verification fails or error correction fails, it is necessary to return to the initial step of obtaining the error correction voltage set of the hard disk to obtain a new error correction voltage set, and then repeat the above steps again based on the new error correction voltage set.

It should be noted that the target page read again is no longer the previous target page, but a new target page obtained from the sub-portion of the original data corresponding to the original offset sub-data when the previous one failed. For example, if the current target page has 16K original data, the next target page also has 16K original data. If the original data of each target page is divided into 8 sub-portions, the size of each sub-portion data is 2K. If the error correction voltage set verification fails when obtaining the target data of the second sub-portion in the current target page, it is necessary to return to the step of obtaining the error correction voltage set of the hard disk, and at this time read the new target page in the hard disk flash memory based on the new error correction voltage set. As shown in Figure 4, the new target page consists of the above-mentioned 7 sub-portions after the current target page and the first sub-portion in the next target page.

It should be noted that in the above implementation scheme, the data volume of the original offset sub-data and the data volume of the original data to be verified are both less than or equal to the maximum data volume that can be corrected at one time. Otherwise, it is impossible to correct them all at one time to improve efficiency.

The embodiment of the present application proposes a data acquisition method, including: obtaining an error correction voltage set of a hard disk, the error correction voltage set including multiple offset voltage values; reading the original data of a target page in the flash memory of the hard disk based on the error correction voltage set, and storing the read multiple original offset data in different cache areas, wherein each original offset data corresponds to the original data; respectively obtaining the corresponding original offset sub-data from different cache areas in sequence for error correction to obtain a number of target data. The present application reads all the data of each page at one time according to different offset voltages, and before subsequent error correction, there is no need to read different data in each page multiple times, but directly obtains the corresponding data from the cache area for error correction, thereby saving a lot of time.

Another embodiment of the present application further provides a data acquisition system 500. As shown in FIG5 , the data acquisition system 500 includes:

The acquisition unit 510 is used to acquire an error correction voltage set of the hard disk, where the error correction voltage set includes a plurality of offset voltage values.

The verification unit 520 is used to verify the error correction voltage set based on the multiple original to-be-verified data read under the multiple offset voltage values.

The read storage unit 530 is used to read the original data of the target page in the hard disk flash memory based on the error correction voltage set when the error correction voltage set is verified, wherein the original data to be verified is part of the original data; and store the read multiple original offset data in different cache areas, wherein the original offset data read under each offset voltage value is placed in the same cache area.

The error correction unit 540 is used to sequentially obtain the corresponding original offset sub-data from the different buffer areas for error correction to obtain a plurality of target data.

Another embodiment of the present application further proposes a hard disk, including a storage unit and a processing unit, wherein a computer program is stored in the storage unit, and the processing unit executes the steps of the above-mentioned data acquisition method by calling the computer program stored in the storage unit.

Another embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. The computer program is suitable for being loaded by a processor to execute the steps of the above-mentioned data acquisition method.

It can be understood that the method steps of this embodiment correspond to the data acquisition method in the above embodiment, wherein the options of the above data acquisition method are also applicable to this embodiment and will not be described repeatedly here.

In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a part of the module, program segment or code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and/or the flow diagram, and the combination of boxes in the structure diagram and/or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

The above description is only a specific implementation mode of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims (10)

1. A data acquisition method, comprising: Acquire an error correction voltage set of a hard disk, wherein the error correction voltage set includes a plurality of offset voltage values; Verifying the error correction voltage set based on a plurality of original to-be-verified data read at the plurality of offset voltage values; When the error correction voltage set is verified, the original data of the target page in the hard disk flash memory is read based on the error correction voltage set, wherein the original data to be verified is part of the original data; and the read multiple original offset data are stored in different cache areas, wherein the original offset data read under each offset voltage value is placed in the same cache area; The corresponding original offset sub-data are sequentially obtained from the different buffer areas for error correction to obtain a plurality of target data. 2. The data acquisition method according to claim 1, characterized in that the error correction voltage set includes a main bias voltage value, a left bias voltage value and a right bias voltage value, and the original offset data includes original main bias data, original left bias data and original right bias data; the reading of the original data of the target page in the hard disk flash memory based on the error correction voltage set comprises: The original data of the target page is read based on the main bias voltage value, the left bias voltage value and the right bias voltage value respectively, and the original main bias data, the original left bias data and the original right bias data are obtained accordingly. 3. The data acquisition method according to claim 1 is characterized in that each of the original offset data is divided into a plurality of original offset sub-data of the same size, each of the original offset sub-data corresponds to a sub-portion of the original data, and all the original offset sub-data corresponding to the same sub-portion correspond to each other; the original offset sub-data include original main offset sub-data, original left offset sub-data and original right offset sub-data; the corresponding original offset sub-data are sequentially acquired from the different buffer areas for error correction to acquire a plurality of target data, including: Sequentially acquiring mutually corresponding original offset sub-data from the different buffer areas for error correction; When the bit error rate of the original main bias sub-data does not fall within the first preset range, the original main bias sub-data is used as the target data; When the bit error rate of the original main bias sub-data belongs to the first preset range, and the bit error rate of the original left bias sub-data does not belong to the first preset range, the original left bias sub-data is used as the target data; When the bit error rates of the original main bias sub-data and the original left bias sub-data both belong to the first preset range, and the bit error rate of the original right bias sub-data does not belong to the first preset range, the original right bias sub-data is used as the target data; When the bit error rates of the original main bias sub-data, the original left bias sub-data, and the original right bias sub-data all belong to the first preset range, it is confirmed that the error correction has failed. 4. The data acquisition method according to claim 1, further comprising: The data volume of the original offset sub-data and the data volume of the original data to be verified are both less than or equal to the maximum data volume that can be corrected at one time. 5. The data acquisition method according to claim 2, characterized in that the verifying the error correction voltage set based on the multiple original to-be-verified data read under the multiple offset voltage values comprises: The original data to be verified are read using the main bias voltage value, the left bias voltage value and the right bias voltage value respectively, and main bias verification data, left bias verification data and right bias verification data are obtained correspondingly; The error correction voltage set is verified based on the main bias verification data, the left bias verification data and the right bias verification data. 6. The data acquisition method according to claim 5, characterized in that the verifying the error correction voltage set based on the main bias verification data, the left bias verification data and the right bias verification data comprises: When the bit error rate of the main bias verification data, the left bias verification data or the right bias verification data does not fall within a second preset range, it is confirmed that the error correction voltage set verification has passed; When the bit error rates of the main bias verification data, the left bias verification data, and the right bias verification data all belong to the second preset range, it is confirmed that the error correction voltage set verification has failed. 7. The data acquisition method according to claim 1, further comprising: When the original offset sub-data is corrected, the original data of the next target page in the hard disk flash memory is also read based on the error correction voltage set to obtain the target data corresponding to the next target page until the target data of all target pages are obtained. 8. The data acquisition method according to any one of claims 1 to 7, further comprising: When the error correction fails or the error correction voltage set verification fails, the process returns to the step of obtaining the error correction voltage set of the hard disk, and uses the obtained new voltage value as the error correction voltage set. 9. A hard disk, characterized in that it comprises a storage unit and a processing unit, wherein the storage unit stores a computer program, and the processing unit executes the steps of the data acquisition method according to any one of claims 1 to 8 by calling the computer program stored in the storage unit. 10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor to execute the steps of the data acquisition method according to any one of claims 1 to 8.