CN118448426A

CN118448426A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN118448426A
Application number: CN202410575593.8A
Authority: CN
Inventors: 吴尚霖; 范扬顺
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2023-11-30
Filing date: 2024-05-10
Publication date: 2024-08-06

Abstract

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a first gate electrode, a first semiconductor layer, a first gate dielectric layer, a second gate electrode, a second gate dielectric layer, a second semiconductor layer, a third gate dielectric layer, a first contact hole, a second contact hole, a source electrode, a drain electrode, and a third gate electrode. The first semiconductor layer is located on the first gate. The first gate dielectric layer is located between the first gate electrode and the first semiconductor layer. The second gate is located on the first semiconductor layer. The second gate dielectric layer is located between the first semiconductor layer and the second gate. The second semiconductor layer is located on the second gate. The third gate dielectric layer is located between the second gate electrode and the second semiconductor layer. The first contact hole and the second contact hole respectively penetrate through the second gate dielectric layer and the third gate dielectric layer continuously. The source electrode and the drain electrode are respectively filled in the first contact hole and the second contact hole and are electrically connected with the first semiconductor layer and the second semiconductor layer. The third gate is located over the second semiconductor layer.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a device, and more particularly, to a semiconductor device.

Background

The dual-channel thin film transistor overcomes the defects of the traditional single-grid thin film transistor and the traditional double-grid thin film transistor that the driving voltage is larger and the reliability is lower, so that the dual-channel thin film transistor is suitable for being used as a driving element of an organic light emitting diode display device or a micro light emitting diode display device. However, in order to connect two channels of the dual channel thin film transistor to the same source and drain, the source and drain need to be implemented by forming deep vias through at least four insulating layers or forming two electrically connected vias connected to the two channels, respectively. The design rule and etching conditions are limited, so that the aperture of the deep via hole is difficult to be reduced, and the distance between two electrically connected via holes is difficult to be reduced, which results in large occupied area of the whole dual-channel thin film transistor and is unfavorable for circuit design with high panel trend resolution, light weight, thinness and shortness. In addition, the channel may be damaged during the formation of the via hole, which affects the performance of the dual channel thin film transistor.

Disclosure of Invention

The invention provides a semiconductor device with reduced area and good performance.

The semiconductor device of the invention comprises a substrate, a first grid electrode, a first semiconductor layer, a first grid dielectric layer, a second grid electrode, a second grid dielectric layer, a second semiconductor layer, a third grid dielectric layer, a first contact hole, a second contact hole, a source electrode, a drain electrode, a third grid electrode and a fourth grid dielectric layer. The first grid electrode is arranged above the substrate. The first semiconductor layer is located on the first grid electrode. The first gate dielectric layer is located between the first gate electrode and the first semiconductor layer. The second gate is located above the first semiconductor layer. The second gate dielectric layer is located between the first semiconductor layer and the second gate. The second semiconductor layer is positioned on the second grid electrode. The third gate dielectric layer is located between the second gate electrode and the second semiconductor layer. The first contact hole continuously penetrates through the second gate dielectric layer and the third gate dielectric layer. The second contact hole continuously penetrates through the second gate dielectric layer and the third gate dielectric layer. The source electrode is filled in the first contact hole and is electrically connected with the first semiconductor layer and the second semiconductor layer. The drain electrode is filled in the second contact hole and is electrically connected with the first semiconductor layer and the second semiconductor layer. The third gate is located over the second semiconductor layer. The fourth gate dielectric layer is located between the second semiconductor layer and the third gate electrode.

The method for manufacturing a semiconductor device of the present invention includes the following steps. Forming a first grid on a substrate. A first gate dielectric layer is formed on the first gate. A first semiconductor layer is formed on the first gate dielectric layer. A second gate dielectric layer is formed on the first semiconductor layer. And forming a second grid electrode on the second grid dielectric layer. A third gate dielectric layer is formed on the second gate. And forming a first contact hole and a second contact hole in the second gate dielectric layer and the third gate dielectric layer and respectively exposing the surface of part of the first semiconductor layer. A source electrode is formed on the third gate dielectric layer and filled into the first contact hole. And forming a drain electrode on the third gate dielectric layer and filling the second contact hole. A second semiconductor layer is formed on the third gate dielectric layer. A fourth gate dielectric layer is formed on the top surface of the source electrode, the top surface of the drain electrode and the top surface of the second semiconductor layer. And forming a third grid electrode on the fourth grid dielectric layer.

Based on the above, the semiconductor device of the present invention electrically connects the source and the drain with the first semiconductor layer and the second semiconductor layer through the first contact hole and the second contact hole with small aperture, so that the orthographic projection area of the source and the drain on the substrate can be reduced, and the area of the semiconductor device can be further reduced, and meanwhile, the semiconductor device can disperse the current between the source and the drain through the first semiconductor layer and the second semiconductor layer, thereby improving the negative influence caused by the current stress or the hot carrier effect and increasing the driving voltage, so that the semiconductor device can be matched with the compact circuit design in the panel when being applied to the driving element of the panel, and the requirements of light, thin, short and small panel and high resolution can be achieved.

Drawings

Fig. 1A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view along line A-A' of fig. 1A.

Fig. 2A to 2G are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 1A to 1B.

Fig. 3A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 3B is a schematic cross-sectional view along line B-B' of fig. 3A.

Fig. 4A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 4B is a schematic cross-sectional view along line C-C' of fig. 4A.

Fig. 5A to 5B are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 4A to 4B.

Fig. 6A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 6B is a schematic cross-sectional view along line D-D' of fig. 6A.

Fig. 7A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 7B is a schematic cross-sectional view along line E-E' of fig. 7A.

Fig. 8A to 8B are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 7A to 7B.

Reference numerals illustrate:

10,20,30,40,50: semiconductor device with a semiconductor device having a plurality of semiconductor chips

100: Substrate board

112: First gate dielectric layer

114: Second gate dielectric layer

116: Third gate dielectric layer

116T,140t,152t,154t: top surface

118: Fourth gate dielectric layer

120: First grid electrode

122: Second grid electrode

124: Third grid electrode

130: First semiconductor layer

130A,130b: doped region

130C: channel region

132: First layer

134: Second layer

140: Second semiconductor layer

152: Source electrode

154: Drain electrode

160: Protective layer

170: Third semiconductor layer

A-a ', B-B ', C-C ', D-D ', E-E ': wire (C)

CH1: first contact hole

CH2: second contact hole

ND: normal direction

P: doping process

Sw1, sw11, sw12, sw2, sw21, sw22: side wall

Detailed Description

In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connection. Furthermore, "electrically connected" or "coupled" may mean that there are other elements between the elements.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer, or section without departing from the teachings herein.

Fig. 1A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 1B is a schematic cross-sectional view along line A-A' of fig. 1A. In fig. 1A, the first gate electrode 120, the second gate electrode 122, the third gate electrode 124, the first semiconductor layer 130, the second semiconductor layer 140, the source electrode 152, the drain electrode 154, the first contact hole CH1, and the second contact hole CH2 are illustrated, and other components are omitted, and the omitted parts may be understood with reference to fig. 1B.

Referring to fig. 1A and 1B, the semiconductor device 10 includes a substrate 100, a first gate 120, a second gate 122, a third gate 124, a first semiconductor layer 130, a second semiconductor layer 140, a first gate dielectric layer 112, a second gate dielectric layer 114, a third gate dielectric layer 116, a fourth gate dielectric layer 118, a source 152, a drain 154, a first contact hole CH1 and a second contact hole CH2.

The first gate 120 is disposed over the substrate 100. The first semiconductor layer 130 is disposed on the first gate electrode 120, and the first gate dielectric layer 112 is disposed between the first gate electrode 120 and the first semiconductor layer 130. The second gate electrode 122 is located above the first semiconductor layer 130, and the second gate dielectric layer 114 is located between the first semiconductor layer 130 and the second gate electrode 122. The second semiconductor layer 140 is disposed on the second gate 122, and the third gate dielectric layer 116 is disposed between the second gate 122 and the second semiconductor layer 140. The third gate 124 is located above the second semiconductor layer 140, and the fourth gate dielectric layer 118 is located between the second semiconductor layer 140 and the third gate 124. In some embodiments, the semiconductor device 10 further includes a protective layer 160, where the protective layer 160 covers the third gate 124.

In some embodiments, the material of the substrate 100 includes glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material), or other suitable material. If a conductive material or metal is used, an insulating layer (not shown) is coated on the substrate 100 to avoid the short circuit problem. In some embodiments, one or more buffer layers (not shown) are further included between the first gate 120 and the substrate 100, but the invention is not limited thereto.

In some embodiments, the materials of the first gate electrode 120, the second gate electrode 122, and the third gate electrode 124 may include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, and other metals, alloys thereof, metal oxides thereof, metal nitrides thereof, combinations thereof, or other conductive materials. For example, the first gate 120, the second gate 122, and the third gate 124 may each be a stacked layer of titanium metal, aluminum metal, and titanium metal. The materials of the first gate 120, the second gate 122, and the third gate 124 may be the same or different, which is not limited by the present invention.

In some embodiments, the materials of the first gate dielectric layer 112, the second gate dielectric layer 114, the third gate dielectric layer 116, the fourth gate dielectric layer 118, and the protective layer 160 include silicon nitride, silicon oxynitride, silicon oxide, hafnium oxide, combinations thereof, or other suitable materials. In some embodiments, the materials of the first gate dielectric layer 112, the second gate dielectric layer 114, the third gate dielectric layer 116, the fourth gate dielectric layer 118 and the passivation layer 160 may be the same or different, which is not limited to the present invention. In some embodiments, the first gate dielectric layer 112, the second gate dielectric layer 114, the third gate dielectric layer 116, the fourth gate dielectric layer 118 and the protection layer 160 may have a single-layer or multi-layer structure, respectively, and the invention is not limited thereto.

In some embodiments, the material of the first semiconductor layer 130 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, an organic semiconductor material, a metal Oxide semiconductor material (e.g., indium-Gallium-Zinc Oxide (IGZO), indium-Tin-Zinc Oxide (ITZO), aluminum-Zinc-Tin-Oxide (AZTO), indium-Tungsten-Zinc Oxide (ZIWO), zinc Oxide (ZnO), tin Oxide (SnO), indium-Zinc Oxide (IZO), gallium-Zinc Oxide (GZO), zinc-Tin Oxide (ZTO), or Indium-Tin Oxide (Indium-Tin Oxide, ITO), or other suitable materials or other suitable combinations thereof.

In this embodiment, the first semiconductor layer 130 has a double-layer structure. For example, the first semiconductor layer 130 may include a first layer 132 and a second layer 134 stacked on each other. A first layer 132 is located on the first gate dielectric layer 112 and a second layer 134 is located on the first layer 132. That is, the first layer 132 is between the second layer 134 and the first gate dielectric layer 112. The band gap of the first layer 132 is different from the band gap of the second layer 134, so that a two-dimensional electron gas (2 DEG) can be formed at the interface between the first layer 132 and the second layer 134 to enhance the electron mobility of the first semiconductor layer 130. However, the present invention is not limited thereto, and in other embodiments, the first semiconductor layer 130 may have a single-layer structure, or the first semiconductor layer 130 may have a multi-layer structure.

The energy gap difference between the first layer 132 and the second layer 134 can be achieved by making the materials or compositions of the first layer 132 and the second layer 134 different. In some embodiments, the materials of the first layer 132 and the second layer 134 may include a metal oxide semiconductor material, and the oxygen content of the first layer 132 is different from the oxygen content of the second layer 134, so that the energy gap of the first layer 132 is different from the energy gap of the second layer 134. In some embodiments, the oxygen content of the first layer 132 is less than the oxygen content of the second layer 134. For example, the oxygen content of the first layer 132 may be between 0 atomic% and 25 atomic%, and the oxygen content of the second layer 134 may be between 25 atomic% and 50 atomic%. In this way, the energy gap (band gap) of the first layer 132 is smaller than that of the second layer 134, so as to form a two-dimensional electron gas at the interface between the first layer 132 and the second layer 134, thereby improving the electron mobility and the output current of the semiconductor device 10. However, the present invention is not limited thereto, and in other embodiments, the oxygen content of the first layer 132 may be greater than that of the second layer 134. In addition, the oxygen content of the first layer 132 and the oxygen content of the second layer 134 can be adjusted according to practical requirements, which is not limited in the present invention.

In some embodiments, the material of the second semiconductor layer 140 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, metal oxide semiconductor materials (e.g., indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, aluminum zinc oxide, or indium tin oxide, or other suitable materials), or other suitable materials, or combinations thereof. In some embodiments, the material of the second semiconductor layer 140 may be the same as or different from the material of the first semiconductor layer 130. Although the second semiconductor layer 140 is shown in fig. 1B as a single-layer structure, the present invention is not limited thereto, and the second semiconductor layer 140 may be a double-layer or multi-layer structure according to practical requirements.

In some embodiments, the orthographic projection area of the second semiconductor layer 140 on the substrate 100 is smaller than the orthographic projection area of the first semiconductor layer 130 on the substrate 100.

The first contact hole CH1 continuously penetrates the second gate dielectric layer 114 and the third gate dielectric layer 116. The second contact hole CH2 continuously penetrates the second gate dielectric layer 114 and the third gate dielectric layer 116. The source electrode 152 is filled in the first contact hole CH1 and electrically connected to the first semiconductor layer 130 and the second semiconductor layer 140. The drain electrode 154 is filled in the second contact hole CH2 and electrically connected to the first semiconductor layer 130 and the second semiconductor layer 140. The fourth gate dielectric 118 covers the top surface 152t of the source electrode 152 and the top surface 154t of the drain electrode 154. Herein, "continuously penetrating" means that the contact hole is formed through one or more gate dielectric layers in one etching process, that is, the first contact hole CH1 is formed through the second gate dielectric layer 114 and the third gate dielectric layer 116 in one etching process, and the second contact hole CH2 is formed through the second gate dielectric layer 114 and the third gate dielectric layer 116 in one etching process. Therefore, in the first contact hole CH1, the sidewall sw1 of the first contact hole CH1 is formed by the sidewall sw11 of the second gate dielectric layer 114 and the sidewall sw12 of the third gate dielectric layer 116, wherein the sidewall sw11 of the second gate dielectric layer 114 is substantially aligned with the sidewall sw12 of the third gate dielectric layer 116; in the second contact hole CH2, the sidewall sw2 of the second contact hole CH2 is formed by the sidewall sw21 of the second gate dielectric layer 114 and the sidewall sw22 of the third gate dielectric layer 116, wherein the sidewall sw21 of the second gate dielectric layer 114 is substantially aligned with the sidewall sw22 of the third gate dielectric layer 116.

In some embodiments, the fourth gate dielectric layer 118 covers the first contact hole CH1 and the second contact hole CH2 in the normal direction ND of the substrate 100. That is, the source 152 and the drain 154 are buried in the second gate dielectric 114, the third gate dielectric 116 and the fourth gate dielectric 118.

Since the first contact hole CH1 and the second contact hole CH2 penetrate the second gate dielectric layer 114 and the third gate dielectric layer 116 without penetrating the fourth gate dielectric layer 118 and the passivation layer 160, the first contact hole CH1 and the second contact hole CH2 can have smaller apertures, so as to reduce the orthographic projection area of the source electrode 152 and the drain electrode 154 on the substrate 100. In some embodiments, the apertures of the first contact hole CH1 and the second contact hole CH2 may be between about 2 μm and 5 μm.

In some embodiments, the orthographic projections of the first contact hole CH1 and the second contact hole CH2 on the substrate 100 are respectively located on opposite sides of the orthographic projection of the first gate 120, the second gate 122, or the third gate 124 on the substrate 100.

In some embodiments, the first semiconductor layer 130 has doped regions 130a, 130b and a channel region 130c. The channel region 130c is located between the doped region 130a and the doped region 130b. The resistivity of the doped region 130a and the doped region 130b is less than the resistivity of the channel region 130c. In some embodiments, the channel region 130c substantially overlaps the second gate 122 in the normal direction ND of the substrate 100, and the doped region 130a and the doped region 130b substantially do not overlap the second gate 122 in the normal direction ND of the substrate 100. In some embodiments, the first contact hole CH1 and the second contact hole CH2 overlap the doped region 130a and the doped region 130b, respectively, in the normal direction ND of the substrate 100.

In the present embodiment, the second semiconductor layer 140 extends into the first contact hole CH1 and the second contact hole CH2 to be in direct contact with the first semiconductor layer 130. Specifically, the second semiconductor layer 140 extends along the top surface 116t of the third gate dielectric layer 116 to the sidewall sw1 of the first contact hole CH1 and the sidewall sw2 of the second contact hole CH2 and contacts the doped regions 130a and 130b of the first semiconductor layer 130, so as to be connected to the first semiconductor layer 130. In this way, the first semiconductor layer 130 may be compensated for the loss caused by forming the first contact hole CH1 and the second contact hole CH2, thereby improving the contact resistance.

In some embodiments, the first contact hole CH1 and the second contact hole CH2 overlap the first semiconductor layer 130 and the second semiconductor layer 140 in the normal direction ND of the substrate 100.

In some embodiments, the source 152 and the drain 154 are respectively located on opposite sides of the second semiconductor layer 140. The source electrode 152 directly contacts the top surface 140t of the second semiconductor layer 140, and the drain electrode 154 directly contacts the top surface 140t of the second semiconductor layer 140. That is, a portion of the second semiconductor layer 140 is sandwiched between the first semiconductor layer 130 and the source electrode 152 and between the first semiconductor layer 140 and the drain electrode 154.

In some embodiments, ohmic contact layers (not shown) may be disposed between the source electrode 152 and the second semiconductor layer 140 and between the drain electrode 154 and the second semiconductor layer 140 to promote electrical connection between the source electrode 152, the drain electrode 154 and the second semiconductor layer 140. For example, the ohmic contact layer may include a doped silicon-containing (silicon-containing) semiconductor material or a metal oxide semiconductor material such that the resistivity of the ohmic contact layer is less than the resistivity of the second semiconductor layer 140.

In some embodiments, the first gate electrode 120, the second gate electrode 122, and the third gate electrode 124 overlap each other in the normal direction ND of the substrate 100. The first gate 120, the second gate 122, and the third gate 124 may be electrically connected or electrically separated according to the actual circuit design, which is not limited in the present invention. For example, in some embodiments, the second gate 122 may serve as a main control gate, while the first gate 120 and the third gate 124 are floating (floating). In some other embodiments, the first gate 120, the second gate 122, and the third gate 124 may be electrically connected to each other through vias (not shown).

Since the first contact hole CH1 and the second contact hole CH2 have small apertures, and the source electrode 152 and the drain electrode 154 are electrically connected to the first semiconductor layer 130 and the second semiconductor layer 140 through the first contact hole CH1 and the second contact hole CH2, the forward projection area of the source electrode 152 and the drain electrode 154 on the substrate 100 can be reduced, so that the area of the semiconductor device 10 is reduced, and meanwhile, the semiconductor device 10 can disperse the current between the source electrode 152 and the drain electrode 154 through the first semiconductor layer 130 and the second semiconductor layer 140, thereby improving the adverse effects caused by the current stress or the hot carrier effect and increasing the driving voltage, so that the semiconductor device 10 still has good performance under the condition of reduced area.

Fig. 2A to 2G are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 1A to 1B. It should be noted that the embodiments of fig. 2A to 2G use the element numbers and part of the contents of the embodiments of fig. 1A to 1B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.

Referring to fig. 2A, a first gate 120 is formed on a substrate 100. For example, a first gate material layer (not shown) may be deposited on the substrate 100 and then patterned to form the first gate 120. In some embodiments, the first gate material layer may be formed by electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the invention is not limited thereto. In some embodiments, the method for patterning the first gate material layer may include photolithography and etching, but the invention is not limited thereto.

Referring to fig. 2B, a first gate dielectric layer 112 is formed on the first gate electrode 120. In some embodiments, the first gate dielectric layer 112 is conformally deposited over the first gate 120 and the substrate 100. In some embodiments, the first gate dielectric layer 112 may be formed by physical vapor deposition or chemical vapor deposition, but the invention is not limited thereto.

Then, a first semiconductor layer 130 is formed on the first gate dielectric layer 122. For example, a material of a first layer of the first semiconductor material layer and a material of a second layer of the first semiconductor material layer may be sequentially deposited on the first gate dielectric layer 122 by, for example, a physical vapor deposition method or a chemical vapor deposition method. The first semiconductor material layer is then patterned by photolithography and etching to form the first semiconductor layer 130 including the first layer 132 and the second layer 134. In embodiments where the first semiconductor layer 130 is a metal oxide semiconductor, the oxygen content of the first layer 132 is different from the oxygen content of the second layer 134. Although fig. 2C shows the first semiconductor layer 130 having a dual-layer structure, the number of layers of the first semiconductor layer 130 can be adjusted according to practical requirements.

Referring to fig. 2C, a second gate dielectric layer 114 is formed on the first semiconductor layer 130. The second gate dielectric layer 114 can be formed by, for example, physical vapor deposition or chemical vapor deposition, but the invention is not limited thereto.

Then, a second gate 122 is formed on the second gate dielectric layer 114. For example, a second gate material layer (not shown) may be deposited on the second gate dielectric layer 114, and then patterned to form the second gate 122. In some embodiments, the second gate material layer may be formed by electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the invention is not limited thereto. In some embodiments, the method for patterning the second gate material layer may include photolithography and etching, but the invention is not limited thereto.

Referring to fig. 2D, a doping process P is performed on the first semiconductor layer 130 with the second gate 122 as a mask to form a doped region 130a, a doped region 130b and a channel region 130c. The doped regions 130a and 130b are formed in the first semiconductor layer 130 at both sides of the second gate electrode 122, respectively. The channel region 130c is aligned with the second gate 122, which is substantially undoped. In some embodiments, the doping process P includes a hydrogen plasma process, an ion implantation process, or other suitable process.

Referring to fig. 2E, a third gate dielectric layer 116 is formed on the second gate 122 and the second gate dielectric layer 114. The third gate dielectric layer 116 may be formed by, for example, physical vapor deposition or chemical vapor deposition, but the invention is not limited thereto.

Then, a first contact hole CH1 and a second contact hole CH2 are formed in the second gate dielectric layer 114 and the third gate dielectric layer 116, and a portion of the surface of the first semiconductor layer 130 is exposed. In some embodiments, the first contact hole CH1 and the second contact hole CH2 expose the doped region 130a and the doped region 130b of the first semiconductor layer 130, respectively. In some embodiments, the forming method of the first contact hole CH1 and the second contact hole CH2 includes: a patterned photoresist layer (not shown) is formed on the third gate dielectric layer 116, and then an etching process is performed on the third gate dielectric layer 116 and the second gate dielectric layer 114 using the patterned photoresist layer as a mask to remove a portion of the second gate dielectric layer 114 and a portion of the third gate dielectric layer 116, wherein the first semiconductor layer 130 may be used as an etching stop layer of the etching process. In some embodiments, the etching process may be, for example, a wet etching process or a dry etching process, which is not limited to the present invention.

Since only the second gate dielectric layer 114 and the third gate dielectric layer 116 need to be removed to form the first contact hole CH1 and the second contact hole CH2 in the etching process, the first contact hole CH1 and the second contact hole CH2 may have a small aperture, for example, between about 2 μm and 5 μm, thereby reducing possible loss of the first semiconductor layer 130 in the etching process.

Referring to fig. 2F, a second semiconductor layer 140 is formed on the third gate dielectric layer 116, and the second semiconductor layer 140 is further formed on the sidewall sw1 of the first contact hole CH1, the sidewall sw2 of the second contact hole CH2, and the surface of the first semiconductor layer 130 exposed by the first contact hole CH1 and the second contact hole CH 2. For example, a second semiconductor material layer (not shown) may be deposited on the third gate dielectric layer 116 and in the first contact hole CH1 and the second contact hole CH2 by, for example, physical vapor deposition or chemical vapor deposition, and then patterned by photolithography and etching to form the second semiconductor layer 140. The second semiconductor layer 140 is formed on the first semiconductor layer 130 through the first contact hole CH1 and the second contact hole CH2 to directly contact the first semiconductor layer 130, so as to compensate for the loss of the first semiconductor layer 130 during the etching process for forming the first contact hole CH1 and the second contact hole CH2, thereby improving the contact resistance.

Referring to fig. 2G, a source electrode 152 is formed on the third gate dielectric layer 116 and fills the first contact hole CH1, and a drain electrode 154 is formed on the third gate dielectric layer 116 and fills the second contact hole CH 2. For example, a layer of conductive material (not shown) may be deposited over the second semiconductor layer 140 and the third gate dielectric layer 116, and then patterned to form the source 152 and drain 154. In some embodiments, the conductive material layer may be formed by electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the invention is not limited thereto. In some embodiments, the method for patterning the conductive material layer may include photolithography and etching, but the invention is not limited thereto.

In some embodiments, an ohmic contact layer (not shown) may be formed on the second semiconductor layer 140 before forming the source electrode 152 and the drain electrode 154. For example, an ohmic contact material layer may be deposited before depositing the aforementioned conductive material layer, followed by patterning the ohmic contact material layer to form an ohmic contact layer between the source electrode 152 and the second semiconductor layer 140 and between the drain electrode 154 and the second semiconductor layer 140.

Referring back to fig. 1B, a fourth gate dielectric layer 118 is formed on the top surface 152t of the source electrode 152, the top surface 154t of the drain electrode 154, and the top surface 140t of the second semiconductor layer 140. The fourth gate dielectric layer 118 can be formed by, for example, physical vapor deposition or chemical vapor deposition, but the invention is not limited thereto.

Then, a third gate 124 is formed on the fourth gate dielectric layer 118. For example, a third gate material layer (not shown) may be deposited on the fourth gate dielectric layer 118, and then patterned to form the third gate 124. In some embodiments, the forming method of the third gate material layer may be, for example, electroplating, electroless plating, physical vapor deposition or chemical vapor deposition, but the invention is not limited thereto. In some embodiments, the method for patterning the third gate material layer may include photolithography and etching, but the invention is not limited thereto.

Then, a passivation layer 160 is formed on the third gate electrode 124 and the fourth gate dielectric layer 118. The passivation layer 160 can be formed by, for example, physical vapor deposition or chemical vapor deposition, but the invention is not limited thereto.

Through the above process, the fabrication of the semiconductor device 10 can be substantially completed.

Fig. 3A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 3B is a schematic cross-sectional view along line B-B' of fig. 3A. It should be noted that the embodiments of fig. 3A to 3B use the element numbers and part of the contents of the embodiments of fig. 1A to 1B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here. In fig. 3A, the first gate electrode 120, the second gate electrode 122, the third gate electrode 124, the first semiconductor layer 130, the second semiconductor layer 140, the third semiconductor layer 170, the source electrode 152, the drain electrode 154, the first contact hole CH1, and the second contact hole CH2 are illustrated, and other components are omitted, and omitted parts may be understood with reference to fig. 3B.

Referring to fig. 3A and 3B, the semiconductor device 20 of the present embodiment is different from the embodiment of fig. 1A to 1B in that the semiconductor device 20 further includes a third semiconductor layer 170, the third semiconductor layer 170 is stacked on the second semiconductor layer 140, and the fourth gate dielectric layer 118 covers a portion of the top surface 152t of the source electrode 152, a portion of the top surface 154t of the drain electrode 154, and the third semiconductor layer 170.

In some embodiments, the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source electrode 152 and the top surface 154t of the drain electrode 154, and a portion of the source electrode 152 and a portion of the drain electrode 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. In this way, the possible loss of the second semiconductor layer 140 during the etching process of the source electrode 152 and the drain electrode 154 can be compensated, thereby improving the contact resistance.

In some embodiments, the material of the third semiconductor layer 170 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, metal oxide semiconductor materials (e.g., indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, aluminum zinc oxide, or indium tin oxide, or other suitable materials), or other suitable materials, or combinations of the above. In some embodiments, the material of the third semiconductor layer 170 may be the same as or different from the material of the first semiconductor layer 130 and/or the second semiconductor layer 140. Although the third semiconductor layer 170 is shown in fig. 3B as a single-layer structure, the present invention is not limited thereto, and the third semiconductor layer 170 may have a double-layer or multi-layer structure according to practical requirements.

In some embodiments, the energy gap of the third semiconductor layer 170 is different from the energy gap of the second semiconductor layer 140, so that a two-dimensional electron gas (2 DEG) may be formed at the interface between the third semiconductor layer 170 and the second semiconductor layer 140 to enhance electron mobility.

The energy gap difference between the third semiconductor layer 170 and the second semiconductor layer 140 can be achieved by making the material or composition of the third semiconductor layer 170 different from that of the second semiconductor layer 140. In some embodiments, the materials of the third semiconductor layer 170 and the second semiconductor layer 140 may include a metal oxide semiconductor material, and the oxygen content of the third semiconductor layer 170 is different from the oxygen content of the second semiconductor layer 140, so that the energy gap of the third semiconductor layer 170 is different from the energy gap of the second semiconductor layer 140. In some embodiments, the oxygen content of the third semiconductor layer 170 is less than the oxygen content of the second semiconductor layer 140. For example, the oxygen content of the third semiconductor layer 170 may be between 0 atomic% and 25 atomic%, and the oxygen content of the second semiconductor layer 140 may be between 25 atomic% and 50 atomic%. However, the present invention is not limited thereto, and in other embodiments, the oxygen content of the third semiconductor layer 170 may be greater than that of the second semiconductor layer 140. In addition, the oxygen content of the third semiconductor layer 170 and the oxygen content of the second semiconductor layer 140 can be adjusted according to practical requirements, which is not limited in the present invention.

In some embodiments, the orthographic projection area of the third semiconductor layer 170 on the substrate 100 is smaller than the orthographic projection area of the second semiconductor layer 140 on the substrate 100.

The method of fabricating the semiconductor device 20 is similar to the method of fabricating the semiconductor device 10, and after the formation of the source electrode 152 and the drain electrode 154 and before the formation of the fourth gate dielectric layer 118, a third semiconductor layer 170 is formed on the second semiconductor layer 140, wherein the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source electrode 152 and the top surface 154t of the drain electrode 154, and a portion of the source electrode 152 and a portion of the drain electrode 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. The third semiconductor layer 170 may be formed by first depositing a third semiconductor material layer (not shown) on the second semiconductor layer 140 and the source and drain electrodes 152 and 154 by, for example, physical vapor deposition or chemical vapor deposition, and then patterning the third semiconductor material layer by photolithography and etching to form the third semiconductor layer 170.

In some embodiments, the method of manufacturing the semiconductor device 20 may further include performing a doping process (e.g., a hydrogen plasma process, an ion implantation process, or other suitable process) on the third semiconductor layer 170 after the third gate 124 is formed, using the third gate 124 as a mask, to form a doped region (not shown) in the third semiconductor layer 170 not covered by the third gate 124, and the third semiconductor layer 170 aligned with the third gate 124 is a channel region (not shown).

Since the third semiconductor layer 170 is formed on the second semiconductor layer 140 after the source and drain electrodes 152 and 154 are formed, possible loss of the second semiconductor layer 140 during etching to form the source and drain electrodes 152 and 154 can be compensated for, thereby improving contact resistance.

Fig. 4A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 4B is a schematic cross-sectional view along line C-C' of fig. 4A. It should be noted that the embodiments of fig. 4A to 4B use the element numbers and part of the contents of the embodiments of fig. 1A to 1B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here. In fig. 4A, the first gate electrode 120, the second gate electrode 122, the third gate electrode 124, the first semiconductor layer 130, the second semiconductor layer 140, the source electrode 152, the drain electrode 154, the first contact hole CH1, and the second contact hole CH2 are illustrated, and other components are omitted, and omitted parts may be understood with reference to fig. 4B.

Referring to fig. 4A and 4B, the semiconductor device 30 of the present embodiment is different from the embodiment of fig. 1A to 1B in that the source electrode 152 of the semiconductor device 30 is directly contacted with the first semiconductor layer 130 through the first contact hole CH1, and the drain electrode 154 is directly contacted with the first semiconductor layer 130 through the second contact hole CH 2. That is, the second semiconductor layer 140 of the semiconductor device 30 does not extend into the first and second contact holes CH1 and CH2 and directly contacts the first semiconductor layer 130. Opposite sides of the second semiconductor layer 140 are respectively located between the source electrode 152 and the third gate dielectric layer 116 and between the drain electrode 154 and the third gate dielectric layer 116.

In some embodiments, the source 152 is in direct contact with the doped region 130a of the first semiconductor layer 130, and the drain 154 is in direct contact with the doped region 130b of the first semiconductor layer 130. In some embodiments, the source 152 and drain 154 directly contact the top surface 140t of the second semiconductor layer 140.

In some embodiments, the first contact hole CH1 and the second contact hole CH2 overlap the first semiconductor layer 130 in the normal direction ND of the substrate 100, but do not overlap the second semiconductor layer 140.

Since the first contact hole CH1 and the second contact hole CH2 have small apertures, and the source electrode 152 and the drain electrode 154 electrically connect the first semiconductor layer 130 and the second semiconductor layer 140 through the first contact hole CH1 and the second contact hole CH2, the forward projection area of the source electrode 152 and the drain electrode 154 on the substrate 100 can be reduced, so that the area of the semiconductor device 30 is reduced, and meanwhile, the semiconductor device 30 can disperse the current between the source electrode 152 and the drain electrode 154 through the first semiconductor layer 130 and the second semiconductor layer 140, thereby improving the adverse effects caused by the current stress or the hot carrier effect and increasing the driving voltage, so that the semiconductor device 30 still has good performance under the condition of reduced area.

Fig. 5A to 5B are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 4A to 4B. It should be noted that the embodiments of fig. 5A to 5B use the element numbers and part of the contents of the embodiments of fig. 4A to 4B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here. Fig. 5A may be a continuation of the process of fig. 2A-2E, and reference may be made to the foregoing for a description of the relevant process.

Referring to fig. 5A, the process of fig. 2E is continued, and a second semiconductor layer 140 is formed on the third gate dielectric layer 116. For example, a second semiconductor material layer (not shown) may be deposited on the third gate dielectric layer 116 by, for example, physical vapor deposition or chemical vapor deposition, and then patterned by photolithography and etching to form the second semiconductor layer 140. Alternatively, a patterned photoresist layer (not shown) may be formed to cover the first contact hole CH1 and the second contact hole CH2 and expose a location where the second semiconductor layer 140 is to be formed, and then a second semiconductor material layer (not shown) is formed on the third gate dielectric layer 116, and then the patterned photoresist layer is stripped off to form the second semiconductor layer 140 on the third gate dielectric layer 116.

Referring to fig. 5B, a source electrode 152 is formed on the third gate dielectric layer 116 and the second semiconductor layer 140 and fills in the first contact hole CH1 to be in direct contact with the first semiconductor layer 130, and a drain electrode 154 is formed on the third gate dielectric layer 116 and the second semiconductor layer 140 and fills in the second contact hole CH2 to be in direct contact with the first semiconductor layer 130. For example, a layer of conductive material (not shown) may be deposited over the second semiconductor layer 140 and the third gate dielectric layer 116, and then patterned to form the source 152 and drain 154. In some embodiments, the conductive material layer may be formed by electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the invention is not limited thereto. In some embodiments, the method for patterning the conductive material layer may include photolithography and etching, but the invention is not limited thereto.

Referring back to fig. 4B, the steps of forming the fourth gate dielectric 118, the third gate 124, and the protective layer 160 similar to the semiconductor device 10 may then be continued, and the fabrication of the semiconductor device 20 may be substantially completed.

Fig. 6A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 6B is a schematic cross-sectional view along line D-D' of fig. 6A. It should be noted that the embodiments of fig. 6A to 6B use the element numbers and part of the contents of the embodiments of fig. 4A to 4B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here. In fig. 6A, the first gate electrode 120, the second gate electrode 122, the third gate electrode 124, the first semiconductor layer 130, the second semiconductor layer 140, the third semiconductor layer 170, the source electrode 152, the drain electrode 154, the first contact hole CH1, and the second contact hole CH2 are illustrated, and other components are omitted, and omitted parts may be understood with reference to fig. 6B.

Referring to fig. 6A and 6B, the semiconductor device 40 of the present embodiment is different from the embodiment of fig. 4A to 4B in that the semiconductor device 40 further includes a third semiconductor layer 170, the third semiconductor layer 170 is stacked on the second semiconductor layer 140, and the fourth gate dielectric layer 118 covers a portion of the top surface 152t of the source electrode 152, a portion of the top surface 154t of the drain electrode 154, and the third semiconductor layer 170.

In some embodiments, the material of the third semiconductor layer 170 may include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, metal oxide semiconductor materials (e.g., indium gallium zinc oxide, indium tin zinc oxide, aluminum zinc tin oxide, indium tungsten zinc oxide, tin oxide, indium zinc oxide, gallium zinc oxide, zinc tin oxide, aluminum zinc oxide, or indium tin oxide, or other suitable materials), or other suitable materials, or combinations of the above. In some embodiments, the material of the third semiconductor layer 170 may be the same as or different from the material of the first semiconductor layer 130 and/or the second semiconductor layer 140. Although the third semiconductor layer 170 is shown in fig. 6B as a single-layer structure, the present invention is not limited thereto, and the third semiconductor layer 170 may have a double-layer or multi-layer structure according to practical requirements.

The method of fabricating the semiconductor device 40 is similar to the method of fabricating the semiconductor device 30, and a third semiconductor layer 170 is formed on the second semiconductor layer 140 after the formation of the source electrode 152 and the drain electrode 154 and before the formation of the fourth gate dielectric layer 118, wherein the third semiconductor layer 170 extends from the top surface 140t of the second semiconductor layer 140 to the top surface 152t of the source electrode 152 and the top surface 154t of the drain electrode 154, and a portion of the source electrode 152 and a portion of the drain electrode 154 are located between the third semiconductor layer 170 and the second semiconductor layer 140. The third semiconductor layer 170 may be formed by first depositing a third semiconductor material layer (not shown) on the second semiconductor layer 140 and the source and drain electrodes 152 and 154 by, for example, physical vapor deposition or chemical vapor deposition, and then patterning the third semiconductor material layer by photolithography and etching to form the third semiconductor layer 170.

Fig. 7A is a top view of a semiconductor device according to an embodiment of the present invention. Fig. 7B is a schematic cross-sectional view along line E-E' of fig. 7A. It should be noted that the embodiments of fig. 7A to 7B use the element numbers and part of the contents of the embodiments of fig. 1A to 1B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here. In fig. 7A, the first gate electrode 120, the second gate electrode 122, the third gate electrode 124, the first semiconductor layer 130, the second semiconductor layer 140, the source electrode 152, the drain electrode 154, the first contact hole CH1, and the second contact hole CH2 are illustrated, and other components are omitted, and omitted parts may be understood with reference to fig. 7B.

Referring to fig. 7A and 7B, the semiconductor device 50 of the present embodiment is different from the embodiment of fig. 1A to 1B in that the source electrode 152 of the semiconductor device 50 is directly contacted with the first semiconductor layer 130 through the first contact hole CH1, the drain electrode 154 is directly contacted with the first semiconductor layer 130 through the second contact hole CH2, and the second semiconductor layer 140 extends from the top surface 116t of the third gate dielectric layer 116 to the top surface 152t of the source electrode 152 and the top surface 154t of the drain electrode 154, and a portion of the source electrode 152 and a portion of the drain electrode 154 are located between the third gate dielectric layer 116 and the second semiconductor layer 140. That is, the second semiconductor layer 140 of the semiconductor device 50 does not extend into the first contact hole CH1 and the second contact hole CH 2.

In some embodiments, opposite sides of the second semiconductor layer 140 are between the fourth gate dielectric layer 118 and the source electrode 152 and between the fourth gate dielectric layer 118 and the drain electrode 154, respectively.

Since the first contact hole CH1 and the second contact hole CH2 have small apertures, and the source electrode 152 and the drain electrode 154 electrically connect the first semiconductor layer 130 and the second semiconductor layer 140 through the first contact hole CH1 and the second contact hole CH2, the forward projection area of the source electrode 152 and the drain electrode 154 on the substrate 100 can be reduced, so that the area of the semiconductor device 50 is reduced, and meanwhile, the semiconductor device 50 can disperse the current between the source electrode 152 and the drain electrode 154 through the first semiconductor layer 130 and the second semiconductor layer 140, thereby improving the adverse effects caused by the current stress or the hot carrier effect and increasing the driving voltage, so that the semiconductor device 50 still has good performance under the condition of reduced area.

Fig. 8A to 8B are schematic cross-sectional views of a method of manufacturing the semiconductor device of fig. 7A to 7B. It should be noted that the embodiments of fig. 8A to 8B use the element numbers and part of the contents of the embodiments of fig. 7A to 7B, wherein the same or similar elements are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here. Fig. 7A may be a continuation of the process of fig. 2A-2E, and reference may be made to the foregoing for a description of the relevant process.

Referring to fig. 8A, continuing with the step of fig. 2E, a source electrode 152 is formed on the third gate dielectric layer 116 and filled into the first contact hole CH1 to be in direct contact with the first semiconductor layer 130, and a drain electrode 154 is formed on the third gate dielectric layer 116 and filled into the second contact hole CH2 to be in direct contact with the first semiconductor layer 130. For example, a layer of conductive material (not shown) may be deposited over the third gate dielectric layer 116, and then patterned to form the source 152 and drain 154 electrodes. In some embodiments, the conductive material layer may be formed by electroplating, electroless plating, physical vapor deposition, or chemical vapor deposition, but the invention is not limited thereto. In some embodiments, the method for patterning the conductive material layer may include photolithography and etching, but the invention is not limited thereto.

Referring to fig. 8B, a second semiconductor layer 140 is formed on the third gate dielectric layer 116, a portion of the source electrode 152 and a portion of the drain electrode 154. For example, a second semiconductor material layer (not shown) may be deposited on the third gate dielectric layer 116, the source electrode 152, and the drain electrode 154 by, for example, physical vapor deposition or chemical vapor deposition, and then patterned by photolithography and etching to form the second semiconductor layer 140.

Referring back to fig. 7B, the steps of forming the fourth gate dielectric layer 118, the third gate electrode 124, and the protection layer 160 may then continue similarly to the semiconductor device 10.

In some embodiments, the method of manufacturing the semiconductor device 50 may further include performing a doping process (e.g., a hydrogen plasma process, an ion implantation process, or other suitable process) on the second semiconductor layer 140 after the third gate 124 is formed using the third gate 124 as a mask to form a doped region (not shown) in the second semiconductor layer 140 not covered by the third gate 124, and the second semiconductor layer 140 aligned with the third gate 124 is a channel region (not shown).

Through the above process, the fabrication of the semiconductor device 50 can be substantially completed.

In summary, the semiconductor device of the present invention has the first contact hole and the second contact hole with small apertures to electrically connect the source and the drain with the first semiconductor layer and the second semiconductor layer, so that the orthographic projection area of the source and the drain on the substrate can be reduced, the area of the semiconductor device can be further reduced, and meanwhile, the semiconductor device can disperse the current between the source and the drain through the first semiconductor layer and the second semiconductor layer, thereby improving the adverse effects caused by the current stress or the hot carrier effect and increasing the driving voltage, so that the semiconductor device can be matched with the compact circuit design in the panel when being applied to the driving element of the panel, and the requirements of light, thin, short and small panel and high resolution can be achieved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims

1.A semiconductor device, comprising:

A substrate;

a first grid electrode positioned above the substrate;

A first semiconductor layer located on the first grid;

A first gate dielectric layer between the first gate and the first semiconductor layer;

A second gate electrode over the first semiconductor layer;

A second gate dielectric layer between the first semiconductor layer and the second gate;

A second semiconductor layer over the second gate;

A third gate dielectric layer between the second gate and the second semiconductor layer;

a first contact hole continuously penetrating the second gate dielectric layer and the third gate dielectric layer;

A second contact hole continuously penetrating the second gate dielectric layer and the third gate dielectric layer;

a source electrode filled in the first contact hole and electrically connected with the first semiconductor layer and the second semiconductor layer;

a drain electrode filled in the second contact hole and electrically connected with the first semiconductor layer and the second semiconductor layer;

A third gate electrode over the second semiconductor layer; and

And a fourth gate dielectric layer between the second semiconductor layer and the third gate.

2. The semiconductor device of claim 1, wherein said second semiconductor layer extends to said first semiconductor layer in direct contact with said first semiconductor layer.

3. The semiconductor device of claim 2, wherein said second semiconductor layer extends into said first contact hole and said second contact hole.

4. The semiconductor device of claim 2, wherein a portion of said second semiconductor layer is sandwiched between said first semiconductor layer and said source and between said first semiconductor layer and said drain.

5. The semiconductor device according to claim 1, further comprising:

A third semiconductor layer extending from a top surface of the second semiconductor layer to a top surface of the source electrode and a top surface of the drain electrode, and a portion of the source electrode and a portion of the drain electrode being located between the third semiconductor layer and the second semiconductor layer.

6. The semiconductor device according to claim 4, wherein an oxygen content of the third semiconductor layer is different from an oxygen content of the second semiconductor layer.

7. The semiconductor device of claim 1, wherein the second semiconductor layer extends from a top surface of the third gate dielectric layer onto a top surface of the source and a top surface of the drain, and a portion of the source and a portion of the drain are located between the second semiconductor layer and the third gate dielectric layer.

8. The semiconductor device of claim 1, wherein the source and drain contacts a top surface of the second semiconductor layer.

9. The semiconductor device of claim 1, wherein the fourth gate dielectric layer covers the first contact hole and the second contact hole in a normal direction of the substrate.

10. The semiconductor device of claim 1, wherein said fourth gate dielectric layer covers a top surface of said source and a top surface of said drain.

11. The semiconductor device of claim 1, wherein said source is in direct contact with said first semiconductor layer and said drain is in direct contact with said first semiconductor layer.

12. The semiconductor device of claim 1, wherein the first semiconductor layer comprises:

a first layer on the first gate dielectric layer; and

A second layer on the first layer,

Wherein the oxygen content of the first layer is different from the oxygen content of the second layer.

13. A method of manufacturing a semiconductor device, comprising:

Forming a first grid on a substrate;

Forming a first gate dielectric layer on the first gate;

forming a first semiconductor layer on the first gate dielectric layer;

forming a second gate dielectric layer on the first semiconductor layer;

Forming a second gate electrode on the second gate dielectric layer;

Forming a third gate dielectric layer on the second gate;

forming a first contact hole and a second contact hole in the second gate dielectric layer and the third gate dielectric layer and exposing part of the surface of the first semiconductor layer respectively;

forming a source electrode on the third gate dielectric layer and filling the first contact hole;

Forming a drain electrode on the third gate dielectric layer and filling the second contact hole;

forming a second semiconductor layer on the third gate dielectric layer;

Forming a fourth gate dielectric layer on a top surface of the source electrode, a top surface of the drain electrode and a top surface of the second semiconductor layer; and

Forming a third gate on the fourth gate dielectric layer.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the second semiconductor layer is further formed in the first contact hole and the second contact hole to be connected to the first semiconductor layer.

15. The method of claim 13, wherein said source is further formed on said second semiconductor layer and said drain is further formed on said second semiconductor layer such that a portion of said second semiconductor layer is sandwiched between said third gate dielectric layer and said source and between said third gate dielectric layer and said drain.

16. The method for manufacturing a semiconductor device according to claim 13, further comprising:

forming a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer extends from the top surface of the second semiconductor layer to the top surface of the source electrode and the top surface of the drain electrode.

17. The method for manufacturing a semiconductor device according to claim 16, wherein an oxygen content of the third semiconductor layer is different from an oxygen content of the second semiconductor layer.

18. The method of manufacturing a semiconductor device as claimed in claim 13, wherein the second semiconductor layer is further formed on the top surface of the source electrode and the top surface of the drain electrode such that a portion of the source electrode and a portion of the drain electrode are located between the second semiconductor layer and the third gate dielectric layer.

19. The method of manufacturing a semiconductor device according to claim 13, wherein the source electrode is in direct contact with the first semiconductor layer and the drain electrode is in direct contact with the first semiconductor layer.