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CN118447895A - Memory and method for accessing memory array - Google Patents

Memory and method for accessing memory array Download PDF

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Publication number
CN118447895A
CN118447895A CN202311376942.5A CN202311376942A CN118447895A CN 118447895 A CN118447895 A CN 118447895A CN 202311376942 A CN202311376942 A CN 202311376942A CN 118447895 A CN118447895 A CN 118447895A
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CN
China
Prior art keywords
memory
bit line
memory cells
metal layer
cells
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Pending
Application number
CN202311376942.5A
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Chinese (zh)
Inventor
洪志豪
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MediaTek Inc
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MediaTek Inc
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Filing date
Publication date
Priority claimed from US18/371,441 external-priority patent/US20240233786A9/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN118447895A publication Critical patent/CN118447895A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Memory and method of accessing a memory array. The memory includes a memory array and a single ended sense amplifier circuit. The memory array includes word lines, bit lines, and memory cells. The bit lines include a first bit line routed on the first metal layer but not the second metal layer, and a second bit line routed on the first metal layer and the second metal layer. Each of the memory cells is coupled to one of the word lines. The memory cells include a first set of memory cells coupled to a first bit line and a second set of memory cells coupled to a second bit line, wherein the first set of memory cells and the second set of memory cells are located at a same column. When the selected word line is enabled, the single-ended sense amplifier circuit performs a read operation on the target memory cell through single-ended sensing.

Description

Memory and method for accessing memory array
Cross reference to related applications
The present application claims the benefit of U.S. provisional application No.63/380,598, filed on day 24 at 10 at 2022, and the benefit of U.S. application No.18/371,441, filed on day 21 at 9 at 2023. The contents of the above application are incorporated herein by reference.
Technical Field
The present invention relates to memory design, and more particularly, to a memory having a fly-bit line (fly-bit line) that works with single-ended sensing and associated memory access methods.
Background
For various applications, the cache storage element may be used to temporarily hold data for further processing. Conventional methods for such cache memory elements are through the use of single-port static random access memory (static random access memory, SRAM) bit cells (e.g., six-transistor, 6T) single-port SRAM bit cells) or dual-port SRAM bit cells (e.g., 8T dual-port SRAM bit cells). In a single-port SRAM bit cell, generally, either of a read operation and a write operation is performed in one access through a complementary bit line pair consisting of two bit lines. When a read operation is performed on a single-port SRAM bit cell, both bit lines of the complementary bit line pair are precharged to a supply voltage, the word line is driven high after the precharge is turned off, one of the bit lines is pulled down according to the stored value, and the differential sense amplifier is activated to capture the stored value according to the differential voltage present at the complementary bit line pair. However, the differential sense amplifier requires complicated precharge timing control and transfer gate timing control. In addition, the differential sense amplifier has a high gate count, resulting in a large chip area and high power consumption.
Thus, there is a need for an innovative memory design that can have a small chip area, low power consumption, and/or simple timing control.
Disclosure of Invention
It is an object of the claimed invention to provide a memory having a flying bitline that works with single ended sensing and associated memory access methods.
According to a first aspect of the present invention, an exemplary memory is disclosed. An exemplary memory includes a memory array and a single ended sense amplifier circuit. The memory array includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Each of the plurality of word lines includes a first bit line and a second bit line, wherein the first bit line is routed on a first metal layer other than a second metal layer, and the second bit line is routed on the first metal layer and the second metal layer, wherein the second metal layer is different from the first metal layer. Each of the plurality of memory cells is coupled to one of the plurality of word lines. The plurality of memory cells includes a first group of memory cells coupled to a first bit line and a second group of memory cells coupled to a second bit line, wherein the first group of memory cells and the second group of memory cells are located at a same column. The single-ended sense amplifier circuit is arranged to perform a read operation on a target memory cell by single-ended sensing when the selected word line is enabled, wherein the target memory cell is selected from the first group of memory cells and the second group of memory cells.
In accordance with a second aspect of the present invention, an exemplary method of accessing a memory array is disclosed. The memory array includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the bit lines include a first bit line routed on a first metal layer other than a second metal layer and a second bit line routed on the first metal layer and the second metal layer, the second metal layer being different from the first metal layer, each of the plurality of memory cells is coupled to one of the plurality of word lines, the plurality of memory cells includes a first group of memory cells coupled to the first bit line and a second group of memory cells coupled to the second bit line, and the first group of memory cells and the second group of memory cells are located at a same column. The exemplary method includes: selecting a target memory cell from the first set of memory cells and the second set of memory cells; and performing a read operation on the target memory cell by single ended sensing in response to the selected word line being enabled.
These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
Drawings
Fig. 1 is a schematic diagram illustrating a memory design according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating a single ended sense amplifier circuit according to an embodiment of the invention.
Fig. 3 is a schematic diagram illustrating waveforms of a plurality of signals associated with a read operation performed by the single-ended sense amplifier circuit shown in fig. 2.
FIG. 4 is a schematic diagram illustrating a memory having a fly bitline operating with single ended sensing and without unbalanced FBL/non-FBL loading in accordance with an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating a memory having a fly bitline operating with single ended sensing and employing unbalanced FBL/non-FBL loading in accordance with an embodiment of the invention.
FIG. 6 is a schematic diagram illustrating another memory design according to an embodiment of the invention.
Detailed Description
Certain terms are used throughout the following description and claims to refer to particular components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to … …". Furthermore, the term "coupled" is intended to mean an indirect or direct electrical connection. Thus, if one device couples to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 1 is a schematic diagram illustrating a memory design according to an embodiment of the present invention. Memory 100 includes a memory array 102 and peripheral circuitry 104. The peripheral circuitry 104 acts as input/output (I/O) circuitry arranged to control access (read/write) of the memory array 102 and may include row decoder circuitry, timing controller circuitry, column decoder circuitry, sense amplifier circuitry, write driver circuitry, and the like. Since the present invention focuses on read operations, only sense amplifier circuitry is illustrated.
The memory array 102 includes a plurality of memory cells arranged in a two-dimensional (2D) array having a plurality of rows and a plurality of columns. As shown in fig. 1, each memory cell column may include N memory cells 106_0 to 106_i and 106_i+1 to 106_n-1. It should be noted that the memory array 102 may include a plurality of columns of memory cells. For a better understanding of the technical features of the present invention, only a single column of memory cells is illustrated in FIG. 1.
In this embodiment, each of the memory cells may have a single-port SRAM architecture for storing one bit, such as a 6T bit cell architecture. Those skilled in the art can readily understand the details of a typical 6T SRAM bit cell, further description is omitted herein for brevity. The memory array 102 includes a plurality of word lines WL_0 through WL_N-1, one complementary bit line pair consisting of bit lines BL and BLB, and another complementary bit line pair consisting of bit lines BL_fly and BLB_fly, where the word lines WL_0 through WL_N-1 correspond to different rows of memory cells, respectively, and the bit lines BL, BLB, BL _fly, BLB_fly correspond to the same column of memory cells.
In this embodiment, a fly-bit line (FBL) structure may be employed to improve memory access speed. For example, each of the bit lines BL and BLB is routed on a first metal layer (e.g., M0) instead of a second metal layer (e.g., M2), and each of the bit lines bl_fly and blb_fly is an FBL having a first segment routed on the first metal layer (e.g., M0) and a second segment routed on the second metal layer (e.g., M2), wherein the second segment routed on the second metal layer (e.g., M2) serves as an extension of the first segment routed on the first metal layer (e.g., M0) and spans the memory cells 106_i+1 through 106_n-1.
As shown in fig. 1, memory cells located in the same memory cell column are divided into a first group of memory cells 108 and a second group of memory cells 110, wherein the first group of memory cells 108 is coupled to bit lines BL and BLB, and the second group of memory cells 110 is coupled to bit lines bl_fly and blb_fly. The first set of memory cells 108 and the second set of memory cells 110 may be separated using edge regions and stripe regions. Since all memory cells belonging to the same memory cell column do not need to be coupled to the same single bit line having a longer length, each of the bit lines BL, BLB, BL _fly, blb_fly may have a shorter length, thereby improving memory access speed.
In this embodiment, the single-ended sense amplifier circuit 105 is arranged to perform a read operation on a target memory cell by single-ended sensing when a selected word line is enabled. For example, a target memory cell is selected from the first and second groups of memory cells 108, 110 located in the same memory cell column, and the selected word line is one of word lines WL_0 to WL_N-1. Thus, when the selected word line wl_j { j=0, 1, … …, N-1} is enabled, the single-ended sense amplifier circuit 105 is activated to capture the stored data bit of the target memory cell 106_j { j=0, 1, … …, N-1} by single-ended sensing. That is, the single-ended sense amplifier circuit 105 does not need to receive voltage levels at the two bit lines BL and BLB (or BL_fly and BLB_fly) of the same complementary bit line pair to capture the stored data bit of the target memory cell. In contrast, single-ended sense amplifier circuit 105 is able to capture a stored data bit of a target memory cell by referencing a voltage level at one of two bit lines connected to a complementary bit line pair of the target memory cell.
In this embodiment, the single-ended sense amplifier circuit 105 may include a logic gate circuit (e.g., a NAND gate) 112 and an output latch circuit 114. The logic gate 112 is arranged to receive two single ended input signals. For example, logic gate 112 may have a first input node coupled to one bit line BLB and a second input node coupled to another bit line BLB_fly, where bit lines BLB and BLB_fly may be connected to SRAM cells of the same column of the memory array. For another example, logic gate 112 may have a first input node coupled to one bit line BL and a second input node coupled to another bit line BL_fly, where bit lines BL and BL_fly may be connected to SRAM cells of the same column of the memory array. It should be noted that logic gate 112 may be implemented by a NAND gate or other logic gates, depending on practical design considerations. The output latch circuit 114 has an input node coupled to the output node of the logic gate circuit 112 and an output node arranged to output the read data DO of the target memory cell.
Please refer to fig. 2 in conjunction with fig. 3. Fig. 2 is a schematic diagram illustrating a single ended sense amplifier circuit according to an embodiment of the invention. Fig. 3 is a schematic diagram illustrating waveforms of a plurality of signals associated with a read operation performed by the single-ended sense amplifier circuit shown in fig. 2. The single-ended sense amplifier circuit 105 used by the memory 100 shown in fig. 1 may be implemented using the single-ended sense amplifier circuit 200 shown in fig. 2, where two single-ended input signals are obtained from the bit lines BL and bl_fly.
In this embodiment, single ended sense amplifier circuit 200 includes a NAND gate 202 and an output latch circuit 204. One input node of the NAND gate 202 (i.e., the gate terminal of one P-channel metal oxide semiconductor transistor) is coupled to the bit line BL, and the other input node of the NAND gate 202 (i.e., the gate terminal of another P-channel metal oxide semiconductor transistor) is coupled to the bit line BL_fly, where the bit lines BL and BL_fly may be connected to SRAM cells at the same column of the memory array. It is assumed that the selected memory cell is one of the memory cells 106_i+1 through 106_n-1 coupled to the complementary bit line pair consisting of bit lines BL and BLB, and stores a data bit "0". During a read period of one cycle of the memory clock CK, precharge is applied to the bit lines BL, BLB, BL _fly, blb_fly (i.e., bl=vdd, blb=vdd, bl_fly=vdd, and blb_fly=vdd) and then turned off, the selected word line WL of the selected memory cell is driven high by an enable pulse to allow the selected memory cell (which stores "0") to pull down the bit line BL connected to the selected memory cell, and the single-ended sense amplifier circuit 200 is activated by a complementary control signal pair consisting of the output latch signals OUTEN and OUTENb. When the bit line BL changes (develop) and becomes lower than the trip point (trip point) of the NAND gate 202, the NAND gate output signal DOC rises and then the sense signal DO falls. It should be noted that if the output latch signals OUTEN and OUTENb are activated earlier than the change of the bit line BL, the access time is determined by the activation of the selected word line WL and the voltage change speed of the bit line BL. It should be noted that since the single-ended sense amplifier circuit 105 (or 200) is implemented entirely within the global I/O circuitry of the memory 100, no additional buffers are required between the logic gate 112 (or nand gate 202) and the output latch circuit 114 (or 204).
Alternatively, the single-ended sense amplifier circuit 200 may be suitably modified to have two single-ended input signals obtained from the bit lines BLB and blb_fly. In short, the circuit design shown in FIG. 2 is for illustrative purposes only and is not meant to limit the present invention.
The single-ended sense amplifier circuit 105/200, which works with FBL, has a simple control design and lower gate count compared to typical differential sense amplifier circuits, which results in smaller chip area and lower power consumption. The single ended sense amplifier circuit 105/200 is shown with logic gates and output latch circuits. However, this is for illustrative purposes only and is not meant to limit the invention. In fact, the single-ended sense amplifier circuit 105 may employ any single-ended sensing scheme to work with the FBL used by the memory array 102. Such alternative designs fall within the scope of the invention.
Because of the fact that the bit line BL_fly/BLB_fly is further routed on the second metal layer (e.g., M2), the resistance of the bit line BL_fly/BLB_fly may be different from the resistance of the bit line BL/BLB, the access speed of the memory cells 106_0-106_N-1 is constrained by the access speed of the memory cells 106_0-106_i connected to the bit line BL_fly/BLB_fly. To solve this problem, the present invention further proposes to use unbalanced FBL/non-FBL loads to compensate for speed. For example, the number of cells of the first set of memory cells 108 (i.e., non-FBL load) may be different than the number of cells of the second set of memory cells 110 (i.e., FBL load). FIG. 4 is a schematic diagram illustrating a memory with a fly bit line operating with single ended sensing and without unbalanced FBL/non-FBL loading, where the number of cells of a first set of memory cells 402 (which are connected to bit lines BL and BLB and located at a column of memory cells) is equal to the number of cells of a second set of memory cells 404 (which are connected to bit lines BL_fly and BLB_fly and located at the same column of memory cells) according to an embodiment of the invention. FIG. 5 is a schematic diagram illustrating a memory with a fly bit line operating with single ended sensing and employing unbalanced FBL/non-FBL loading in accordance with an embodiment of the invention, where the number of cells of a first set of memory cells 502 (which are connected to bit lines BL and BLB and located at a column of memory cells) is greater than the number of cells of a second set of memory cells 504 (which are connected to bit lines BL_fly and BLB_fly and located at the same column of memory cells). In this way, the additional load caused by the FBL routed on the second metal layer (e.g., M2) may be balanced by the additional load (i.e., more memory cells) added to the non-FBL routed on the first metal layer (e.g., M0). By properly controlling the unbalanced FBL/non-FBL load, the access speed of the memory cells connected to the bit lines bl_fly/blb_fly may be substantially the same as the access speed of the memory cells connected to the bit lines BL/BLB.
In the above-described embodiments, each of the memory cells has a single-port SRAM architecture for storing one bit, such as a 6T-bit cell architecture. However, this is for illustrative purposes only and is not meant to limit the invention. The same single-ended sensing concept can be applied to memory arrays using dual-port memory cells and flying bit lines.
FIG. 6 is a schematic diagram illustrating another memory design according to an embodiment of the invention. The memory 600 includes a memory array 602 and peripheral circuitry 604. The peripheral circuits 604 may function as I/O circuits arranged to control access (read/write) of the memory array 602, and may include row decoder circuits, timing controller circuits, column decoder circuits, sense amplifier circuits, write driver circuits, and the like. Since the present invention focuses on read operations, only sense amplifier circuitry is illustrated.
The memory array 602 includes a plurality of memory cells arranged in a 2D array having a plurality of rows and a plurality of columns. As shown in fig. 6, each memory cell column may include N memory cells 606_0 to 606_i and 606_i+1 to 606_n-1. It should be noted that the memory array 602 may include a plurality of columns of memory cells. For a better understanding of the technical features of the present invention, only a single column of memory cells is illustrated in fig. 6.
In this embodiment, each of the memory cells may have a dual port SRAM architecture for storing one bit, such as an 8T bit cell architecture. Those skilled in the art can readily understand the details of a typical 8T SRAM bit cell, further description is omitted herein for brevity. The memory array 602 includes: a plurality of read word lines RWL_0 through RWL_N-1 (which are used in a read operation of an 8T SRAM bit cell); a plurality of write word lines WWL_0 through WWL_N-1 (which are used in write operations of 8T SRAM bit cells); a complementary pair of write bit lines (which are used in a write operation of an 8T SRAM bit cell and are not used in a read operation of an 8T SRAM bit cell) consisting of write bit lines WBL and WBLB; a complementary pair of write bit lines (which are used in a write operation of an 8T SRAM bit cell and are not used in a read operation of an 8T SRAM bit cell) consisting of write bit lines WBL_fly and WBLB_fly; a read bit line RBL (which is used in read operations of 8T SRAM bit cells and not in write operations of 8T SRAM bit cells); and a read bit line rbl_fly (which is used in read operations of 8T SRAM bit cells and not used in write operations of 8T SRAM bit cells), wherein read word line rwl_j and write word line wwl_j (j= {0,1, … …, N-1 }) correspond to the same memory cell row, and bit lines WBL, WBLB, WBL _fly, wblb_ fly, RBL, RBL _fly correspond to the same memory cell column.
In this embodiment, the FBL structure may be employed to increase the memory access speed. For example, each of the bit lines WBL, WBLB, and RBL is routed on a first metal layer (e.g., M0) instead of a second metal layer (e.g., M2), and each of the bit lines wbl_fly, wblb_fly, and rbl_fly is an FBL having a first segment routed on the first metal layer (e.g., M0) and a second segment routed on the second metal layer (e.g., M2), wherein the second segment routed on the second metal layer (e.g., M2) acts as an extension of the first segment routed on the first metal layer (e.g., M0) and spans the memory cells 606_i+1 through 606_n-1.
As shown in fig. 6, memory cells in the same memory cell column are divided into a first group of memory cells 608 and a second group of memory cells 610, wherein the first group of memory cells 608 is coupled to bit lines WBL, WBLB, RBL and the second group of memory cells 610 is coupled to bit lines wbl_fly, wblb_fly, rbl_fly. The first set of memory cells 608 and the second set of memory cells 610 may be separated by an edge region and a stripe region.
In this embodiment, the single-ended sense amplifier circuit 605 is arranged to perform a read operation on a target memory cell by single-ended sensing when a selected read word line is enabled. For example, a target memory cell is selected from the first group of memory cells 608 and the second group of memory cells 610 located in the same memory cell column, and the selected read word line is one of the read word lines rwl_0 to rwl_n-1.
In this embodiment, the single-ended sense amplifier circuit 605 may include a logic gate circuit (e.g., a NAND gate) 612 and an output latch circuit 614. Logic gate 612 is arranged to receive two single ended input signals. For example, logic gate 612 may have a first input node coupled to one bit line RBL and a second input node coupled to another bit line RBL_fly, where bit lines RBL and RBL_fly may be connected to SRAM cells at the same column of the memory array. It should be noted that logic gate 612 may be implemented by a NAND gate or other logic gates, depending on practical design considerations. The output latch circuit 614 has an input node coupled to the output node of the logic gate circuit 612 and an output node arranged to output the read data DO of the target memory cell. Further description is omitted herein for brevity since details of the single-ended sense amplifier circuit 605 operating with the FBL will be readily understood by those skilled in the art after reading the paragraphs above for single-ended sense amplifier circuit 105/200.
Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and methods may be made while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the scope and metes of the appended claims.

Claims (18)

1. A memory, the memory comprising:
A memory array, the memory array comprising:
A plurality of word lines;
a plurality of bit lines, the plurality of bit lines comprising:
a first bit line wired on the first metal layer but not the second metal layer; and
A second bit line wired on the first metal layer and the second metal layer,
Wherein the second metal layer is different from the first metal layer;
a plurality of memory cells, each memory cell coupled to one of the plurality of word lines, wherein the plurality of memory cells comprises:
a first set of memory cells coupled to the first bit line; and
A second set of memory cells coupled to the second bit line, wherein,
The first set of memory cells and the second set of memory cells are located at the same column; and
A single-ended sense amplifier circuit arranged to perform a read operation on a target memory cell by single-ended sensing when a selected word line is enabled, wherein the target memory cell is selected from the first set of memory cells and the second set of memory cells.
2. The memory of claim 1, wherein each memory cell included in the first and second sets of memory cells employs a single-port static random access memory SRAM cell architecture.
3. The memory of claim 1, wherein each memory cell included in the first and second sets of memory cells employs a dual port static random access memory SRAM cell architecture.
4. The memory of claim 1, wherein the single-ended sense amplifier circuit comprises:
A logic gate circuit, the logic gate circuit comprising:
a first input node coupled to the first bit line;
a second input node coupled to the second bit line; and
An output node; and
An output latch circuit, the output latch circuit comprising:
An input node coupled to the output node of the logic gate circuit; and
An output node arranged to output the read data of the target memory cell.
5. The memory of claim 4, wherein the logic gate is a nand gate.
6. The memory of claim 4, wherein the first bit line is one of two bit lines of one complementary bit line pair and the second bit line is one of two bit lines of the other complementary bit line pair.
7. The memory of claim 4, wherein the first bit line is one read bit line, the second bit line is another read bit line, and none of the first bit line and the second bit line are used by a write operation.
8. The memory of claim 1, wherein a cell number of the first set of memory cells is different from a cell number of the second set of memory cells.
9. The memory of claim 8, wherein the number of cells of the first set of memory cells is greater than the number of cells of the second set of memory cells.
10. A method of accessing a memory array comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of bit lines comprises a first bit line routed on a first metal layer and not a second metal layer and a second bit line routed on the first metal layer and the second metal layer, the second metal layer being different from the first metal layer, each of the plurality of memory cells being coupled to one of the plurality of word lines, the plurality of memory cells comprising a first group of memory cells coupled to the first bit line and a second group of memory cells coupled to the second bit line, and the first group of memory cells and the second group of memory cells being located at a same column; and the method comprises:
selecting a target memory cell from the first set of memory cells and the second set of memory cells; and
A read operation is performed on the target memory cell by single ended sensing in response to the selected word line being enabled.
11. The method of claim 10, wherein each memory cell included in the first and second sets of memory cells employs a single-port static random access memory SRAM cell architecture.
12. The method of claim 10, wherein each memory cell included in the first and second sets of memory cells employs a dual port static random access memory SRAM cell architecture.
13. The method of claim 10, wherein performing the read operation on the target memory cell using single-ended sensing comprises:
Performing a logic operation on a first input signal obtained from the first bit line and a second input signal obtained from the second bit line to generate an output signal; and
An output latch operation is performed on the output signal to generate and output read data of the target memory cell.
14. The method of claim 13, wherein the logical operation is a nand operation.
15. The method of claim 13, wherein the first bit line is one of two bit lines of one complementary bit line pair and the second bit line is one of two bit lines of the other complementary bit line pair.
16. The method of claim 13, wherein the first bit line is one read bit line, the second bit line is another read bit line, and none of the first bit line and the second bit line are used by a write operation.
17. The method of claim 10, wherein a cell number of the first set of memory cells is different from a cell number of the second set of memory cells.
18. The method of claim 17, wherein the number of cells of the first set of memory cells is greater than the number of cells of the second set of memory cells.
CN202311376942.5A 2022-10-24 2023-10-23 Memory and method for accessing memory array Pending CN118447895A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/380,598 2022-10-24
US18/371,441 2023-09-21
US18/371,441 US20240233786A9 (en) 2022-10-24 2023-09-21 Memory with fly-bitlines that work with single-ended sensing and associated memory access method

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