CN118426570B - Memory control circuit resetting method, device, equipment and medium - Google Patents
Memory control circuit resetting method, device, equipment and medium Download PDFInfo
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- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
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Abstract
The invention discloses a memory control circuit resetting method, a device, equipment and a medium, which belong to the field of data processing, and the invention successively resets a remote control circuit, a physical interface transceiver PHY circuit, an AXI interface circuit 1, an Atomic module circuit, a register control circuit 1, a register control circuit 2, an AXI interface circuit 2 and a register control circuit 3 according to the characteristics of a memory control circuit; the reset_glb signals of the remote control circuit are generated by the remote control circuit except for the SoC, the reset signals are all generated by the remote control circuit and all come from registers in the remote control circuit, and the registers in the remote control circuit can be configured by upstream software to generate corresponding reset signals, so that the whole design is flexible and configurable, the operability is stronger, and the metastable propagation in the system can be effectively restrained through the reset time sequence.
Description
Technical Field
The embodiment of the disclosure relates to the field of data processing, in particular to a memory control circuit resetting method, a device, equipment and a medium.
Background
With asynchronous components in the system, it is difficult to completely avoid the occurrence of metastables, which typically occur in asynchronous signal detection, cross-clock transfer and reset circuits. In addition to causing logic misjudgment, metastable states may propagate to the next stage of the circuit, namely, the transfer of metastable states, so that the fault plane of the whole circuit is enlarged. The system chip has higher data quality requirement on the memory control circuit, if the memory control circuit is improperly controlled in reset time sequence, the problem of metastable state transmission can occur, so that the whole chip is wrong, and therefore, how to program the reset time sequence of each module in the memory control circuit is a problem to be solved urgently.
Disclosure of Invention
The present invention is directed to a memory control circuit resetting method, apparatus, device and medium, so as to at least partially solve the above-mentioned problems.
According to one aspect of the present disclosure, a memory control circuit reset method is provided, including:
s1, resetting a remote control circuit, setting a reset signal reset_glb of the remote control circuit to be high level after resetting, wherein the remote control circuit is used for generating reset signals of all modules of a memory control circuit,
S2, setting all the reset signals of all the modules of the memory control circuit to be high level through the remote control circuit, then setting all the reset signals to be low level,
S3, after a first preset time, setting a reset signal reset_5 of a PHY circuit of the physical interface transceiver to be high level,
S4, after a second preset time, setting a reset signal reset_0 of the AXI interface circuit 1 corresponding to an upstream module clock domain to be high level, then setting a reset signal reset_1 of the AXI interface circuit 1 corresponding to a memory control circuit clock domain, an reset signal reset_2 of the Atomic module circuit and a reset signal reset_6 of the register control circuit 1 to be high level respectively, wherein the register control circuit 1 is used for configuring a register in the Atomic module, the Atomic module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
S5, after the reset_0 is set to the high level, setting the reset signal reset_4 of the register control circuit 2 to the high level after a third preset time, wherein the register control circuit 2 is used for configuring a register in a core control circuit, the core control circuit is used for converting an AXI signal into a DFI signal, optimizing and sequencing access requests,
S6, after reset_4 is set to high level, reset signal reset_3 of AXI interface circuit 2 is set to high level after a fourth preset time, AXI interface circuit 2 is used for receiving AXI signal sent by the Atomic module and forwarding the signal to the core control circuit,
S7, reset_3 is set to high level and the reset signal reset_7 of the register control circuit 3 is set to high level after a fifth predetermined time elapses.
In some embodiments, the remote control circuit reset signal reset_glb is from a SoC.
In some embodiments, the remote control circuit is configured to generate a reset signal for each module of the memory control circuit, specifically, by configuring an internal register of the remote control circuit with upstream software to generate the reset signal.
In some embodiments, the reset signal is at a low level, the corresponding module circuit is in a reset state, and the reset signal is at a high level, the corresponding module circuit is in a normal operation state.
According to another aspect of the present disclosure, there is provided a memory control circuit reset device, including:
a first reset unit for resetting the remote control circuit, after the reset is completed, setting the reset signal reset_glb of the remote control circuit to be high level, the remote control circuit is used for generating the reset signals of all modules of the memory control circuit,
A second reset unit for setting all the reset signals of each module of the memory control circuit to high level and then to low level through the remote control circuit,
A third reset unit for setting a physical interface transceiver PHY circuit reset signal reset _5 to a high level after a first predetermined time,
A fourth reset unit, configured to set a reset signal reset_0 of the AXI interface circuit 1 corresponding to the clock domain of the upstream module to a high level after a second predetermined time, and then set a reset signal reset_1 of the AXI interface circuit 1 corresponding to the clock domain of the memory control circuit, a reset signal reset_2 of the AXI module circuit, and a reset signal reset_6 of the register control circuit 1 to a high level, where the register control circuit 1 is a register used for configuring the interior of the AXI module, the AXI module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
A fifth reset unit for setting reset_0 to a high level and then setting reset_4 of the register control circuit 2 to a high level after a third predetermined time elapses, the register control circuit 2 being configured to configure registers inside a core control circuit for converting an AXI signal into a DFI signal and optimizing and ordering access requests,
A sixth reset unit, configured to set reset_4 to a high level, and after a fourth predetermined time, set reset_3 of AXI interface circuit 2 to a high level, where AXI interface circuit 2 is configured to receive an AXI signal sent by an Atomic module, and forward the signal to a core control circuit,
A seventh reset unit for setting reset_3 to a high level and setting a reset signal reset_7 of the register control circuit 3 to a high level after a fifth predetermined time elapses.
In some embodiments, the remote control circuit reset signal reset_glb is from a SoC.
In some embodiments, the remote control circuit is configured to generate a reset signal for each module of the memory control circuit, specifically, by configuring an internal register of the remote control circuit with upstream software to generate the reset signal.
In some embodiments, the reset signal is at a low level, the corresponding module circuit is in a reset state, and the reset signal is at a high level, the corresponding module circuit is in a normal operation state.
The embodiment of the application also provides electronic equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the steps in the method in any embodiment by calling the computer program stored in the memory.
The embodiment of the application also provides a computer readable storage medium storing a computer program, which is characterized in that: the computer program, when executed by a processor, performs the steps of the method of any of the embodiments above.
The method comprises the steps of resetting a remote control circuit, a physical interface transceiver PHY circuit, an AXI interface circuit 1, an Atomic module circuit, a register control circuit 1, a register control circuit 2, an AXI interface circuit 2 and a register control circuit 3 according to the characteristics of a memory control circuit; the reset_glb signals of the remote control circuit are generated by the remote control circuit except for the SoC, the reset signals are all generated by the remote control circuit and all come from registers in the remote control circuit, and the registers in the remote control circuit can be configured by upstream software to generate corresponding reset signals, so that the whole design is flexible and configurable, the operability is stronger, and the metastable propagation in the system can be effectively restrained through the reset time sequence.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Fig. 1 is a schematic diagram of a memory control circuit reset method according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a memory control circuit architecture according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a reset timing sequence of a memory control circuit according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a memory control circuit reset device according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings. The description of these embodiments is provided to assist understanding of the present invention, but is not intended to limit the present invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
It should be noted that, in the description of the present invention, the positional or positional relation indicated by the terms such as "upper", "lower", "left", "right", "front", "rear", etc. are merely for convenience of describing the present invention based on the description of the present invention shown in the drawings, and are not intended to indicate or imply that the system or element to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The terms "first" and "second" in this technical solution are merely references to the same or similar structures, or corresponding structures that perform similar functions, and are not an arrangement of the importance of these structures, nor are they ordered, or are they of a comparative size, or other meaning.
In addition, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., the connection may be a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two structures. It will be apparent to those skilled in the art that the specific meaning of the terms described above in this application may be understood in the light of the general inventive concept in connection with the present application.
The first aspect of the disclosure discloses a memory control circuit resetting method, as shown in fig. 1, which is a schematic diagram of a memory control circuit resetting method according to an embodiment of the present invention.
The memory control circuit has a plurality of modules, each module usually has a reset signal unique to itself, and the modules usually comprise:
An AXI interface module circuit for synchronizing AXI signals sent from the upstream module,
An Atomic module circuit for supporting CUDA access,
The core control circuit is used for converting the AXI signal into the dfi signal and optimizing and sequencing the access requests,
A Pipeline circuit, interposed between the core control circuit and phy, for optimizing timing,
PHY, physical interface transceiver. Between the DRAM and the pipeline circuit,
The circuitry associated with the registers is configured to,
Remote system control circuitry.
In resetting the memory control circuit (memory controller, hereinafter referred to as MC), the following are generally considered:
1. Upon reset, the metastable state of the previous stage cannot pass to the next stage. The whole chip needs to suppress the spread of metastables as much as possible;
2. since there are many memory control circuit modules, there are many corresponding clock signals. If the module is synchronously reset, synchronizing a reset signal to the clock domain of the module; if the module is asynchronous reset, a synchronous reset and asynchronous release circuit is required to be designed;
3. Since some of the blocks in the memory control circuit are synchronously reset, a corresponding clock is required. This part of the clock is generated from the phase locked loop of the PHY, which requires the entire system to reset the PHY first.
Referring to fig. 1, a memory control circuit reset method according to the present disclosure includes the following steps:
s1, resetting a remote control circuit, setting a reset signal reset_glb of the remote control circuit to be high level after resetting, wherein the remote control circuit is used for generating reset signals of all modules of a memory control circuit,
S2, setting all the reset signals of all the modules of the memory control circuit to be high level through the remote control circuit, then setting all the reset signals to be low level,
S3, after a first preset time, setting a reset signal reset_5 of a PHY circuit of the physical interface transceiver to be high level,
S4, after a second preset time, setting a reset signal reset_0 of the AXI interface circuit 1 corresponding to an upstream module clock domain to be high level, then setting a reset signal reset_1 of the AXI interface circuit 1 corresponding to a memory control circuit clock domain, an reset signal reset_2 of the Atomic module circuit and a reset signal reset_6 of the register control circuit 1 to be high level respectively, wherein the register control circuit 1 is used for configuring a register in the Atomic module, the Atomic module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
S5, after reset_0 is set to high level, setting reset signal reset_4 of register control circuit 2 to high level, wherein register control circuit 2 is used for configuring internal registers of core control circuit, and core control circuit is used for converting AXI signal into dfi signal, optimizing and ordering access request,
S6, after reset_4 is set to high level, reset signal reset_3 of AXI interface circuit 2 is set to high level after a fourth preset time, AXI interface circuit 2 is used for receiving AXI signal sent by the Atomic module and forwarding the signal to the core control circuit,
S7, reset_3 is set to high level and the reset signal reset_7 of the register control circuit 3 is set to high level after a fifth predetermined time elapses.
In some embodiments, as shown in fig. 2, a schematic diagram of a memory control circuit architecture, wherein,
An AXI interface circuit 1 for synchronizing AXI signals sent from upstream modules. Because the clocks of the upstream module (not shown in the figure) and MC are not identical, AXI interface circuit 1 can be divided into two resets according to the difference in clock domain, reset_0 and reset_1, respectively;
an Atomic module circuit for supporting CUDA access, the module is synchronously reset, reset_2 is used,
AXI interface circuit 2 is arranged to receive an AXI signal from the Atomic and to forward this signal to the core control circuit, the module being asynchronously reset, using reset 3,
A core control circuit for converting the AXI signal into a DFI signal and optimizing and ordering the access requests, the module being an asynchronous reset, using reset _4,
A Pipeline module circuit, interposed between the core control circuit and phy, for optimizing timing, the module being an asynchronous reset, using reset _4,
PHY, physical interface transceiver. Between the DRAM and the pipeline circuit; the module is reset asynchronously, using reset _5,
The register control circuit 1 is for configuring registers inside an Atomic module and observing the state inside the Atomic module. The module is a synchronous reset and in some embodiments the module uses a different clock than the Atomic circuit for power consumption, so it cannot share a reset with the Atomic. The module is used to reset _6,
The register control circuit 2 is for configuring registers inside the core control circuit and observing the internal states of the core control circuit. The module is reset asynchronously, the clock used is different from the clock of the core control circuit, so that the module cannot share a reset with the core control circuit, the module uses reset_4,
The register control circuit 3 is for configuring PHY internal registers and observing PHY internal states. The module is asynchronously reset, uses the same clock as the PHY, so shares a reset _5 with the PHY,
And the remote system control circuit is used for generating reset signals required by the modules. The reset signal itself comes from a control circuit (not shown in the figure) of SoC (System on Chip). The module is synchronously reset, using reset_glb.
For the purpose of illustrating the inventive concept in detail, the present embodiment is described with a specific example. Referring to the reset timing diagram shown in fig. 3, a specific reset method includes the steps of:
1. firstly reset_glb resets a remote control circuit, and after the reset is completed, reset_glb is set to be high level;
2. Reset_0 to 7 are all set to high level through the remote control circuit and then set to low level. The purpose of this is to make a reset falling edge, ensuring that circuits that are only sensitive to reset edges enter reset;
3. after waiting 320ns, reset_5 is set high. Waiting 320ns is to ensure that the PHY has been sufficiently reset;
Since the PHY will provide data_clk, we need to reset the PHY first;
3 after reset_5 is set high, wait for 500ns again, set reset_0 high. Waiting 500ns is to wait for PHY PLL to start vibrating. Because AXI interface circuit 1 and the Atomic module are synchronously reset, the clock generated by the PHY PLL is needed;
4. After reset_0 is set to high level, reset_1, reset_2, reset_6 are set to high level. Releasing the AXI interface module 1 of the atmospheric module and resetting the register control circuit 1;
5. After reset_0 is set to a high level and 100ns later, reset_4 is set to a high level, and reset of the core control circuit is released;
6. after reset_4 is set high for 100ns, reset reset_3 of AXI interface circuit 2 is released.
7. After reset_3 is set high for 100ns, reset reset_7 of register circuit 3 is released.
Wherein reset is active low, i.e., when low, the module is in a reset state. When reset is high, the circuit is in normal operation.
Wherein register_clk refers to the clock of the register circuit; data_clk is the clock of the data (non-register portion).
It will be appreciated that, according to the actual situation, the reset intervals of the different modules may be adjusted according to the reset sequence, which is not limited in this embodiment.
In some embodiments, the reset_glb signal of the remote control circuit is from the SoC, the other reset signals are generated by the remote control circuit, the reset signals are from registers in the remote control circuit, and the registers in the remote control circuit can be configured by upstream software to generate corresponding reset signals, so that the overall design is flexible and configurable, and the operability is higher.
A second aspect of the present disclosure discloses a memory control circuit reset device, as shown in fig. 4, which includes:
a first reset unit for resetting the remote control circuit, after the reset is completed, setting the reset signal reset_glb of the remote control circuit to be high level, the remote control circuit is used for generating the reset signals of all modules of the memory control circuit,
A second reset unit for setting all the reset signals of each module of the memory control circuit to high level and then to low level through the remote control circuit,
A third reset unit for setting a physical interface transceiver PHY circuit reset signal reset _5 to a high level after a first predetermined time,
A fourth reset unit, configured to set a reset signal reset_0 of the AXI interface circuit 1 corresponding to the clock domain of the upstream module to a high level after a second predetermined time, and then set a reset signal reset_1 of the AXI interface circuit 1 corresponding to the clock domain of the memory control circuit, a reset signal reset_2 of the AXI module circuit, and a reset signal reset_6 of the register control circuit 1 to a high level, where the register control circuit 1 is a register used for configuring the interior of the AXI module, the AXI module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
A fifth reset unit for setting reset_0 to a high level and then setting reset_4 of the register control circuit 2 to a high level after a third predetermined time elapses, the register control circuit 2 being configured to configure registers inside a core control circuit for converting an AXI signal into a DFI signal and optimizing and ordering access requests,
A sixth reset unit, configured to set reset_4 to a high level, and after a fourth predetermined time, set reset_3 of AXI interface circuit 2 to a high level, where AXI interface circuit 2 is configured to receive an AXI signal sent by an Atomic module, and forward the signal to a core control circuit,
A seventh reset unit for setting reset_3 to a high level and setting a reset signal reset_7 of the register control circuit 3 to a high level after a fifth predetermined time elapses.
In some embodiments, the remote control circuit reset signal reset_glb is from a SoC.
In some embodiments, the remote control circuit is configured to generate a reset signal for each module of the memory control circuit, specifically, by configuring an internal register of the remote control circuit with upstream software to generate the reset signal.
In some embodiments, the reset signal is at a low level, the corresponding module circuit is in a reset state, and the reset signal is at a high level, the corresponding module circuit is in a normal operation state.
A third aspect of the disclosure discloses an electronic device, which may be a terminal or a server. Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application, as shown in fig. 5.
The electronic device 500 includes a processor 501 having one or more processing cores, a memory 502 having one or more computer readable storage media, and a computer program stored on the memory 502 and executable on the processor. The processor 501 is electrically connected to the memory 502. It will be appreciated by those skilled in the art that the electronic device structure shown in the figures is not limiting of the electronic device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
The processor 501 is a control center of the electronic device 500, connects various parts of the entire electronic device 500 using various interfaces and lines, and performs various functions of the electronic device 500 and processes data by running or loading software programs (computer programs) and/or units stored in the memory 502, and calling data stored in the memory 502, thereby performing overall monitoring of the electronic device 500.
In the embodiment of the present application, the processor 501 in the electronic device 500 loads the instructions corresponding to the processes of one or more application programs into the memory 502 according to the following steps, and the processor 501 executes the application programs stored in the memory 502, so as to implement various functions:
s1, resetting a remote control circuit, setting a reset signal reset_glb of the remote control circuit to be high level after resetting, wherein the remote control circuit is used for generating reset signals of all modules of a memory control circuit,
S2, setting all the reset signals of all the modules of the memory control circuit to be high level through the remote control circuit, then setting all the reset signals to be low level,
S3, after a first preset time, setting a reset signal reset_5 of a PHY circuit of the physical interface transceiver to be high level,
S4, after a second preset time, setting a reset signal reset_0 of the AXI interface circuit 1 corresponding to an upstream module clock domain to be high level, then setting a reset signal reset_1 of the AXI interface circuit 1 corresponding to a memory control circuit clock domain, an reset signal reset_2 of the Atomic module circuit and a reset signal reset_6 of the register control circuit 1 to be high level respectively, wherein the register control circuit 1 is used for configuring a register in the Atomic module, the Atomic module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
S5, after the reset_0 is set to the high level, setting the reset signal reset_4 of the register control circuit 2 to the high level after a third preset time, wherein the register control circuit 2 is used for configuring a register in a core control circuit, the core control circuit is used for converting an AXI signal into a DFI signal, optimizing and sequencing access requests,
S6, after reset_4 is set to high level, reset signal reset_3 of AXI interface circuit 2 is set to high level after a fourth preset time, AXI interface circuit 2 is used for receiving AXI signal sent by the Atomic module and forwarding the signal to the core control circuit,
S7, reset_3 is set to high level and the reset signal reset_7 of the register control circuit 3 is set to high level after a fifth predetermined time elapses.
Optionally, as shown in fig. 5, the electronic device 500 further includes: a memory control circuit reset device 503, a communication module 504, an input unit 505, and a power supply 506. The processor 501 is electrically connected to the memory control circuit resetting device 503, the communication module 504, the input unit 505 and the power supply 506, respectively. It will be appreciated by those skilled in the art that the electronic device structure shown in fig. 5 is not limiting of the electronic device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
The memory control circuit resetting device 503 may be used to implement resetting of the module circuits of the memory control circuit.
The communication module 504 may be used to communicate with other devices.
The input unit 505 may be used to receive input numbers, character information, or user characteristic information (e.g., fingerprint, iris, facial information, etc.), and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control.
The power supply 506 is used to power the various components of the electronic device 500. Alternatively, the power supply 506 may be logically connected to the processor 501 through a power management system, so as to perform functions of managing charging, discharging, and power consumption management through the power management system. The power supply 506 may also include one or more of any of a direct current or alternating current power supply, a recharging system, a power failure detection circuit, a power converter or inverter, a power status indicator, and the like.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
A fourth aspect of the present disclosure discloses a computer-readable storage medium, and those of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be implemented by instructions, or by controlling related hardware by instructions, which may be stored in a computer-readable storage medium and loaded and executed by a processor.
To this end, an embodiment of the present application provides a computer readable storage medium storing a plurality of computer programs capable of being loaded by a processor to execute the steps of a memory control circuit resetting method provided by the embodiment of the present application. For example, the computer program may perform the steps of:
s1, resetting a remote control circuit, setting a reset signal reset_glb of the remote control circuit to be high level after resetting, wherein the remote control circuit is used for generating reset signals of all modules of a memory control circuit,
S2, setting all the reset signals of all the modules of the memory control circuit to be high level through the remote control circuit, then setting all the reset signals to be low level,
S3, after a first preset time, setting a reset signal reset_5 of a PHY circuit of the physical interface transceiver to be high level,
S4, after a second preset time, setting a reset signal reset_0 of the AXI interface circuit 1 corresponding to an upstream module clock domain to be high level, then setting a reset signal reset_1 of the AXI interface circuit 1 corresponding to a memory control circuit clock domain, an reset signal reset_2 of the Atomic module circuit and a reset signal reset_6 of the register control circuit 1 to be high level respectively, wherein the register control circuit 1 is used for configuring a register in the Atomic module, the Atomic module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
S5, after the reset_0 is set to the high level, setting the reset signal reset_4 of the register control circuit 2 to the high level after a third preset time, wherein the register control circuit 2 is used for configuring a register in a core control circuit, the core control circuit is used for converting an AXI signal into a DFI signal, optimizing and sequencing access requests,
S6, after reset_4 is set to high level, reset signal reset_3 of AXI interface circuit 2 is set to high level after a fourth preset time, AXI interface circuit 2 is used for receiving AXI signal sent by the Atomic module and forwarding the signal to the core control circuit,
S7, reset_3 is set to high level and the reset signal reset_7 of the register control circuit 3 is set to high level after a fifth predetermined time elapses.
The specific implementation of each operation may be referred to the foregoing embodiments, and will not be described herein.
Wherein the computer-readable storage medium may comprise: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.
The steps in any memory control circuit resetting method provided by the embodiment of the present application can be executed by the computer program stored in the storage medium, so that the beneficial effects of any memory control circuit resetting method provided by the embodiment of the present application can be achieved, which are detailed in the previous embodiments and are not described herein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a system for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, and yet fall within the scope of the invention.
Claims (10)
1. A memory control circuit reset method, the method comprising:
s1, resetting a remote control circuit, setting a reset signal reset_glb of the remote control circuit to be high level after resetting, wherein the remote control circuit is used for generating reset signals of all modules of a memory control circuit,
S2, setting all the reset signals of all the modules of the memory control circuit to be high level through the remote control circuit, then setting all the reset signals to be low level,
S3, after a first preset time, setting a reset signal reset_5 of a PHY circuit of the physical interface transceiver to be high level,
S4, after a second preset time, setting a reset signal reset_0 of the AXI interface circuit 1 corresponding to an upstream module clock domain to be high level, then setting a reset signal reset_1 of the AXI interface circuit 1 corresponding to a memory control circuit clock domain, an reset signal reset_2 of the Atomic module circuit and a reset signal reset_6 of the register control circuit 1 to be high level respectively, wherein the register control circuit 1 is used for configuring a register in the Atomic module, the Atomic module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
S5, after the reset_0 is set to the high level, setting the reset signal reset_4 of the register control circuit 2 to the high level after a third preset time, wherein the register control circuit 2 is used for configuring a register in a core control circuit, the core control circuit is used for converting an AXI signal into a DFI signal, optimizing and sequencing access requests,
S6, after reset_4 is set to high level, reset signal reset_3 of AXI interface circuit 2 is set to high level after a fourth preset time, AXI interface circuit 2 is used for receiving AXI signal sent by the Atomic module and forwarding the signal to the core control circuit,
S7, reset_3 is set to high level and the reset signal reset_7 of the register control circuit 3 is set to high level after a fifth predetermined time elapses.
2. The method according to claim 1, characterized in that:
the remote control circuit reset signal reset_glb is from the SoC.
3. The method as recited in claim 1, further comprising:
the remote control circuit is used for generating reset signals of all modules of the memory control circuit, specifically, the upstream software is used for configuring an internal register of the remote control circuit to generate the corresponding reset signals.
4. The method according to claim 1, characterized in that:
when the reset signal is at a low level, the corresponding module circuit is in a reset state, and when the reset signal is at a high level, the corresponding module circuit is in a normal working state.
5. A memory control circuit reset device, characterized in that: comprising the following steps:
a first reset unit for resetting the remote control circuit, after the reset is completed, setting the reset signal reset_glb of the remote control circuit to be high level, the remote control circuit is used for generating the reset signals of all modules of the memory control circuit,
A second reset unit for setting all the reset signals of each module of the memory control circuit to high level and then to low level through the remote control circuit,
A third reset unit for setting a physical interface transceiver PHY circuit reset signal reset _5 to a high level after a first predetermined time,
A fourth reset unit, configured to set a reset signal reset_0 of the AXI interface circuit 1 corresponding to the clock domain of the upstream module to a high level after a second predetermined time, and then set a reset signal reset_1 of the AXI interface circuit 1 corresponding to the clock domain of the memory control circuit, a reset signal reset_2 of the AXI module circuit, and a reset signal reset_6 of the register control circuit 1 to a high level, where the register control circuit 1 is a register used for configuring the interior of the AXI module, the AXI module circuit is used for supporting CUDA access, the AXI interface circuit 1 is used for synchronizing the AXI signals sent by the upstream module,
A fifth reset unit for setting reset_0 to a high level and then setting reset_4 of the register control circuit 2 to a high level after a third predetermined time elapses, the register control circuit 2 being configured to configure registers inside a core control circuit for converting an AXI signal into a DFI signal and optimizing and ordering access requests,
A sixth reset unit, configured to set reset_4 to a high level, and after a fourth predetermined time, set reset_3 of AXI interface circuit 2 to a high level, where AXI interface circuit 2 is configured to receive an AXI signal sent by an Atomic module, and forward the signal to a core control circuit,
A seventh reset unit for setting reset_3 to a high level and setting a reset signal reset_7 of the register control circuit 3 to a high level after a fifth predetermined time elapses.
6. The apparatus according to claim 5, wherein:
the remote control circuit reset signal reset_glb is from the SoC.
7. The apparatus according to claim 6, wherein:
the remote control circuit is used for generating reset signals of all modules of the memory control circuit, specifically, the upstream software is used for configuring an internal register of the remote control circuit to generate the corresponding reset signals.
8. The apparatus of claim 7, wherein the device comprises a plurality of sensors,
When the reset signal is at a low level, the corresponding module circuit is in a reset state, and when the reset signal is at a high level, the corresponding module circuit is in a normal working state.
9. An electronic device, characterized in that: comprising a memory storing executable program code and a processor coupled to the memory; wherein the processor invokes executable program code stored in the memory to perform the method of any of claims 1-4.
10. A computer-readable storage medium storing a computer program, characterized in that: the computer program, when executed by a processor, performs the method of any of claims 1-4.
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| CN110780724A (en) * | 2019-08-23 | 2020-02-11 | 天津大学 | Method for resetting flash memory device executed by storage controller of host |
| CN111128269A (en) * | 2019-11-21 | 2020-05-08 | 深圳市国微电子有限公司 | DDR bit delay alignment method, device and storage medium |
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| US7272709B2 (en) * | 2002-12-26 | 2007-09-18 | Micron Technology, Inc. | Using chip select to specify boot memory |
| US20130227257A1 (en) * | 2012-02-23 | 2013-08-29 | Freescale Semiconductor, Inc | Data processor with asynchronous reset |
| US8705266B2 (en) * | 2012-03-23 | 2014-04-22 | Kabushiki Kaisha Toshiba | Semiconductor device and method for controlling the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110780724A (en) * | 2019-08-23 | 2020-02-11 | 天津大学 | Method for resetting flash memory device executed by storage controller of host |
| CN111128269A (en) * | 2019-11-21 | 2020-05-08 | 深圳市国微电子有限公司 | DDR bit delay alignment method, device and storage medium |
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