CN118412359A

CN118412359A - Image sensor and method of manufacturing the same

Info

Publication number: CN118412359A
Application number: CN202410023653.5A
Authority: CN
Inventors: 朴惠涓; 李允基; 金智恩; 朴巨成; 林夏珍; 全宅洙; 崔现圭; 许在成
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2023-01-27
Filing date: 2024-01-08
Publication date: 2024-07-30

Abstract

An image sensor and a method of manufacturing the same are provided. The image sensor includes: a first substrate including a pixel region and a peripheral region adjacent to the pixel region, the pixel region including a plurality of pixels in a two-dimensional array; a first wiring layer on a lower surface of the first substrate; an anti-reflection layer having a first refractive index, the anti-reflection layer being on an upper surface of the first substrate; and color filters corresponding to the pixel regions on the anti-reflection layer and spaced apart from each other by a metal-free grid pattern.

Description

Image sensor and method of manufacturing the same

The present application is based on and claims priority of korean patent application No. 10-2023-0011106 filed in the korean intellectual property office at 1 month 27 of 2023, korean patent application No. 10-2023-0033475 filed in 3 month 14 of 2023, and korean patent application No. 10-2023-0085982 filed in 7 month 3 of 2023, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

Embodiments of the present disclosure relate to an image sensor, and more particularly, to an image sensor including a grid for separating color filters from each other, and a method of manufacturing the image sensor.

Background

An image sensor is a semiconductor device that can convert optical information into an electrical signal. The image sensor may include a pixel array including a plurality of pixels arranged in two dimensions. The pixels may each include at least one photodiode. The photodiode may convert light incident thereon into an electrical signal. The pixel array may include a pixel array region including pixels generating the image signal and a light blocking region including reference pixels generating the reference signal at the dark level. The image sensor may process the image signal by referring to the reference signal, thereby generating a final image signal. The light blocking region may include a light blocking film such that light incident on the light blocking film is blocked from being transferred to the reference pixel under the light blocking film.

Disclosure of Invention

One or more embodiments provide an image sensor and a method of manufacturing the image sensor, which may exhibit improved Quantum Efficiency (QE) and improve stain defects.

The embodiments are not limited in the above-described aspects, and the above-described and other aspects of the embodiments will be clearly understood by those of ordinary skill in the art from the following detailed description.

According to an aspect of the embodiments, there is provided an image sensor including: a first substrate including a pixel region and a peripheral region adjacent to the pixel region, the pixel region including a plurality of pixels in a two-dimensional array; a first wiring layer on a lower surface of the first substrate; an anti-reflection layer having a first refractive index, the anti-reflection layer being on an upper surface of the first substrate; and color filters corresponding to the pixel regions on the anti-reflection layer and spaced apart from each other by a metal-free grid pattern.

According to another aspect of the embodiments, there is provided an image sensor including a first semiconductor chip including a first substrate including a pixel region and a peripheral region adjacent to the pixel region, a plurality of pixels having a two-dimensional array structure in the pixel region, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a logic device, wherein an anti-reflection layer including a TiO ₂ layer is on an upper surface of the first substrate, wherein a color filter has a two-dimensional array structure on the anti-reflection layer of the pixel region, and wherein the color filters are spaced apart from each other by a metal-free grid pattern having a two-dimensional grid shape.

According to another aspect of the embodiments, there is provided an image sensor including: the first substrate comprises a pixel area and a peripheral area adjacent to the pixel area, wherein a plurality of pixels are in a two-dimensional array structure in the pixel area; a first wiring layer on a lower surface of the first substrate; an anti-reflection layer on an upper surface of the first substrate and including a TiO ₂ layer; a color filter having a two-dimensional array structure on the anti-reflection layer of the pixel region; a grid pattern on the anti-reflection layer of the pixel region and separating the color filters from each other in a two-dimensional grid shape, the grid pattern including a single insulating layer having a low refractive index and no metal; a microlens on the color filter and the grid pattern; a second wiring layer under the first wiring layer; and a second substrate under the second wiring layer.

According to another aspect of the embodiments, there is provided a method of manufacturing an image sensor, the method including: forming a plurality of pixels each including a photodiode in a pixel region of a first substrate of a first semiconductor chip and forming a first wiring layer on an active surface of the first substrate; forming a logic device in a second substrate of a second semiconductor chip and forming a second wiring layer on an active surface of the second substrate; connecting the first semiconductor chip and the second semiconductor chip to each other such that the first wiring layer faces the second wiring layer; removing a portion of the passive surface of the first substrate; forming an anti-reflection layer having a first refractive index on a passive surface of a first substrate; forming a through hole in a peripheral region of the first substrate, the peripheral region of the first substrate being adjacent to the pixel region; forming color filters corresponding to the plurality of pixels, respectively, on the anti-reflection layer of the pixel region; and forming microlenses on the color filters, respectively, wherein the step of forming the color filters includes forming a metal-free grid pattern having a two-dimensional grid shape in the pixel region and forming the color filters in grids of the grid pattern, respectively.

Drawings

Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of an image sensor according to an embodiment;

fig. 2 is a perspective view of the image sensor of fig. 1, more specifically, an exploded perspective view showing a first semiconductor chip and a second semiconductor chip separated from each other;

fig. 3 is an equivalent circuit diagram of some unit pixels in a pixel region of the image sensor of fig. 1;

FIG. 4 is a plan view of the image sensor of FIG. 1;

FIG. 5 is a cross-sectional view of the image sensor of FIG. 1 taken along line I-I' of FIG. 4;

Fig. 6A is a graph showing an extinction coefficient (i.e., κ) of TiN as a function of wavelength, and fig. 6B is a graph showing a Quantum Efficiency (QE) of each type of grid pattern as a function of wavelength;

fig. 7A and 7B are conceptual diagrams showing loss and improvement of QE in the image sensor of the related example and the image sensor according to the embodiment, respectively;

fig. 8A and 8B are cross-sectional views respectively showing the grid pattern structures of the image sensor of the related example and the image sensor according to the embodiment;

Fig. 9A is an enlarged cross-sectional view of a region A1 of fig. 8A, fig. 9B is an enlarged cross-sectional view of a region A2 of fig. 8B, and fig. 9C is a cross-sectional view showing an anti-reflection layer of a node spacer of an image sensor according to an embodiment;

Fig. 10A, 10B, 11A, 11B, 12A and 12B illustrate plan views and cross-sectional views corresponding thereto of node spacers of the anti-reflection layer of fig. 9C at various locations in the image sensor of fig. 1;

Fig. 13A, 13B, 13C, 13D, 13E, 13F, 13G, 13H, 13I, 13J, and 13K are cross-sectional views respectively showing a series of processes of a method of manufacturing an image sensor according to an embodiment; and

Fig. 14A and 14B are cross-sectional views showing a process of forming a grid pattern in the image sensor of the related example and the image sensor according to the embodiment, respectively.

Detailed Description

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are denoted by the same reference numerals, and repetitive description thereof will be omitted.

Fig. 1 is a block diagram of an image sensor according to an embodiment.

Referring to fig. 1, an image sensor 1000 may include a pixel region 100 (or PA), a row driver 200, a mode setting register 300, a timing controller 400, a ramp signal generator 500, an analog-to-digital converter (ADC) block 600, and a signal processor 700.

The pixel region 100 may include a pixel array region APS and a light blocking region OB. As shown in fig. 1, the pixel array area APS may be disposed in a central portion of the pixel area 100, and the light blocking area OB may be disposed in a peripheral portion of the pixel area 100 to be disposed adjacent to and surrounding the pixel array area APS. For example, the pixel array area APS may be referred to as an active pixel sensor area, and the light blocking area OB may be referred to as an optical black pixel area. Each of the pixel array area APS and the light blocking area OB may include a plurality of unit pixels arranged two-dimensionally. The unit pixel may convert an optical signal into an electrical signal. Each of the unit pixels of the pixel region 100 may output an electric signal through a column line CL corresponding thereto in response to a plurality of driving signals DS (such as a pixel selection signal, a reset signal, and a charge transfer signal) based on a row from the row driver 200.

The row driver 200 may select and drive the unit pixels of the pixel region 100 based on the rows. The row driver 200 may decode a row control signal (e.g., an address signal) received from the timing controller 400 and may generate a plurality of driving signals DS corresponding to the decoded row lines to transmit the plurality of driving signals DS to the pixel region 100.

The mode setting register 300 may correspond to a register of an Application Processor (AP) for connection with the image sensor 1000 to set an operation mode of the image sensor 1000 through an interface. The AP may change the operating condition of the image sensor 1000 on a frame basis through the mode setting register 300.

The timing controller 400 may commonly control the operations of the circuit blocks (i.e., 200, 400, and 500) of the image sensor 1000 according to the mode setting information set in the mode setting register 300.

The RAMP signal generator 500 may generate a RAMP signal RAMP that increases or decreases with a specific slope, and may provide the RAMP signal RAMP to the ADC block 600.

The ADC block 600 may convert an analog electric signal output from the column line CL of the pixel region 100 into a digital image signal by a Correlated Double Sampling (CDS) method. The CDS method may allow the noise level and the signal level of the unit pixel transferred to the column line to be double-sampled, and allow a difference level corresponding to a difference between the noise level and the signal level to be converted and generated into a digital image signal.

The signal processor 700 may process the received image signal to output a final image signal. The signal processing of the signal processor 700 may include noise reduction, gain adjustment, waveform normalization, interpolation, white balancing, gamma processing, edge enhancement, merging (binning), and the like.

Fig. 2 is a perspective view of the image sensor 1000 of fig. 1, and more particularly, is an exploded perspective view showing a first semiconductor chip and a second semiconductor chip separated from each other. The description is described with reference to fig. 2 in conjunction with fig. 1, and the description that has been given with reference to fig. 1 is briefly or omitted.

Referring to fig. 2, the image sensor 1000 according to an embodiment may include two semiconductor chips (i.e., CH1 and CH 2). The pixel region 100 of the image sensor 1000 of fig. 1 may be disposed in the first semiconductor chip CH 1. All circuit blocks (i.e., 200 to 700) except the pixel region 100 of the image sensor 1000 of fig. 1 may be arranged in the second semiconductor chip CH 2. The first semiconductor chip CH1 and the second semiconductor chip CH2 may be stacked vertically on each other. The first and second semiconductor chips CH1 and CH2 may transmit signals to each other through a wiring layer of each of the first and second semiconductor chips CH1 and through silicon vias (TSVs, or "silicon vias") or inter-chip connection terminals through the first semiconductor chip CH 1.

In an embodiment, the image sensor 1000 may include three semiconductor chips stacked. When the image sensor 1000 includes three semiconductor chips stacked, the pixel region 100 may be formed in the uppermost first semiconductor chip, and here, some components constituting the unit pixel may be arranged in the first semiconductor chip. For example, a photodiode (see PD of fig. 3), a transfer transistor (see TX of fig. 3), and a floating diffusion region (see FD of fig. 3) constituting a unit pixel may be arranged in the first semiconductor chip. The pixel region 100 may also be formed in a second semiconductor chip located under the first semiconductor chip, and here, pixel transistors other than the transfer transistor TX, such as a reset transistor (see RX of fig. 3), a source follower transistor (see DX of fig. 3), and a selection transistor (see SX of fig. 3), may be arranged in the second semiconductor chip. The transfer transistor TX and the floating diffusion FD in the first semiconductor chip may be connected with the pixel transistors (i.e., RX, DX, and SX) in the second semiconductor chip and their counterparts through TSVs, inter-chip connection terminals, and the like. The circuit blocks (i.e., 200 to 700) other than the pixel region 100 may be arranged in a third semiconductor chip located under the second semiconductor chip. The third semiconductor chip may be connected to the second semiconductor chip through TSVs, inter-chip connection terminals, and the like.

Fig. 3 is a circuit diagram of some unit pixels in the pixel region 100 of the image sensor 1000 of fig. 1. The description is described with reference to fig. 3 together with fig. 1 and 2, and the description that has been given with reference to fig. 1 and 2 is briefly or omitted.

Referring to fig. 3, the pixel region 100 may include a plurality of unit pixels UP, and the unit pixels UP may be arranged in a two-dimensional array structure. The unit pixel UP may include a photodiode PD and a pixel transistor. The pixel transistors may include a transfer transistor TX, a reset transistor RX, a source follower transistor DX, and a selection transistor SX. Further, the unit pixel UP may include a floating diffusion region FD connected to a source or drain of each of the transfer transistor TX and the reset transistor RX, and connected to a gate of the source follower transistor DX.

The photodiode PD may generate and accumulate charges in proportion to the amount of light incident from the outside thereof during the exposure period. In the image sensor 1000 according to the embodiment, a phototransistor, a clamp photodiode (pinned photodiode), or the like may be arranged instead of the photodiode PD. Therefore, a device that converts light into electric charge is called a photoelectric conversion device.

The transfer transistor TX may transfer the charges accumulated in the photodiode PD during the exposure period to the floating diffusion region FD in response to a transfer control signal. The charge transferred from the photodiode PD via the transfer transistor TX may be stored in the floating diffusion region FD. The voltage of the gate of the source follower transistor DX may be determined according to the amount of charge stored in the floating diffusion region FD.

The reset transistor RX may reset the charge stored in the floating diffusion region FD. A source of the reset transistor RX may be connected to the floating diffusion FD, and a drain of the reset transistor RX may be connected to the power supply voltage V _DD. When the reset transistor RX is turned on by the reset control signal RG, the power supply voltage V _DD of the drain of the reset transistor RX may be applied to the floating diffusion region FD and charges may be discharged. Accordingly, when the reset transistor RX is turned on, all charges stored in the floating diffusion region FD may be discharged, and the voltage of the floating diffusion region FD may be reset to the power supply voltage V _DD.

The source follower transistor DX may include a gate connected to the floating diffusion FD, a drain connected to the power supply voltage V _DD, and a source connected to the selection transistor SX. The source follower transistor DX may function as a source follower buffer amplifier generating an output voltage in its source in response to the voltage of its gate.

The selection transistor SX may transmit an output voltage to the source of the source follower transistor DX to the column line CL in response to the column selection signal SEL. For example, the source follower transistor DX and the selection transistor SX may sense a voltage change of the floating diffusion region FD, and thus output the output voltage V _OUT to the column line CL.

In the unit pixel UP of fig. 3, one floating diffusion FD and pixel transistors (i.e., RX, DX, and SX) corresponding thereto may be arranged one-to-one in one photodiode PD. However, the unit pixel constituting the high resolution image sensor may have a shared pixel structure in which a plurality of photodiodes PD share one floating diffusion region FD and pixel transistors (i.e., RX, DX, and SX) corresponding thereto.

Fig. 4 is a plan view of the image sensor 1000 of fig. 1, and fig. 5 is a cross-sectional view of the image sensor 1000 taken along line I-I' of fig. 4. The description is described with reference to fig. 4 and 5 together with fig. 1 to 3, and the description that has been given with reference to fig. 1 to 3 is briefly or omitted.

Referring to fig. 4 and 5, the image sensor 1000 according to the embodiment may include a first semiconductor chip CH1 and a second semiconductor chip CH2. In the image sensor 1000 according to the embodiment, for example, the first semiconductor chip CH1 may be stacked on the second semiconductor chip CH2.

The first semiconductor chip CH1 may include a first substrate 101. The first substrate 101 may include silicon (Si). The first substrate 101 may include, for example, a silicon single crystal substrate, a silicon epitaxial layer substrate, or a Silicon On Insulator (SOI) substrate. However, the material of the first substrate 101 is not limited to Si. For example, the first substrate 101 may include another single element semiconductor such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first substrate 101 may be doped with, for example, an impurity of the first conductivity type. Here, the first conductive type may be a P type. However, the first conductivity type is not limited to P-type. The first substrate 101 may include a front surface (or "lower surface") 101f and a rear surface (or "upper surface") 101b opposite to each other. Here, the front surface 101f may correspond to an effective surface, and the rear surface 101b may correspond to an ineffective surface.

In a plan view of the first semiconductor chip CH1, the image sensor 1000 may include a pixel region PA and a peripheral region PE. As described with reference to fig. 1, the pixel region PA may include a pixel array region APS and a light blocking region OB. A plurality of unit pixels UP may be formed in the first substrate 101 in the pixel array area APS and the light blocking area OB. As shown in fig. 4, the light blocking area OB may surround the pixel array area APS. For example, although fig. 4 shows that the pixel array area APS is centrally located with a small area, and each of the light blocking area OB and the peripheral area PE has a relatively large area, the embodiment is not limited thereto. In the image sensor 1000 according to the embodiment, the pixel array area APS may occupy a large portion of the first semiconductor chip CH1, and the light blocking area OB and the peripheral area PE may each be disposed outside the pixel array area APS with a relatively small area.

The peripheral region PE may be adjacent to and surround the pixel region PA (i.e., the light blocking region OB). The peripheral region PE may include, for example, a contact region BR1, a backside via stack region BR2, and a pad region PR. The contact region BR1 may be disposed adjacent to the light blocking region OB. In the contact region BR1, the back-side contacts BCA may be linearly arranged at certain intervals along a line surrounding the light blocking region OB.

The backside via stack region BR2 may be located between the contact region BR1 and the pad region PR. The backside via stack (alternatively referred to as a "through via" or "first through via") BVS may be arranged in a backside via stack region BR 2. In fig. 4, the backside via stack BVS is arranged in a line to be adjacent to the contact area BR1 and to be disposed around the contact area BR 1. However, the embodiment is not limited thereto, and the backside via stack BVS may be arranged in the backside via stack region BR2 in a two-dimensional array structure. Further, although the backside via stack BVS is disposed adjacent to all sides of the contact region BR1, the embodiment is not limited thereto, and the backside via stack BVS may not be disposed at least one side of the contact region BR 1. According to some embodiments, a shielding region may be defined between the contact region BR1 and the pad region PR, and a backside via stack region BR2 may be disposed in a portion of the shielding region.

The pad region PR may be located in an outermost portion of the peripheral region PE. Backside vias (alternatively referred to as "through vias" or "second through vias") BV and PADs (PADs, also referred to as "PADs") PAD (alternatively referred to as "metal PADs") PAD may be arranged in PAD region PR. Although fig. 4 shows that the PAD region PR has a large area, this is exaggerated to show the arrangement of the PAD and its surrounding backside via BV. According to some embodiments, the chip edge region may be arranged outside the pad region PR. In addition, a portion of a scribe lane (scribe line) may remain in the chip edge region.

The pixel isolation unit DTI (deep trench isolation (DTI)) may be formed in the first substrate 101 in the pixel array region APS and the light blocking region OB, thereby isolating the unit pixels UP from each other. As shown in fig. 5, the pixel isolation unit DTI may also be formed in the contact region BR1 and the backside via stack region BR2 of the peripheral region PE. The pixel isolation unit DTI may have a mesh shape in a plan view. The pixel isolation unit DTI may have a structure penetrating the first substrate 101 in the z-direction. Since the pixel isolation unit DTI has a structure passing through the first substrate 101, crosstalk due to obliquely incident light can be prevented.

The pixel isolation unit DTI may have a Front DTI (FDTI) structure extending from the front surface 101f to the rear surface 101b of the first substrate 101. According to some embodiments, the pixel isolation unit DTI may have a rear DTI (BDTI) structure extending from the rear surface 101b to the front surface 101f of the first substrate 101. For example, each of the FDTI and BDTI structures may be identified according to which of its width at the front surface 101f and its width at the rear surface 101b is greater. That is, the pixel isolation unit DTI may be formed by forming a trench in the first substrate 101 and then filling the inside of the trench with an insulating material and a conductive material. Accordingly, in the case of the FDTI structure obtained by digging the trench from the front surface 101f of the first substrate 101, the width of the trench at the front surface 101f of the first substrate 101 may be greater than the width of the trench at the rear surface 101b of the first substrate 101. In the case of the BDTI structure obtained by digging the trench from the rear surface 101b of the first substrate 101, the width of the trench at the rear surface 101b of the first substrate 101 may be greater than the width of the trench at the front surface 101f of the first substrate 101.

The pixel isolation unit DTI may include an insulating pattern 102, a side insulating layer 104, and a conductive pattern 106. The insulating pattern 102 may be disposed between the conductive pattern 106 and the first interlayer dielectric IL 1. The side insulating layer 104 may be disposed between the conductive pattern 106 and the first substrate 101 and between the insulating pattern 102 and the first substrate 101. The side insulating layer 104 may surround a peripheral portion of the conductive pattern 106 and insulate the conductive pattern 106 from the first substrate 101. The side insulating layer 104 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

Each of the insulating pattern 102 and the side insulating layer 104 may include an insulating material having a refractive index different from that of the first substrate 101. Each of the insulating pattern 102 and the side insulating layer 104 may include, for example, silicon oxide. The conductive pattern 106 may be separated from the first substrate 101 by the side insulating layer 104. The conductive pattern 106 may include polysilicon or silicon germanium doped with impurities. The impurity doped into the polysilicon or silicon germanium may include, for example, one of boron, phosphorus, and arsenic. According to some embodiments, the conductive pattern 106 may include a metal, a metal silicide, a metal-containing conductive material, or the like.

The photodiode PD may be doped with impurities of a second conductivity type opposite to the first conductivity type. For example, the second conductivity type may be N-type. The region doped with the N-type impurity may form a PN junction together with the first substrate 101 located therearound and doped with the P-type impurity, thereby constituting the photodiode PD.

A device isolation unit STI (shallow trench isolation (STI)) may be disposed adjacent to the front surface 101f of the first substrate 101. The device isolation unit STI may be pierced (penetrated) by the pixel isolation unit DTI. In some embodiments, the pixel isolation unit DTI may be in contact with the device isolation unit STI. The active region may be defined in the unit pixel UP by the device isolation unit STI. In the active region, transistors (i.e., TX, RX, DX, and SX) of the unit pixel UP may be arranged.

The transfer gate TG of the transfer transistor TX of the unit pixel UP may be disposed on the front surface 101f of the first substrate 101. The transfer gate TG may have a vertical gate structure in which a portion of the transfer gate TG extends to the inside of the first substrate 101. However, according to some embodiments, the transfer gate TG may have a planar gate structure in which the transfer gate TG is disposed only on the front surface 101f of the first substrate 101. The gate insulating film Gox may be disposed between the transfer gate TG and the first substrate 101. The floating diffusion region FD may be disposed at one side of the transfer gate TG in the first substrate 101. The floating diffusion region FD may be doped with, for example, an impurity of the second conductivity type.

The image sensor 1000 according to an embodiment may include an image sensor having a backside illumination (BSI) structure. The BSI structure may refer to a structure in which the color filters CF and the microlenses ML are disposed on or over the rear surface 101b of the first substrate 101 and the first wiring layer 130 is disposed on the front surface 101f of the first substrate 101. Thus, in the image sensor 1000 according to the embodiment, light may be incident on the photodiodes PD of the pixel array area APS through the rear surface 101b of the first substrate 101. Electron-hole pairs may be generated in the photodiode PD by light incident on the photodiode PD, and thus, electrons may be accumulated in the photodiode PD. When the transfer transistor TX is turned on, electrons accumulated in the photodiode PD may move to the floating diffusion region FD. For reference, there is a Front Side Illumination (FSI) structure opposite to the BSI structure, and the FSI structure may refer to a structure in which all of the color filters CF, the microlenses ML, and the first wiring layer 130 are disposed on or over the front surface 101f of the first substrate 101.

The first semiconductor chip CH1 may include a first wiring layer 130 disposed on the front surface 101f of the first substrate 101. The first wiring layer 130 may include a first interlayer dielectric IL1, a first wiring 132, and a first via contact 134. The first interlayer dielectric IL1 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous low-k material, and may have a multi-layered structure. The first wiring 132 may be disposed in the first interlayer dielectric IL 1. The first wiring 132 may have a multilayer structure corresponding to that of the first interlayer dielectric IL 1. Although not shown, the first wirings 132 in different layers may be connected to each other through the first via contacts 134 passing through at least a portion of the first interlayer dielectric IL 1. Further, the first wiring 132 may be connected to the floating diffusion FD and the transfer gate TG through a first via contact 134.

The anti-reflection layer 110 may be disposed on the rear surface 101b of the first substrate 101. The anti-reflection layer 110 may be disposed in the entire portions of the pixel region PA and the peripheral region PE. However, the embodiment is not limited thereto, and the anti-reflection layer 110 may not be disposed on the back contact BCA, the back via stack BVS, and the back via BV. The anti-reflection layer 110 may have a multi-layered structure and may include a TiO ₂ layer (see 114 of fig. 9B). The anti-reflection layer 110 may suppress reflection of incident light and increase the amount of light incident on the photodiode PD according to the thickness and refractive index of each layer of the anti-reflection layer 110. In the image sensor 1000 according to the embodiment, the anti-reflection layer 110 includes the TiO ₂ layer 114, thereby preventing stain defects that may be generated because the grid pattern (or referred to as "metal-free grid pattern") 120 does not include a metal layer. The multilayered structure of the anti-reflection layer 110 is described in more detail below with reference to fig. 9A to 9C.

The grid pattern 120 may be disposed on the anti-reflection layer 110 of the pixel array area APS. The grid pattern 120 may have a grid shape in a plan view, and may vertically overlap the pixel isolation unit DTI. The grid pattern 120 may have a uniform width and a uniform thickness, and may include an organic material or an inorganic material having a relatively low refractive index. Here, the width may refer to a width in an x-direction or a y-direction, and the thickness may refer to a thickness in a z-direction. In the image sensor 1000 according to the embodiment, the grid pattern 120 may have a low refractive index. For example, the grid pattern 120 may have a refractive index of 1.3 or less. However, the refractive index of the grid pattern 120 is not limited to the above numerical range. In the image sensor 1000 according to an embodiment, the grid pattern 120 may include tetraethyl orthosilicate (TEOS), PTEOS, or a porous low-k material. For example, TEOS may be formed by a plasma process at a temperature of 400 ℃ or less. Thus, TEOS formed by a plasma process is referred to as PE-TEOS or PTEOS.

For example, a relatively low refractive index and a relatively high refractive index may be determined based on a refractive index of around 1.5. For example, it is known that TiO ₂ having the highest refractive index among metal oxides may have an extremely high refractive index of 2.5 (in an anatase crystal structure) or 2.7 (in a rutile crystal structure). MgF ₂ may have a low refractive index of about 1.38. Further, mgF ₂ may have a refractive index that decreases with an increase in oblique incidence angle thereon, and may have an extremely low refractive index of about 1.2 at an oblique incidence angle of 80 ° due to the porous structure of MgF ₂.

The grid pattern 120 may include a single insulating layer structure. However, the embodiment is not limited thereto, and the grid pattern 120 may include a multi-insulating layer structure. In the image sensor 1000 according to an embodiment, the grid pattern 120 may not include a metal layer such as Ti/TiN. Accordingly, the grid pattern 120 does not include a metal layer, thereby preventing loss of Quantum Efficiency (QE) due to absorption of light by the metal layer. Accordingly, the QE of the image sensor 1000 can be improved.

CF1 and CF2 may be disposed inside the grids of the grid pattern 120 on the anti-reflection layer 110, respectively. For example, the color filters CF1 and CF2 may be isolated from each other by the grid pattern 120. Each of the color filters CF1 and CF2 may have one color among blue, green, and red, for example. In an embodiment, each of the color filters CF1 and CF2 may have a color combination such as cyan, magenta, or yellow. In the image sensor 1000 according to the embodiment, the color filters CF1 and CF2 may be arranged in a bayer pattern. However, the embodiment is not limited thereto, and the color filters CF1 and CF2 may be arranged in the form of a quad pattern having a2×2 array, a nine-element pattern having a 3×3 array, or a sixteen-element pattern having a 4×4 array. The grid pattern 120 may have a refractive index smaller than that of each of the color filters CF1 and CF 2. For example, the grid pattern 120 may have a refractive index of 1.3 or less. The grid pattern 120 may prevent crosstalk between adjacent unit pixels UP.

The light blocking layer OBL may be disposed on the anti-reflection layer 110 of the light blocking region OB of the first substrate 101. The light blocking layer OBL may block light from being incident on the photodiode PD' of the reference pixel formed in the first substrate 101 in the light blocking region OB. Each of the photodiodes PD' of the reference pixel may have the same structure as the photodiode PD formed in the pixel array area APS, but may not perform the same operation as the photodiode PD (i.e., an operation of generating an electrical signal according to the amount of light incident thereon). For example, since the photodiodes PD 'of the reference pixels are blocked, the photodiodes PD' of the reference pixels may each generate a dark level reference signal. The signal processor 700 of fig. 1 may compensate for a dark level of an output value of a pixel of the pixel array area APS by using a dark level reference signal.

The light blocking layer OBL may include a first conductive layer 152, a first insulating layer 156, and a second insulating layer 158. Furthermore, according to some embodiments, the light blocking layer OBL may further comprise an additional conductive layer between the first insulating layer 156 and the second insulating layer 158. A portion of the light incident on the light blocking layer OBL may pass through the first insulating layer 156 and the second insulating layer 158, and may be reflected or absorbed by the first conductive layer 152. A portion of the light reflected by the first conductive layer 152 may be absorbed by the first insulating layer 156. Furthermore, when the additional conductive layer is provided, the remaining portion of the light may be absorbed by the additional conductive layer. The first conductive layer 152 may absorb energy of light in the visible and near infrared bands due to a plasma phenomenon at the surface of the first conductive layer 152. Since the light reflected by the light blocking region OB is further minimized, degradation in quality of an image signal caused by a flash phenomenon that may occur in the image sensor 1000 can be further prevented.

A light blocking layer OBL may be disposed on the anti-reflection layer 110. A barrier metal layer for improving adhesion may be further disposed between the light blocking layer OBL and the anti-reflection layer 110. The barrier metal layer may include, for example, titanium (Ti) and/or titanium nitride (TiN). The first conductive layer 152 may have a relatively high thickness (e.g., a thickness of 100nm or more) to minimize transmittance of light incident thereon. The first conductive layer 152 may include a metal such as tungsten (W). The thickness of the first insulating layer 156 may be determined according to the wavelength of light to be absorbed. For example, when the image sensor 1000 is a device using RGB visible light, the thickness of the first insulating layer 156 may be smaller than that of the first insulating layer 156 of a device using infrared light. The first insulating layer 156 may include, for example, silicon oxide. The second insulating layer 158 may serve as an anti-reflection layer. Accordingly, the second insulating layer 158 may be formed to have a thickness less than or equal to a thickness corresponding to 1/4 of the wavelength of light intended to be absorbed. According to some embodiments, the second insulating layer 158 may be formed in a multi-layered structure, and may include hafnium oxide (HfO _x). The materials, thicknesses, etc. of the first conductive layer 152, the first insulating layer 156, and the second insulating layer 158 are not limited to the above materials or values, and various changes may be made according to some embodiments.

In the pixel array area APS, the height of the light blocking layer OBL from the anti-reflection layer 110 may be substantially equal to or less than the height of each of the color filters CF1 and CF2 from the anti-reflection layer 110. The step height between the light blocking layer OBL on the rear surface 101b of the first substrate 101 and each of the color filters CF1 and CF2 may be minimized to improve defects in a subsequent process, such as a process of forming the microlenses ML.

The backside contact BCA may be arranged in the contact area BR 1. The backside contact BCA may penetrate the anti-reflection layer 110 and may be disposed in the first groove T1 of the first substrate 101. The backside contact BCA may include a first conductive layer 152 and a first metal pattern 154a. A barrier metal layer may be further disposed under the first conductive layer 152. The first conductive layer 152 and the barrier metal layer may uniformly cover the side surfaces and the bottom surface of the first trench T1. The first metal pattern 154a may include, for example, aluminum (Al). However, the material of the first metal pattern 154a is not limited to Al. The first metal pattern 154a may fill the first trench T1. The back side contact BCA may be connected to the conductive pattern 106 of the pixel isolation unit DTI. The back side contact BCA may receive a specific voltage (e.g., a ground voltage or a negative voltage) applied thereto through the first conductive layer 152, and may apply the voltage to the conductive pattern 106 of the pixel isolation unit DTI. In this way, since the ground voltage or the negative voltage is applied to the conductive pattern 106 of the pixel isolation unit DTI through the back-side contact BCA, holes (i.e., positive holes) that may exist at the surface of the side insulating layer 104 of the pixel isolation unit DTI may be fixed, thereby improving dark current characteristics.

The backside via stack BVS may be arranged in a backside via stack region BR 2. The backside via stack BVS may be arranged in the first hole HO 1. The backside via stack BVS may extend in the z-direction in a structure that passes through the anti-reflective layer 110, the first substrate 101, and the first interlayer dielectric IL1 and partially passes through the second interlayer dielectric IL 2. In the backside via stack BVS, the first conductive layer 152 and the first insulating layer 156 of the light blocking layer OBL may uniformly cover the sidewalls and bottom surfaces of the first hole HO 1. The backside via stack BVS may electrically connect some of the first wirings 132 of the first semiconductor chip CH1 with some of the second wirings 172 of the second semiconductor chip CH 2. The first holes HO1 may be all filled with the protection pattern LRI. The protective pattern LRI may include a low refractive index material layer. In addition, the overlay pattern CFR may be disposed on the protection pattern LRI.

The PAD may be disposed in the PAD region PR. The PAD may be disposed in the second trench T2. The PAD may include a first conductive layer 152 and a second metal pattern 154b. For example, the anti-reflection layer 110 may be disposed on sidewalls and a bottom surface of the second trench T2. The first conductive layer 152 may uniformly cover the anti-reflection layer 110 in the second trench T2. The second metal pattern 154b may be disposed on the first conductive layer 152 and may fill the second trench T2. The second metal pattern 154b may include Al, for example. However, the material of the second metal pattern 154b is not limited to Al.

As can be seen from fig. 4, the backside vias BV may be arranged around the PAD. Similar to the backside via stack BVS, the backside via BV may penetrate the anti-reflective layer 110, the first substrate 101, and the first interlayer dielectric IL1, and partially penetrate the second interlayer dielectric IL2. The backside via BV may not be connected to the first wiring 132, but may be connected to some of the second wirings 172. The backside via BV may be connected to its corresponding PAD through the first conductive layer 152. That is, a signal input from outside the image sensor 1000 or output from the image sensor 1000 may be interfaced by the backside via BV and the PAD.

The microlenses ML may be disposed on the color filters CF1 and CF2 of the pixel array area APS, respectively. Edge portions of the microlenses ML can be in contact with and connected to each other. The microlenses ML may constitute an array. Thus, the microlenses ML can form a microlens array. One microlens ML may cover and correspond to one pixel. However, in some embodiments, one microlens ML may cover a plurality of pixels together. For example, when a plurality of pixels constitute one shared pixel, one microlens ML may cover the entire shared pixel.

The lens remaining layer MLR may be disposed on the light blocking layer OBL of the peripheral region PE. The lens remaining layer MLR may include the same material as the microlens ML. The lens coating layer MLC may cover the microlenses ML and the lens remaining layer MLR. In the PAD region PR, an opening OP may be formed through the lens remaining layer MLR and the lens coating layer MLC to expose the PAD.

The second semiconductor chip CH2 may include a second substrate 160 and a second wiring layer 170. The second semiconductor chip CH2 may be disposed under the first semiconductor chip CH1, and the second wiring layer 170 of the second semiconductor chip CH2 may be connected to the first wiring layer 130 of the first semiconductor chip CH 1. The transistor PTR for the logic device may be disposed in an upper portion of the second substrate 160. The transistors PTR for the logic devices may constitute circuit blocks (i.e., 200 to 700) of the image sensor 1000. In the second semiconductor chip CH2, the upper surface of the second substrate 160 may correspond to a front surface of the second substrate 160 as an active surface. The second wiring layer 170 may be disposed on the second substrate 160 and the transistor PTR. The second wiring layer 170 may include a second interlayer dielectric IL2, a second wiring 172, and a second via contact 174. The second interlayer dielectric IL2, the second wiring 172, and the second via contact 174 are the same as those described with respect to the first interlayer dielectric IL1, the first wiring 132, and the first via contact 134 of the first wiring layer 130, respectively.

In the image sensor 1000 according to the embodiment, the grid pattern 120 may not include a metal layer such as Ti/TiN or the like. For example, the grid pattern 120 may include only a single insulating layer having a relatively low refractive index. Accordingly, the image sensor 1000 according to the embodiment can prevent QE loss due to light absorption of the metal layer, and thus exhibit improved QE. Further, in the image sensor 1000 according to the embodiment, the anti-reflection layer 110 disposed under the color filters CF1 and CF2 and the grid pattern 120 may include the TiO ₂ layer 114, and the TiO ₂ layer 114 may serve as a charge path. Accordingly, the image sensor 1000 according to the embodiment may prevent stain defects that may be generated due to the grid pattern 120 not including the metal layer.

Fig. 6A is a graph showing the variation of the extinction coefficient (i.e., κ) of TiN with wavelength, and fig. 6B is a graph showing the variation of QE of each type of grid pattern with wavelength.

Referring to fig. 6A, in the case of TiN mainly used for the barrier metal layer, its extinction coefficient (i.e., κ) may increase with an increase in wavelength. Therefore, when TiN is included in the grid pattern as the barrier metal layer, QE loss due to the grid pattern may be generated, and particularly, there may be significant QE loss in long wavelengths.

Referring to fig. 6B, the change in QE with wavelength for a structure in which the grid pattern does not include a metal layer (i.e., a metal-free grid), a structure in which the grid pattern includes a barrier metal layer including TiN (i.e., a TiN grid), and a structure in which the grid pattern includes a barrier metal layer including Ti/TiN is shown. Further, the solid line shows the QE of the blue color filter, the broken line shows the QE of the green color filter, and the two-dot chain line shows the QE of the red color filter.

As can be seen by the graph in fig. 6B, the metal-free grid shows the highest QE over the entire wavelength. In particular, in the case of a blue color filter, the QE of the metal-free grid may be highest among short wavelengths based on blue, where the QE of the metal-free grid remains high, and may also be highest among medium and long wavelengths, where the QE of the metal-free grid remains low. These results are the same for the green and red filters. In summary, it is expected that QE of the image sensor can be improved by forming a grid pattern excluding the metal layer.

For example, in an image sensor, a grid pattern between color filters is introduced for the purpose of pixel isolation, and has an effect of reducing crosstalk. However, when a metal layer exists in the grid pattern, there is a loss of QE due to light absorption of the metal layer. Therefore, the material that has been developed to the grid pattern changes from W to a Low Refractive Index (LRI) material, and the barrier metal layer in the lower portion of the grid pattern includes only TiN obtained by removing Ti from the Ti/TiN combination. However, as can be seen from the graph of fig. 6A, the barrier metal layer comprising TiN may also still cause a loss of QE due to light absorption.

However, the image sensor 1000 according to the embodiment may include the metal-free grid pattern 120 by omitting the barrier metal layer. In general, in order not to generate stain defects in an image sensor, it is necessary to secure a charge path when static electricity is generated. When the barrier metal layer is omitted from the grid pattern, a stain defect may be generated because there is no charge path. However, in the image sensor 1000 according to the embodiment, the anti-reflection layer 110 may include the TiO ₂ layer 114, and the TiO ₂ layer 114 may serve as a charge path. Therefore, the image sensor 1000 according to the embodiment can effectively prevent stain defects even though the grid pattern 120 does not include a metal layer.

Fig. 7A and 7B are conceptual diagrams showing loss and improvement of QE in the image sensor of the related example and the image sensor according to the embodiment, respectively.

Referring to fig. 7A and 7B, in the image sensor com of the related example of fig. 7A, the grid pattern GP may include a barrier metal layer including TiN. Accordingly, in the region corresponding to the red color filter (i.e., CF), a portion of the light L having a size larger than that of the red color filter (i.e., CF) may be absorbed by the barrier metal layer of the grid pattern GP, and thus, there may be a loss of QE. For reference, in fig. 7A and 7B, the first quadrant may correspond to the red color filter (i.e., CF), the second and fourth quadrants may correspond to the green color filter (i.e., CF), and the third quadrant may correspond to the blue color filter (i.e., CF). In the image sensor 1000 according to the embodiment in fig. 7B, the grid pattern 120 may not include a metal layer. Accordingly, in the region corresponding to the red color filter (i.e., CF), a portion of the light L having a size larger than that of the red color filter (i.e., CF) may not be absorbed by the grid pattern 120 and may be incident to the inside of the pixel (i.e., photodiode PD), and thus QE may be improved.

Fig. 8A and 8B are cross-sectional views showing the grid pattern structure of the image sensor of the related example and the image sensor according to the embodiment, respectively. Fig. 9A is an enlarged cross-sectional view of a region A1 of fig. 8A, fig. 9B is an enlarged cross-sectional view of a region A2 of fig. 8B, and fig. 9C is a cross-sectional view showing an antireflection layer of a node isolation portion of an image sensor according to an embodiment.

Referring to fig. 8A and 9A, in the image sensor com of the related example, the grid pattern GP of the pixel array region APS may include a barrier metal layer BM and a grid insulation layer GL. The barrier metal layer BM may comprise, for example, ti/TiN or TiN. The grid insulating layer GL may include an insulating layer having a low refractive index. For example, the grid insulation layer GL may include TEOS or PTEOS. In the case of the image sensor com of the related example, since the grid pattern GP includes the barrier metal layer BM, there may be a loss of QE as described above.

In the image sensor com of the related example, the anti-reflection layer ARL may include four layers L1, L2, L3, and L4 stacked in the stated order on the rear surface of the first substrate 101. For example, the antireflective layer ARL may include an AlO layer (i.e., L1), a first HfO _x layer (i.e., L2), a PTEOS layer (i.e., L3), and a second HfO _x layer (i.e., L4). In addition, the four layers L1 through L4 may each have aboutTo aboutAboutTo aboutAboutTo aboutAboutTo aboutIs a thickness of (c). The second HfO _x layer (i.e., L4) may serve as an etch stop layer when the grid pattern GP on the second HfO _x layer (i.e., L4) is etched. That is, the second HfO _x layer (i.e., L4) may function as an etch stop layer with respect to the barrier metal layer BM of the grid pattern GP.

Referring to fig. 8B, 9B and 9C, in the image sensor 1000 according to the embodiment, the grid pattern 120 of the pixel array area APS may include a single insulating layer. For example, the grid pattern 120 may not include a metal layer such as a barrier metal layer. The grid pattern 120 may include an insulating layer having a low refractive index. For example, the grid pattern 120 may include TEOS, PTESO, or a porous low-k material. However, the material of the grid pattern 120 is not limited to the above-described material.

In the image sensor 1000 according to the embodiment, since the grid pattern 120 includes a single insulating layer, the anti-reflection layer 110 may include the AlO layer 112, the TiO ₂ layer 114, the PTEOS layer 116, and the HfO _x layer 118 stacked on the rear surface of the first substrate 101 in the stated order. The AlO layer 112, tiO ₂ layer 114, PTEOS layer 116, and HfO _x layer 118 may each have aboutTo aboutAboutTo aboutAboutTo aboutAnd about (f)To aboutIs a thickness of (c). However, the respective thicknesses of the AlO layer 112, the TiO ₂ layer 114, the PTEOS layer 116, and the HfO _x layer 118 are not limited to the above numerical ranges. The HfO _x layer 118 may be used as an etch stop layer when etching the grid pattern 120 on the HfO _x layer 118.

In the image sensor 1000 according to the embodiment, the grid pattern 120 may not include a metal layer. Further, the anti-reflection layer 110 may include the TiO ₂ layer 114 instead of the first HfO _x layer L2 in the image sensor com of the related example. In this way, since the grid pattern 120 does not include a metal layer, QE of the image sensor 1000 can be improved. In addition, since the anti-reflection layer 110 includes the TiO ₂ layer 114, a charge path can be ensured, thereby preventing stain defects of the image sensor 1000. In addition, because the TiO ₂ layer 114 is formed to be aboutTo aboutThe total thickness of the anti-reflection layer 110 can be reduced by about as compared with the anti-reflection layer ARL of the image sensor com of the related exampleTo aboutFurther, as seen in fig. 8A, in the image sensor com of the related example, due to the presence of the barrier metal layer BM, the distance between the lower surface of the grid insulating layer GL and the upper surface of the anti-reflection layer ARL may be greater than the distance between the lower surface of the color filter CF and the upper surface of the anti-reflection layer ARL. As can be seen in fig. 8B, in the image sensor 1000 according to the embodiment, the distance between the lower surface of the grid pattern 120 and the upper surface of the anti-reflection layer 110 may be substantially equal to the distance between the lower surface of the color filter CF and the upper surface of the anti-reflection layer 110. Further, in an embodiment, the lower surface of the grid pattern 120 and the lower surface of the color filter CF may be in substantially the same plane.

Because the anti-reflective layer 110 includes the conductive TiO ₂ layer 114, the TiO ₂ layer 114 may break the connection in areas where node isolation is desired. Fig. 9C shows a structure in which the TiO ₂ layer 114 is disconnected at the node-isolated portion NDA. Since the TiO ₂ layer 114 of the anti-reflection layer 110 is disconnected at the node-isolating portion NDA, the groove G may be formed in the node-isolating portion NDA. For example, as shown in fig. 9C, in the node-isolated portion NDA where the TiO ₂ layer 114 is disconnected, since the PTEOS layer 116 and the HfO _x layer 118 disposed on or over the TiO ₂ layer 114 are continuously formed with a uniform thickness without interruption, the groove G may be formed in the node-isolated portion NDA. Hereinafter, in fig. 10A to 12B, various node isolation portions NDA of the TiO ₂ layer 114 disconnected are shown.

Fig. 10A to 12B illustrate plan views of node-isolated portions of the anti-reflection layer 110 of fig. 9C in respective positions of the image sensor 1000 of fig. 1, and cross-sectional views corresponding to the plan views.

Referring to fig. 10A and 10B, the node isolation portion NDA in the pad region PR of the peripheral region PE is shown. The node isolation portion NDA may be arranged in a structure surrounding the backside via BV. For example, as shown in fig. 4 and 10A, the backside vias BV may be arranged linearly on both sides of the PAD. Further, the node isolation portion NDA may have a structure surrounding each backside via BV arranged linearly, as shown by a double-dashed line of a rectangular shape. For example, in fig. 10A to 12B, the first insulating layer 156, the second insulating layer 158, and the like disposed on or over the first conductive layer 152 are omitted and not illustrated.

Referring to fig. 11A and 11B, the node isolation portion NDA in the backside via stack area BR2 is shown. The node isolation portion NDA may be adjacent to and surround the backside via stack BVS. For example, as shown in fig. 11A, the backside via stacks BVS may be arranged in a two-dimensional array structure in a backside via stack region BR 2. Further, the node isolation portion NDA may surround the backside via stack BVS while having a grid shape as shown by a double dashed line.

Referring to fig. 12A and 12B, the node isolation portion NDA in the contact region BR1 outside the pixel region PA is shown. The node isolating portion NDA may be disposed at both sides of the backside contact BCA. For example, as shown in fig. 12A, the back-side contacts BCA may be arranged around the light blocking area OB at certain intervals along a line surrounding the light blocking area OB. Further, the node isolating portion NDA may linearly extend at both sides of the backside contacts BCA to surround each of the backside contacts BCA as shown by double-dashed lines.

Fig. 13A to 13K are cross-sectional views respectively showing a series of processes of a method of manufacturing an image sensor according to an embodiment. The description is described with reference to fig. 13A to 13K together with fig. 4 and 5, and the description that has been given with reference to fig. 1 to 12B is simplified or omitted.

Referring to fig. 13A, a first semiconductor chip CH1 is manufactured according to a method of manufacturing an image sensor according to an embodiment. For example, a device isolation unit STI, a pixel isolation unit DTI, and a photodiode PD are formed in the first substrate 101 including the pixel region PA and the peripheral region PE. The device isolation unit STI may define an active area, and the pixel isolation unit DTI may define an area of the unit pixel UP. The photodiode PD may be formed by performing an ion implantation process or the like. Next, a pixel transistor constituting the unit pixel UP is formed in the active region. Then, the first wiring layer 130 is formed on the front surface 101f of the first substrate 101. The first wiring layer 130 may include a first interlayer dielectric IL1, a first wiring 132, and a first via contact 134.

The second semiconductor chip CH2 is manufactured in parallel with the manufacture of the first semiconductor chip CH 1. The second semiconductor chip CH2 may include a second substrate 160 and a second wiring layer 170. A transistor PTR for a logic device may be disposed in the second substrate 160. A second wiring layer 170 may be disposed on an active surface (i.e., a front surface) of the second substrate 160, and the second wiring layer 170 may include a second interlayer dielectric IL2, a second wiring 172, and a second via contact 174.

Referring to fig. 13B, after the first semiconductor chip CH1 and the second semiconductor chip CH2 are manufactured, the first interlayer dielectric IL1 is aligned with the second interlayer dielectric IL2, and then a thermal compression process or the like is performed, thereby bonding and bonding the first semiconductor chip CH1 to the second semiconductor chip CH 2.

Referring to fig. 13C, as indicated by thick arrows, a polishing process is performed on the rear surface 101b of the first substrate 101, thereby reducing the thickness of the first substrate 101. The conductive pattern 106 of the pixel isolation unit DTI may be exposed through a grinding process. In some embodiments, the side insulating layer 104 of the pixel isolation unit DTI may be exposed through a grinding process. The process of thinning the first substrate 101 may further include a Chemical Mechanical Polishing (CMP) process. In such a CMP process, the conductive pattern 106 of the pixel isolation unit DTI may be used as an etch stop layer, or the side insulating layer 104 of the pixel isolation unit DTI may be used as an etch stop layer.

Referring to fig. 13D, in the pad region PR of the peripheral region PE, in order to form a pad on the rear surface 101b of the first substrate 101, a second trench T2 is formed in the pad region PR in the first substrate 101 by etching a portion of the first substrate 101. Next, an anti-reflection layer 110 including a plurality of layers is formed. For example, the anti-reflection layer 110 may include an AlO layer 112, a TiO ₂ layer 114, a PTEOS layer 116, and a HfO _x layer 118 stacked in the stated order on the rear surface 101b of the first substrate 101. Each of the plurality of layers of the anti-reflection layer 110 may be formed by Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or the like. When the anti-reflection layer 110 is formed, as described with reference to fig. 9C to 12B, the node-isolated portion NDA where the TiO ₂ layer 114 is disconnected may be formed.

Next, in the contact region BR1, a first trench T1 is formed by etching a specific portion of the anti-reflection layer 110 and the first substrate 101. When the first trench T1 is formed, the pixel isolation unit DTI may be partially etched, and thus, the conductive pattern 106 of the pixel isolation unit DTI may be exposed. Further, in the backside via stack region BR2, the anti-reflection layer 110, the first substrate 101, the first interlayer dielectric IL1, and the second interlayer dielectric IL2 are partially etched, thereby forming a first hole HO1 for forming the backside via stack BVS. As shown in fig. 4, when the first hole HO1 is formed, a second hole for forming the backside via BV may also be formed around the second trench T2 of the pad region PR.

Referring to fig. 13E to 13G, in the pixel region PA and the peripheral region PE, a first conductive layer 152 and a second conductive layer 154 are formed in stated order on the rear surface 101b of the first substrate 101. For example, the first conductive layer 152 may include W, and the second conductive layer 154 may include Al. However, the materials of the first conductive layer 152 and the second conductive layer 154 are not limited to the above materials. Next, the second conductive layer 154 is left only in the trenches (i.e., T1) of the contact region BR1 and the trenches (i.e., T2) of the pad region PR by an etching process, thereby forming the first and second metal patterns 154a and 154b. In some embodiments, a barrier metal layer including Ti may be further formed under the first conductive layer 152. In addition, a barrier metal layer including TiN may be formed on the second conductive layer 154 and under the second conductive layer 154. The first conductive layer 152 and the first metal pattern 154a may constitute a backside contact BCA, and the first conductive layer 152 and the second metal pattern 154b may constitute a PAD.

Referring to fig. 13H, a first insulating layer 156 is formed in the pixel region PA and the peripheral region PE. Here, the first insulating layer 156 may also be formed in the first hole HO1 of the backside via stack region BR 2. Further, although not shown, the first insulating layer 156 may be formed in the second hole for the backside via BV. For example, the first insulating layer 156 may include, for example, silicon oxide.

Referring to fig. 13I, the first conductive layer 152 and the first insulating layer 156 formed in the pixel array area APS are removed.

Referring to fig. 13J, a grid pattern 120 is formed in the pixel array area APS. The grid pattern 120 may include a single insulating layer having a low refractive index. A low refractive index material layer may be formed on the structure on the rear surface 101b of the first substrate 101 and then patterned in the pixel array area APS by a patterning process, thereby forming the grid pattern 120. When the grid pattern 120 is formed, the low refractive index material layer may fill the inside of the first hole HO1, thereby constituting the protective pattern LRI. Next, a second insulating layer 158 may be formed in the light blocking region OB and the peripheral region PE. The first conductive layer 152, the first insulating layer 156, and the second insulating layer 158 may constitute a light blocking layer OBL. In addition, the capping pattern CFR may be formed in the upper portion of the first hole HO1 by using a negative photoresist before the second insulating layer 158 is formed, thereby forming the backside via stack BVS. Referring to fig. 13K, next, in order to electrically block the PAD of the PAD region PR and the backside via stack BVS of the backside via stack region BR2 from each other, a blocking groove BG is formed by removing the first conductive layer 152, the first insulating layer 156, and the second insulating layer 158 in the PAD region PR. In addition, in order to electrically block the backside contact BCA of the contact region BR1 and the backside via stack BVS of the backside via stack region BR2 from each other, a blocking groove BG may be formed by removing the first conductive layer 152, the first insulating layer 156, and the second insulating layer 158 in the backside via stack region BR 2.

Referring back to fig. 5, color filters CF1 and CF2 are successively formed in the pixel array area APS. The color filters may not be formed in the light blocking region OB and the peripheral region PE. The color filters CF1 and CF2 may each fill the inside of the grid pattern 120, and may be separated from each other by the grid pattern 120. In the image sensor 1000 according to the embodiment, the color filters CF1 and CF2 may each have one color among blue, green, and red, for example. Further, the color filters CF1 and CF2 may be arranged in a bayer pattern. However, the color combinations and pattern shapes of the color filters CF1 and CF2 are not limited to the above examples.

Next, a material layer for microlenses is coated to cover the structures on the rear surface 101b of the first substrate 101, and then microlenses ML are formed in the pixel array area APS and a lens remaining layer MLR is formed in other areas. Further, in the PAD region PR, the lens remaining layer MLR, the second insulating layer 158, the first insulating layer 156, and the like may be removed, and thus, an opening OP may be formed to expose the PAD, thereby manufacturing the image sensor 1000 of fig. 5.

Fig. 14A and 14B are cross-sectional views showing a process of forming a grid pattern in the image sensor of the related example and the image sensor of the embodiment, respectively. Description is made with reference to fig. 14A and 14B and fig. 8A and 8B.

Referring to fig. 14A, in the case of the image sensor com of the related example, as shown in fig. 8A, the grid pattern GP may include a barrier metal layer BM at a lower portion thereof. Accordingly, in order to form the grid pattern GP, a lower metal layer BMl and an upper insulating layer GLl are formed on the anti-reflection layer ARL. The lower metal layer BMl may comprise, for example, a TiN layer and the upper insulating layer GLl may comprise a low refractive index material, such as TEOS or PTEOS.

Next, a hard mask HM is formed on the upper insulating layer GLl by a photolithography process. According to some embodiments, a Photoresist (PR) pattern may remain on the hard mask HM. Next, the lower metal layer BMl and the upper insulating layer GLl are etched by using the hard mask HM as an etching mask, thereby forming the grid insulating layer GL and the barrier metal layer BM. The second HfO _x layer L4 of the anti-reflection layer ARL may be used as an etch stop layer in the etching process.

Referring to fig. 14B, in the case of the image sensor 1000 according to the embodiment, as shown in fig. 8B, the grid pattern 120 may include a single insulating layer without a separate barrier metal layer at a lower portion thereof. Accordingly, in order to form the grid pattern 120, a low refractive index material layer 120a is formed on the anti-reflection layer 110. The low refractive index material layer 120a may include, for example, TEOS, PTEOS, porous low-k material, etc. However, the material of the low refractive index material layer 120a is not limited to the above-described material.

Next, a hard mask 1500 is formed on the low refractive index material layer 120a through a photolithography process. According to some embodiments, the PR pattern may remain on the hard mask 1500. Next, the low refractive index material layer 120a is etched by using the hard mask 1500 as an etching mask, thereby forming the grid pattern 120. The HfO _x layer 118 of the anti-reflective layer 110 may be used as an etch stop layer in an etching process.

While the embodiments have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. An image sensor, the image sensor comprising:

a first substrate including a pixel region and a peripheral region adjacent to the pixel region, the pixel region including a plurality of pixels in a two-dimensional array;

a first wiring layer on a lower surface of the first substrate;

an anti-reflection layer having a first refractive index, the anti-reflection layer being on an upper surface of the first substrate; and

The color filters correspond to the pixel regions on the anti-reflection layer and are spaced apart from each other by a metal-free grid pattern.

2. The image sensor of claim 1, wherein the color filters correspond to the plurality of pixels in a two-dimensional array,

Wherein the metal-free grid pattern has a two-dimensional grid shape and is between the color filters, and

Wherein the metal-free grid pattern includes a single insulating layer having a second refractive index lower than the first refractive index.

3. The image sensor of claim 1, wherein the anti-reflective layer comprises a TiO ₂ layer.

4. The image sensor of claim 3, wherein the TiO ₂ layer is disconnected at the node-isolated portion.

5. The image sensor of claim 4, further comprising:

A back side contact linearly disposed at a certain interval along a line surrounding a peripheral portion of the pixel region,

Wherein the node isolation portion extends along the line on both sides of the backside contact.

6. The image sensor of claim 4, further comprising: a first through hole in a two-dimensional array over a portion of the peripheral region,

Wherein the node isolation portion is adjacent to each of the first through holes in a two-dimensional grid shape.

7. The image sensor of claim 4, further comprising: a second through via adjacent to and on at least one side of each of the metal pads in a peripheral portion of the peripheral region,

Wherein the node isolation portion is adjacent to each of the second through vias.

8. The image sensor of claim 3, wherein the anti-reflective layer further comprises an AlO layer below the TiO ₂ layer, and a tetraethyl orthosilicate layer and a HfO _x layer above the TiO ₂ layer, and

Wherein the TiO ₂ layer is disconnected in the node isolating portion, and

Wherein the AlO layer, the tetraethyl orthosilicate layer and the HfO _x layer all extend continuously in the node-isolated portion.

9. The image sensor of claim 1, wherein a distance between a lower surface of the metal-free grid pattern and an upper surface of the anti-reflection layer is equal to a distance between a lower surface of each of the color filters and an upper surface of the anti-reflection layer.

10. An image sensor, the image sensor comprising:

The first semiconductor chip comprises a first substrate and a first wiring layer, wherein the first substrate comprises a pixel area and a peripheral area adjacent to the pixel area, the first wiring layer is arranged on the lower surface of the first substrate, and a plurality of pixels are in a two-dimensional array structure in the pixel area; and

A second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second substrate including logic devices and a second wiring layer on an upper surface of the second substrate,

Wherein an anti-reflection layer including a TiO ₂ layer is on the upper surface of the first substrate,

Wherein the color filter has a two-dimensional array structure on the anti-reflection layer of the pixel region, and

Wherein the color filters are spaced apart from each other by a metal-free grid pattern having a two-dimensional grid shape.

11. The image sensor of claim 10, wherein the metal-free grid pattern comprises a single insulating layer having a first refractive index.

12. The image sensor of claim 10, wherein the TiO ₂ layer is disconnected at the node-isolated portion.

13. The image sensor of claim 12, wherein the node isolation portion is adjacent to:

Each of the back side contacts disposed linearly adjacent to the peripheral portion of the pixel region at a certain interval;

Each of the first through holes in a two-dimensional array structure in a portion of the peripheral region; and

A second through via adjacent to and on at least one side of each of the metal pads in the peripheral portion of the peripheral region.

14. The image sensor of claim 10 wherein the anti-reflective layer further comprises an AlO layer below the TiO ₂ layer, and a tetraethyl orthosilicate layer and a HfO _x layer above the TiO ₂ layer,

Wherein the TiO ₂ layer is disconnected in the node isolating portion, and

15. An image sensor, the image sensor comprising:

The first substrate comprises a pixel area and a peripheral area adjacent to the pixel area, wherein a plurality of pixels are in a two-dimensional array structure in the pixel area;

a first wiring layer on a lower surface of the first substrate;

An anti-reflection layer on an upper surface of the first substrate and including a TiO ₂ layer;

a color filter having a two-dimensional array structure on the anti-reflection layer of the pixel region;

a grid pattern on the anti-reflection layer of the pixel region and separating the color filters from each other in a two-dimensional grid shape, the grid pattern including a single insulating layer having a low refractive index and no metal;

a microlens on the color filter and the grid pattern;

a second wiring layer under the first wiring layer; and

And a second substrate under the second wiring layer.

16. The image sensor of claim 15, wherein the TiO ₂ layer is disconnected at the node-isolated portion, and

Wherein the node isolation portion is disposed adjacent to:

17. A method of manufacturing an image sensor, the method comprising the steps of:

Forming a plurality of pixels each including a photodiode in a pixel region of a first substrate of a first semiconductor chip, and forming a first wiring layer on an active surface of the first substrate;

forming a logic device in a second substrate of the second semiconductor chip, and forming a second wiring layer on an active surface of the second substrate;

connecting the first semiconductor chip and the second semiconductor chip to each other such that the first wiring layer faces the second wiring layer;

Removing a portion of the passive surface of the first substrate;

Forming an anti-reflection layer having a first refractive index on a passive surface of a first substrate;

Forming a through hole in a peripheral region of the first substrate, the peripheral region of the first substrate being adjacent to the pixel region;

Forming color filters corresponding to the plurality of pixels, respectively, on the anti-reflection layer of the pixel region; and

Microlenses are formed on the color filters respectively,

Wherein the step of forming the color filter includes:

Forming a metal-free grid pattern having a two-dimensional grid shape in the pixel region; and

Color filters are respectively formed in grids without metal grid patterns.

18. The method of claim 17, wherein the metal-free grid pattern comprises a single insulating layer having a second refractive index lower than the first refractive index, and

Wherein the anti-reflection layer comprises a TiO ₂ layer.

19. The method of claim 18, wherein the anti-reflective layer further comprises an AlO layer below the TiO ₂ layer, and a tetraethyl orthosilicate layer and a HfO _x layer above the TiO ₂ layer, and

Wherein the HfO _x layer serves as an etch stop layer when patterning the single insulating layer.

20. The method of claim 19, wherein in the step of forming the anti-reflection layer, a node isolating portion in which the TiO ₂ layer is disconnected is formed adjacent to: