CN118398602B - Semiconductor test structure and test method thereof - Google Patents
Semiconductor test structure and test method thereof Download PDFInfo
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- CN118398602B CN118398602B CN202410764741.0A CN202410764741A CN118398602B CN 118398602 B CN118398602 B CN 118398602B CN 202410764741 A CN202410764741 A CN 202410764741A CN 118398602 B CN118398602 B CN 118398602B
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- 238000012360 testing method Methods 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000010998 test method Methods 0.000 title abstract description 7
- 239000003990 capacitor Substances 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 231
- 239000002184 metal Substances 0.000 claims description 127
- 229910052751 metal Inorganic materials 0.000 claims description 127
- 239000011229 interlayer Substances 0.000 claims description 42
- 230000015556 catabolic process Effects 0.000 claims description 26
- 230000002159 abnormal effect Effects 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 208000037909 invasive meningococcal disease Diseases 0.000 description 2
- 101100084902 Mus musculus Psmd14 gene Proteins 0.000 description 1
- 101150057849 Padi1 gene Proteins 0.000 description 1
- 101150092599 Padi2 gene Proteins 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a semiconductor test structure and a test method thereof.A first enclosing wall structure of the semiconductor test structure is arranged on the outer side of a second bonding pad structure in an insulating manner, the second enclosing wall structure is arranged on the outer side of a third bonding pad structure in an insulating manner, the second bonding pad structure and the third bonding pad structure are electrically connected through a capacitor, the first bonding pad structure is electrically connected with the first enclosing wall structure, the first enclosing wall structure is electrically connected with the third bonding pad structure through a first resistor, the second enclosing wall structure is electrically connected with a fourth bonding pad structure, and the second enclosing wall structure is electrically connected with the second bonding pad structure through a second resistor; and when the TDDB is tested, one of the second bonding pad structure and the third bonding pad structure is grounded, one of the second bonding pad structure and the third bonding pad structure is applied with voltage, and whether the IMD breaks down normally or not is determined according to the resistance between the first bonding pad structure and the second bonding pad structure, so that a semiconductor test structure damage sample caused by the TDDB test or the packaging reason is effectively removed, and the TDDB test accuracy of the IMD is greatly improved.
Description
Technical Field
The present invention relates to the field of semiconductor testing, and in particular, to a semiconductor testing structure and a testing method thereof.
Background
In BEOL (back end of line), IMD (Inter-METALDIELECTRIC, inter-layer dielectric) is limited by material, so that toughness is poor, especially when copper, which is a metal material selected in advanced semiconductor manufacturing, is matched with Low-K dielectric layer (Low-K), damage is easily generated when the copper is stressed. Thus, the characteristics of IMDs present some challenges for reliability testing.
TDDB (TIME DEPENDENT DIELECTRIC break down) of an IMD is a common item for process reliability evaluation of IMDs. The items can be classified into WLR (WAFER LEVEL reliability) test and PLR (Package-Level Reliability) test, as shown in fig. 1, both ends of the test structure are connected to corresponding pads (pads), respectively, and TDDB test is performed at high temperature. The WLR test probe generates thermal expansion under the condition of high-temperature long-time baking, extrudes the IMD and generates a crack (crack), thereby affecting the test structure; the PLR test is to wire-bond the package first and thermally press-connect the gold wire to the bonding pad, and when the pressure is too high, it is easy to squeeze the IMD and generate a ack, thereby affecting the test accuracy of the test structure.
Disclosure of Invention
The invention aims to provide a semiconductor test structure and a test method thereof, which can improve the accuracy of TDDB test of an IMD.
The invention provides a semiconductor test structure, which comprises a capacitor, a first resistor, a second resistor, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a fourth bonding pad structure, a first enclosing wall structure and a second enclosing wall structure, wherein the first enclosing wall structure is arranged on the outer side of the second bonding pad structure in an insulating manner, the second enclosing wall structure is arranged on the outer side of the third bonding pad structure in an insulating manner, the second bonding pad structure and the third bonding pad structure are electrically connected through the capacitor, the first bonding pad structure and the first enclosing wall structure are electrically connected through the first resistor and the third bonding pad structure, the second enclosing wall structure and the fourth bonding pad structure are electrically connected through the second resistor, and the second enclosing wall structure is electrically connected with the second bonding pad structure through the second resistor;
and in the TDDB test, applying a voltage to the second pad structure, wherein the third pad structure is grounded, or the second pad structure is grounded, applying a voltage to the third pad structure, and determining whether an interlayer dielectric layer is normally broken down according to the resistance between the first pad structure and the second pad structure and the resistance between the third pad structure and the fourth pad structure.
Optionally, the interval between the first enclosing wall structure and the second bonding pad structure is equal to the interval between the second enclosing wall structure and the third bonding pad structure, and the interval is 0.045 μm-0.2 μm.
Optionally, the first enclosure structure and the second enclosure structure are ring structures with two notches, so as to realize the electrical connection of the second pad structure and the electrical connection of the third pad structure at the two notches, and the first enclosure structure and the second enclosure structure are respectively and electrically connected below the respective notches.
Optionally, when the semiconductor test structure is used for performing TDDB test on the horizontal interlayer dielectric layer of the metal interconnection structure, the first pad structure, the second pad structure, the third pad structure and the fourth pad structure all include a current layer metal layer and an extraction pad layer which are sequentially arranged from bottom to top, all the current layer metal layers are arranged in the same layer, the extraction pad layer is located on the surface of the interlayer dielectric layer, the current layer metal layer and the extraction pad layer are electrically connected through conductive through holes, the first enclosure structure surrounds the current layer metal layer of the second pad structure, and the second enclosure structure surrounds the current layer metal layer of the third pad structure.
Optionally, when the semiconductor test structure is used for TDDB testing of an interlayer dielectric layer between adjacent metal layers, the first pad structure, the second pad structure, the third pad structure and the fourth pad structure each include a first current layer metal layer, a second current layer metal layer and a lead-out pad layer which are sequentially arranged from bottom to top, the first current layer metal layer and the second current layer metal layer are spaced along the thickness direction and are embedded in the interlayer dielectric layer in an insulating manner, the lead-out pad layer is located on the surface of the interlayer dielectric layer, and the first current layer metal layer, the second current layer metal layer and the lead-out pad layer are sequentially electrically connected through conductive vias;
The first enclosure structure and the second enclosure structure are respectively provided with a first sub-enclosure and a second sub-enclosure which are sequentially arranged from bottom to top, all the first metal layers on the current layer and all the first sub-enclosures are arranged on the same layer, all the second metal layers on the current layer and all the second sub-enclosures are arranged on the same layer, the first sub-enclosures of the first enclosure structure are arranged on the outer side of the first metal layers on the current layer of the second bonding pad structure at intervals in an insulating manner, and the second sub-enclosures of the first enclosure structure are arranged on the outer side of the second metal layers on the current layer of the second bonding pad structure at intervals in an insulating manner; the first sub-enclosing walls of the second enclosing wall structure are arranged at intervals and in an insulating manner on the outer side of the first metal layer of the third bonding pad structure, and the second sub-enclosing walls of the second enclosing wall structure are arranged at intervals and in an insulating manner on the outer side of the second metal layer of the third bonding pad structure.
Optionally, the resistances of the first resistor and the second resistor are the same, and are kilo-ohm resistors.
Further, the first resistor and the second resistor are kilo-ohm resistors.
On the other hand, the invention also provides a testing method of the semiconductor testing structure, which comprises the following steps:
Applying a voltage to the second pad structure, the third pad structure being grounded, or the second pad structure being grounded, applying a voltage to the third pad structure for TDDB testing;
And when breakdown is detected, measuring the resistance between the first pad structure and the second pad structure and the resistance between the third pad structure and the fourth pad structure to determine whether the interlayer dielectric layer is in normal breakdown.
Optionally, in measuring the resistance between the first pad structure and the second pad structure,
If the resistance between the first bonding pad structure and the second bonding pad structure tends to 0, judging that abnormal breakdown occurs in an interlayer dielectric layer between the first enclosing wall structure and the second bonding pad structure;
and if the resistance between the first bonding pad structure and the second bonding pad structure is equal to the resistance of the first resistance, judging that the interlayer dielectric layer is in normal breakdown.
Optionally, in measuring the resistance between the third pad structure and the fourth pad structure,
If the resistance between the third bonding pad structure and the second bonding pad structure tends to 0, judging that abnormal breakdown occurs in the interlayer dielectric layer between the second enclosing wall structure and the third bonding pad structure;
And if the resistance between the third pad structure and the second pad structure is equal to the resistance of the second resistance, judging that the interlayer dielectric layer is in normal breakdown.
Compared with the prior art, the invention has the following unexpected technical effects:
The invention provides a semiconductor test structure and a test method thereof, wherein the semiconductor test structure comprises a capacitor, a first resistor, a second resistor, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a fourth bonding pad structure, a first enclosing wall structure and a second enclosing wall structure, wherein the first enclosing wall structure is arranged on the outer side of the second bonding pad structure in an insulating manner, the second enclosing wall structure is arranged on the outer side of the third bonding pad structure in an insulating manner, the second bonding pad structure and the third bonding pad structure are electrically connected through the capacitor, the first bonding pad structure and the first enclosing wall structure are electrically connected through the first resistor, the second enclosing wall structure and the fourth bonding pad structure are electrically connected, and the second enclosing wall structure is electrically connected through the second resistor and the second bonding pad structure; in the TDDB test, a voltage is applied to the second pad structure, the third pad structure is grounded, or the second pad structure is grounded, a voltage is applied to the third pad structure, and whether the interlayer dielectric layer is normally broken down is determined according to the resistance between the first pad structure and the second pad structure, and the resistance between the third pad structure and the fourth pad structure, which achieves the unexpected technical effects that: the damage sample of the semiconductor test structure caused by TDDB test or package reasons can be effectively removed, and the TDDB test accuracy of the IMD is greatly improved.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor test structure.
Fig. 2 is a schematic structural diagram of a semiconductor test structure according to an embodiment of the present invention.
Fig. 3 is an enlarged schematic structural view of the third pad structure and the second enclosure structure.
Fig. 4 is a schematic cross-sectional view of the metal layer and the second enclosure structure of the third pad structure of fig. 2.
Fig. 5 is a schematic cross-sectional view of fig. 2B in one embodiment.
Fig. 6 is a schematic cross-sectional view of the first metal layer, the second metal layer and the second enclosure structure of the third pad structure in fig. 2.
Fig. 7 is a schematic cross-sectional view of fig. 2B in another embodiment.
Reference numerals illustrate:
100-a first pad structure; 200-a second pad structure; 300-a third pad structure; 310-a first current layer metal layer of a third pad structure; 320-a second current layer metal layer of the third pad structure; 400-fourth pad structure; 500-a first enclosure structure; 600-a second enclosure structure; 610-a first sub-enclosure of a second enclosure structure; 620-a second sub-enclosure of a second enclosure structure.
Detailed Description
A semiconductor test structure and a test method thereof according to the present invention will be described in further detail. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
As shown in fig. 1, a conventional semiconductor test structure for TDDB test is composed of two lead pads Pad1 and Pad2 electrically connected with a capacitor C, and the structure is affected when an IMD is pressed by pressure to generate cracks, thereby resulting in inaccurate test.
As shown in fig. 2, in order to solve the above problems, the present invention provides a semiconductor test structure, which can perform TDDB test on an interlayer dielectric layer (i.e., a dielectric layer between the same metal layers) in each metal layer, and can also perform TDDB test on an interlayer dielectric layer (i.e., a dielectric layer between upper and lower metal layers) between adjacent metal layers.
The semiconductor test structure comprises a capacitor C, a first resistor R1, a second resistor R2, a first pad structure 100, a second pad structure 200, a third pad structure 300, a fourth pad structure 400, a first enclosure structure 500 and a second enclosure structure 600, wherein the first enclosure structure 500 is arranged on the outer side of the second pad structure 200 in an insulation manner, the second enclosure structure 600 is arranged on the outer side of the third pad structure 300 in an insulation manner, the second pad structure 200 and the third pad structure 300 are electrically connected through the capacitor C, the first pad structure 100 is electrically connected with the first enclosure structure 500, the first enclosure structure 500 is electrically connected with the third pad structure 300 through the first resistor R1, the second enclosure structure 600 is electrically connected with the fourth pad structure 400, and the second enclosure structure 600 is electrically connected with the second pad structure 200 through the second resistor R2;
At the time of TDDB test, a voltage is applied to the second pad structure 200, the third pad structure 300 is grounded, or the second pad structure 200 is grounded, a voltage is applied to the third pad structure 300, and whether the IMD is a normal breakdown is determined according to the resistance between the first pad structure 100 and the second pad structure 200, and the resistance between the third pad structure 300 and the fourth pad structure 400.
In the semiconductor test structure of the embodiment, in the TDDB test, if the resistance between the first pad structure 100 and the second pad structure 200 tends to 0, it is determined that abnormal breakdown occurs between the second pad structure 200 and the first enclosure structure 500; if the resistance between the first pad structure 100 and the second pad structure 200 is equal to the first resistance R1, judging that the capacitor C breaks down normally; if the resistance between the third pad structure 300 and the fourth pad structure 400 tends to 0, it is determined that abnormal breakdown occurs between the third pad structure 300 and the second enclosure structure 600, and if the resistance between the third pad structure 300 and the fourth pad structure 400 is equal to the second resistance R2, it is determined that normal breakdown occurs between the capacitor C, so that a damaged sample of the semiconductor test structure due to the TDDB test or the package reason can be effectively removed, and the TDDB test accuracy of the IMD is greatly improved.
In detail, the first, second, third and fourth pad structures 100, 200, 300 and 400 are identical in structure. The first enclosure structures 500 are spaced apart from and insulated from each other and are surrounded on the outer side of the second pad structure 200, the second enclosure structures 600 are spaced apart from and insulated from each other and are surrounded on the outer side of the third pad structure 300, and the space between the first enclosure structures 500 and the second pad structure 200 is equal to the space between the second enclosure structures 600 and the third pad structure 300, and the space between the first enclosure structures 500 and the second pad structure 200 may be 0.045 μm to 0.2 μm, for example, 0.1 μm. The first enclosure structure 500 and the second enclosure structure 600 are ring structures with two notches, so as to realize the electrical connection between the second pad structure 200 and the second electrical group, the electrical connection between the third pad structure 300 and the first resistor R1, the electrical connection between the second pad structure 200 and the capacitor C, and the electrical connection between the third pad structure 300 and the capacitor C at the two notches. Wherein the length a of the notch is, for example, 1 μm.
The semiconductor test structure is used for TDDB testing of an interlayer dielectric layer (i.e., a same-layer dielectric layer, i.e., a horizontal interlayer dielectric layer) of a metal layer (i.e., an ith metal layer Mi) of a preset layer of the metal interconnection structure, the first pad structure 100, the second pad structure 200, the third pad structure 300 and the fourth pad structure 400 each include a current-layer metal layer and an extraction pad layer, which are sequentially arranged from bottom to top, the current-layer metal layer is embedded in the interlayer dielectric layer, the extraction pad layer is located on the surface of the interlayer dielectric layer, and the current-layer metal layer and the extraction pad layer are electrically connected through conductive vias. The metal layer on the current layer is formed simultaneously with the metal interconnection structure, and the metal interconnection structure comprises n metal layers which are separated by IMD, and the metal layer on the current layer is formed simultaneously with the metal layer Mi on the i. Wherein i is less than or equal to n and is a positive integer. As shown in fig. 4, taking the third pad structure 300 and the second enclosure structure 600 as an example, the metal layer of the second enclosure structure 600 is spaced apart by an interlayer dielectric layer and is insulated and arranged outside the second enclosure structure 600.
The metal layer of the first pad structure 100, the metal layer of the second pad structure 200, the metal layer of the third pad structure 300, and the metal layer of the fourth pad structure 400, the capacitor C, the first resistor R1, and the second resistor R2 are all arranged on the same layer in the metal layer Mi, so as to perform TDDB test on the horizontal interlayer dielectric layer.
As shown in fig. 3, the first enclosure structure 500 surrounds the metal layer of the second pad structure 200, the second enclosure structure 600 surrounds the metal layer of the third pad structure 300, a connection line between the metal layer of the second pad structure 200 and the second resistor R2 needs to pass through the first enclosure structure 500, a connection line between the metal layer of the second pad structure 200 and the capacitor C needs to pass through the first enclosure structure 500, a connection line between the metal layer of the third pad structure 300 and the capacitor C needs to pass through the second enclosure structure 600, and a connection line between the metal layer of the third pad structure 300 and the first resistor R1 needs to pass through the second enclosure structure 600. Thus, the first enclosure structure 500 and the second enclosure structure 600 each have two notches, i.e., an annular structure having two notches. The spacing between the metal layer of the second pad structure 200 and the first wall structure 500 is the same as the spacing between the metal layer of the third pad structure 300 and the second wall structure 600.
Since the first and second enclosure structures 500 and 600 each have two notches on the i-th metal layer Mi, the first and second enclosure structures 500 and 600 are connected on the i-1-th metal layer Mi-1, respectively. As shown in fig. 5, taking the second enclosure structure 600 as an example, the second enclosure structure 600 has a notch in the i-th metal layer Mi, and an electrical connection is implemented on the i-1-th metal layer Mi-1 below the notch.
The semiconductor test structure is used for TDDB testing of an interlayer dielectric layer (i.e., an interlayer dielectric layer between an upper metal layer and a lower metal layer, i.e., a vertical interlayer dielectric layer) between adjacent metal layers, the first pad structure 100, the second pad structure 200, the third pad structure 300 and the fourth pad structure 400 each include a first current layer metal layer, a second current layer metal layer and a lead-out pad layer which are sequentially arranged from bottom to top, the first current layer metal layer and the second current layer metal layer are spaced along a thickness direction and are embedded in the interlayer dielectric layer, the lead-out pad layer is located on the surface of the interlayer dielectric layer, and the first current layer metal layer, the second current layer metal layer and the lead-out pad layer are sequentially electrically connected through conductive vias.
The first enclosure structure 500 and the second enclosure structure 600 each have a first sub-enclosure and a second sub-enclosure that are sequentially arranged from bottom to top, all the first metal layers on the current layer and all the first sub-enclosures are arranged in the same layer, all the second metal layers on the current layer and all the second sub-enclosures are arranged in the same layer, the first sub-enclosures of the first enclosure structure 500 are spaced apart and are arranged around the outer side of the first metal layer on the current layer of the second pad structure 200 in an insulating manner, and the second sub-enclosures of the first enclosure structure 500 are spaced apart and are arranged around the outer side of the second metal layer on the current layer of the second pad structure 200 in an insulating manner; the first sub-enclosing walls of the second enclosing wall structure 600 are spaced apart from and insulated from each other and are enclosed outside the first metal layer of the third pad structure 300, and the second sub-enclosing walls of the second enclosing wall structure 600 are spaced apart from and insulated from each other and enclosed outside the second metal layer of the third pad structure 300.
The first and second metal layers of the first pad structure 100, the first and second metal layers of the second pad structure 200, the first and second metal layers of the third pad structure 300, the first and second metal layers of the fourth pad structure 400, the first and second sub-enclosures of the first enclosure structure 500, and the first and second sub-enclosures of the second enclosure structure 600 are all formed simultaneously with the metal interconnection structure, and all of the first and first sub-enclosures are all formed simultaneously with the i-th metal layer Mi, and all of the second metal layers of the second enclosure are all formed simultaneously with the i+1th metal layer mi+1. As shown in fig. 6, taking the third pad structure 300 and the second enclosure structure 600 as an example, the first metal layer 310 at the i-th metal layer Mi is electrically connected to the second metal layer 320 at the i+1th metal layer mi+1 through a conductive via, and the first sub-enclosure 610 at the i-th metal layer Mi is electrically connected to the second sub-enclosure 620 at the i+1th metal layer mi+1 through a conductive via. Therefore, the first pad structure 100, the second pad structure 200, the third pad structure 300, the fourth pad structure 400, the capacitor C, the first resistor R1, and the second resistor R2 are all disposed on the i-th metal layer Mi and the i+1th metal layer mi+1 to perform TDDB test on the vertical interlayer dielectric layer.
A connection line between the first metal layer of the second pad structure 200 and the second resistor R2 needs to pass through a first sub-enclosure of the first enclosure structure 500, and a connection line between the second metal layer of the second pad structure 200 and the second resistor R2 needs to pass through a second sub-enclosure of the first enclosure structure 500; a connection line between the first metal layer of the second pad structure 200 and the capacitor C needs to pass through a first sub-enclosure of the first enclosure structure 500, and a connection line between the second metal layer of the second pad structure 200 and the capacitor C needs to pass through a second sub-enclosure of the first enclosure structure 500; a connection line between the first metal layer of the third pad structure 300 and the capacitor C needs to pass through a first sub-enclosure of the second enclosure structure 600, and a connection line between the second metal layer of the third pad structure 300 and the capacitor C needs to pass through a second sub-enclosure of the second enclosure structure 600; a connection line between the first metal layer of the third pad structure 300 and the first resistor R1 needs to pass through a first sub-enclosure of the second enclosure structure 600; the connection line between the second metal layer of the third pad structure 300 and the first resistor R1 needs to pass through the second sub-enclosure of the second enclosure structure 600. Therefore, the first sub-enclosure and the second sub-enclosure of the first enclosure structure 500 and the first sub-enclosure and the second sub-enclosure of the second enclosure structure 600 have two gaps, that is, annular structures with two gaps, respectively. The spacing between the first wall structure 500 and the second metal layer of the second pad structure 200 is the same as the spacing between the second wall structure 600 and the second metal layer of the third pad structure 300.
Since the first sub-enclosing wall of the first enclosing wall structure 500 and the first sub-enclosing wall of the second enclosing wall structure 600 have two gaps on the i-th metal layer Mi, and the second sub-enclosing wall of the first enclosing wall structure 500 and the second sub-enclosing wall of the second enclosing wall structure 600 have two gaps on the i+1th metal layer mi+1, the first enclosing wall structure 500 and the second enclosing wall structure 600 are connected through conductive vias on the metal layer Mi-1 below the gaps of the i-th metal layer Mi. As shown in fig. 7, taking the second enclosure structure 600 as an example, the first sub-enclosure 610 located in the i-th metal layer Mi and the second sub-enclosure 620 located in the i+1th metal layer mi+1 are both provided with a notch, and the first sub-enclosure 610 is electrically connected to the second sub-enclosure 620 through a conductive via, and the first sub-enclosure 610 is electrically connected to the i-1 th metal layer Mi-1 located below the notch of the i-th metal layer Mi through a conductive via.
The resistances of the first resistor R1 and the second resistor R2 are the same, for example, kilo-ohm resistors.
With continued reference to fig. 2-7, the present embodiment further provides a testing method of a semiconductor test structure, which includes the following steps:
Step S1: applying a voltage to the second pad structure 200, the third pad structure 300 being grounded, or the second pad structure 200 being grounded, and applying a voltage to the third pad structure 300 to perform a TDDB test;
Step S2: upon detection of a breakdown, the resistance between the first pad structure 100 and the second pad structure 200, and the resistance between the third pad structure 300 and the fourth pad structure 400 are measured to determine if the IMD is a normal breakdown.
In step S2, when measuring the resistance between the first pad structure 100 and the second pad structure 200, the circuit loop is: the first pad structure 100 is electrically connected to the third pad structure 300 through the first enclosure structure 500 and the first resistor R1, and the second pad structure 200 is electrically connected to the third pad structure 300 through the capacitor C. In this loop, if breakdown occurs in the IMD between the first and second enclosure structures 500 and 200, the resistance between the first and second enclosure structures 100 and 200 tends to be 0, that is, when the resistance between the first and second enclosure structures 100 and 200 tends to be 0, for example, tends to be 0, it is determined that abnormal breakdown occurs in the IMD between the first and second enclosure structures 500 and 200. When the IMD between the first enclosure structure 500 and the second pad structure 200 is not broken down and is the IMD breakdown between the capacitors C, the resistance between the first pad structure 100 and the second pad structure 200 is equal to the resistance of the first resistor R1 (the sum of the resistance of the electrical connection wire and the resistance of the first resistor R1), and is the normal breakdown.
In measuring the resistance between the third pad structure 300 and the fourth pad structure 400, the circuit loop is: the fourth pad structure 400 is electrically connected to the second pad structure 200 through the second enclosure structure 600 and the second resistor R2, and the third pad structure 300 is electrically connected to the third pad structure 300 through the capacitor C. In this loop, if the IMD between the second enclosure structure 600 and the third pad structure 300 breaks down, the resistance between the third pad structure 300 and the second pad structure 200 tends to be 0, that is, when the resistance between the third pad structure 300 and the second pad structure 200 tends to be 0, it is determined that the IMD between the second enclosure structure 600 and the third pad structure 300 breaks down abnormally. When the IMD between the second enclosure structure 600 and the third pad structure 300 is not broken down and is the IMD breakdown between the capacitors C, the resistance between the third pad structure 300 and the second pad structure 200 is equal to the resistance of the second resistor R2, and is the normal breakdown.
In summary, the present invention provides a semiconductor test structure and a test method thereof, where the semiconductor test structure includes a capacitor, a first resistor, a second resistor, a first pad structure, a second pad structure, a third pad structure, a fourth pad structure, a first enclosure structure and a second enclosure structure, where the first enclosure structure is insulated and enclosed outside the second pad structure, the second enclosure structure is insulated and enclosed outside the third pad structure, the second pad structure and the third pad structure are electrically connected through the capacitor, the first pad structure and the first enclosure structure are electrically connected, the first enclosure structure is electrically connected through the first resistor and the third pad structure, the second enclosure structure and the fourth pad structure are electrically connected, and the second enclosure structure is electrically connected through the second resistor and the second pad structure; in the TDDB test, a voltage is applied to the second pad structure, the third pad structure is grounded, or the second pad structure is grounded, a voltage is applied to the third pad structure, and whether the interlayer dielectric layer is normally broken down is determined according to the resistance between the first pad structure and the second pad structure, and the resistance between the third pad structure and the fourth pad structure, which achieves the unexpected technical effects that: the damage sample of the semiconductor test structure caused by TDDB test or package reasons can be effectively removed, and the TDDB test accuracy of the IMD is greatly improved.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (7)
1. The semiconductor test structure is characterized by comprising a capacitor, a first resistor, a second resistor, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a fourth bonding pad structure, a first enclosing wall structure and a second enclosing wall structure, wherein the first enclosing wall structure is arranged on the outer side of the second bonding pad structure in an insulating manner, the second enclosing wall structure is arranged on the outer side of the third bonding pad structure in an insulating manner, the second bonding pad structure and the third bonding pad structure are electrically connected through the capacitor, the first bonding pad structure and the first enclosing wall structure are electrically connected, the first enclosing wall structure is electrically connected with the third bonding pad structure through the first resistor, the second enclosing wall structure and the fourth bonding pad structure are electrically connected, and the second enclosing wall structure is electrically connected with the second bonding pad structure through the second resistor;
The first enclosing wall structure and the second enclosing wall structure are annular structures with two gaps, so that the electrical connection of the second bonding pad structure and the electrical connection of the third bonding pad structure are realized at the two gaps, and the first enclosing wall structure and the second enclosing wall structure are respectively and electrically connected below the respective gaps;
Applying a voltage to the second pad structure, the third pad structure being grounded, or the second pad structure being grounded, applying a voltage to the third pad structure, and determining that the interlayer dielectric layer is normally broken down when the resistance between the first pad structure and the second pad structure is equivalent to the resistance of the first resistance, and determining that the interlayer dielectric layer is abnormal breakdown when the resistance between the first pad structure and the second pad structure tends to 0, and determining that the interlayer dielectric layer is normal breakdown when the resistance between the third pad structure and the fourth pad structure is equivalent to the resistance of the second resistance, and determining that the interlayer dielectric layer is abnormal breakdown when the resistance between the third pad structure and the fourth pad structure tends to 0.
2. The semiconductor test structure of claim 1, wherein a pitch between the first perimeter wall structure and the second pad structure is equal to a pitch between the second perimeter wall structure and the third pad structure, and the pitch is 0.045 μιη to 0.2 μιη.
3. The semiconductor test structure of claim 1, wherein when the semiconductor test structure is used for TDDB testing of a horizontal interlayer dielectric layer of a metal interconnection structure, the first pad structure, the second pad structure, the third pad structure and the fourth pad structure each include a layer-on-metal layer and an extraction pad layer sequentially arranged from bottom to top, all the layer-on-metal layers are arranged in the same layer, the layer-on-metal layer is embedded in the interlayer dielectric layer, the extraction pad layer is located on the surface of the interlayer dielectric layer, the layer-on-metal layer and the extraction pad layer are electrically connected through conductive vias, the first enclosure structure encloses the layer-on-metal layer of the second pad structure, and the second enclosure structure encloses the layer-on-metal layer of the third pad structure.
4. The semiconductor test structure of claim 1, wherein when the semiconductor test structure is used for TDDB testing of an interlayer dielectric layer between adjacent metal layers, the first pad structure, the second pad structure, the third pad structure and the fourth pad structure each comprise a first layer-when-metal layer, a second layer-when-metal layer and a lead-out pad layer which are sequentially arranged from bottom to top, the first layer-when-metal layer and the second layer-when-metal layer are spaced along a thickness direction and are embedded in the interlayer dielectric layer in an insulating manner, the lead-out pad layer is positioned on the surface of the interlayer dielectric layer, and the first layer-when-metal layer, the second layer-when-metal layer and the lead-out pad layer are sequentially electrically connected through conductive vias;
The first enclosure structure and the second enclosure structure are respectively provided with a first sub-enclosure and a second sub-enclosure which are sequentially arranged from bottom to top, all the first metal layers on the current layer and all the first sub-enclosures are arranged on the same layer, all the second metal layers on the current layer and all the second sub-enclosures are arranged on the same layer, the first sub-enclosures of the first enclosure structure are arranged on the outer side of the first metal layers on the current layer of the second bonding pad structure at intervals in an insulating manner, and the second sub-enclosures of the first enclosure structure are arranged on the outer side of the second metal layers on the current layer of the second bonding pad structure at intervals in an insulating manner; the first sub-enclosing walls of the second enclosing wall structure are arranged at intervals and in an insulating manner on the outer side of the first metal layer of the third bonding pad structure, and the second sub-enclosing walls of the second enclosing wall structure are arranged at intervals and in an insulating manner on the outer side of the second metal layer of the third bonding pad structure.
5. The semiconductor test structure of claim 1, wherein the first resistor and the second resistor have the same resistance value and are both kilo-ohm resistors.
6. The semiconductor test structure of claim 5, wherein the first resistor and the second resistor are kilo-ohm resistors.
7. A testing method of a semiconductor testing structure according to any one of claims 1 to 6, comprising the steps of:
Applying a voltage to the second pad structure, the third pad structure being grounded, or the second pad structure being grounded, applying a voltage to the third pad structure for TDDB testing;
When breakdown is detected, the interlayer dielectric layer is determined to be normal breakdown when the resistance between the first pad structure and the second pad structure is equal to the resistance of the first resistor, the interlayer dielectric layer is determined to be abnormal breakdown when the resistance between the first pad structure and the second pad structure tends to 0, the interlayer dielectric layer is determined to be normal breakdown when the resistance between the third pad structure and the fourth pad structure is equal to the resistance of the second resistor, and the interlayer dielectric layer is determined to be abnormal breakdown when the resistance between the third pad structure and the fourth pad structure tends to 0.
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| CN111933620A (en) * | 2020-10-19 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Test structure for detecting defects of dielectric layer |
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| CN111933620A (en) * | 2020-10-19 | 2020-11-13 | 晶芯成(北京)科技有限公司 | Test structure for detecting defects of dielectric layer |
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