CN118398494B - E/D integrated GaAs HEMT device, manufacturing method, circuit and electronic equipment thereof - Google Patents
E/D integrated GaAs HEMT device, manufacturing method, circuit and electronic equipment thereof Download PDFInfo
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 238000000151 deposition Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000011265 semifinished product Substances 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 4
- -1 boron ions Chemical class 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- General Physics & Mathematics (AREA)
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Abstract
The invention relates to the technical field of semiconductor devices, and provides an E/D integrated GaAs HEMT device, a manufacturing method thereof, a circuit thereof and electronic equipment, wherein the method comprises the following steps of: growing an epitaxial layer on the GaAs substrate to form a GaAs epitaxial wafer; etching the P-type cap layer of the depletion type gate region, the source drain region and the isolation region, stopping at the first stop layer, and depositing a dielectric layer; etching the first stop layer of the depletion type gate region and the source drain region, stopping at the first barrier layer, and depositing an N-type cap layer in the depletion type gate region and the source drain region; implanting ions for isolation into the isolation region; etching the N-type cap layer and the first barrier layer of the depletion type gate region, stopping at the second stop layer, and forming a depletion type gate groove; forming a source metal and a drain metal; an enhancement gate metal and a depletion gate metal are formed.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a manufacturing method of an E/D integrated GaAs HEMT device, the E/D integrated GaAs HEMT device, a GaAs microwave monolithic integrated circuit and electronic equipment.
Background
As a new generation of microwave devices, gaAs HEMT (High Electron Mobility Transistors, high electron mobility transistor) devices (including GAAS PHEMT (Pseudomorphic High Electron Mobility Transistors, pseudomorphic high electron mobility transistor) devices) have great advantages in terms of frequency, gain, and efficiency.
The enhanced GaAs HEMT device adopting the low-doped P-type (P-type) gate can improve the amplitude and stability of threshold voltage. The enhanced GaAs HEMT device needs to be integrated with a depletion type GaAs HEMT device, and can realize a direct logic function on a GaAs microwave monolithic product.
At present, the integration (i.e. E/D integration) process of the enhancement mode device and the depletion mode device is more complex, and the manufactured product has gaps between the enhancement mode device and the depletion mode device, so that the product quality is still to be further improved.
Disclosure of Invention
The invention provides an E/D integrated GaAs HEMT device, a manufacturing method, a circuit and electronic equipment thereof, and aims to solve the technical problems.
The technical scheme adopted by the invention is as follows:
A manufacturing method of an E/D integrated GaAs HEMT device comprises the following steps: s1, growing an epitaxial layer on a GaAs substrate to form a GaAs epitaxial wafer, wherein the epitaxial layer is of a multi-layer structure, four layers from top to bottom are a P-type cap layer, a first stop layer, a first barrier layer and a second stop layer respectively, and the GaAs epitaxial wafer is divided into an enhancement type gate region, a depletion type gate region, a source drain region and an isolation region; s2, etching the P-type cap layers of the depletion type gate region, the source drain region and the isolation region, stopping at the first stop layer, depositing a dielectric layer, forming a P-type bulge in the enhancement type gate region, forming a dielectric layer covering the top surface and the side wall of the P-type bulge, and forming a dielectric layer in the isolation region; s3, etching the first stop layers of the depletion type gate region and the source drain region, stopping at the first barrier layer, and depositing an N-type cap layer on the depletion type gate region and the source drain region; s4, implanting ions for isolation into the isolation region; s5, etching the N-type cap layer and the first barrier layer of the depletion type gate region, stopping at the second stop layer, and forming a depletion type gate groove; s6, forming source metal and drain metal at corresponding positions of the source-drain region respectively; s7, forming an enhancement type gate metal and a depletion type gate metal in the enhancement type gate region and the depletion type gate region respectively.
The step S2 specifically comprises the following steps: depositing a dielectric layer on the GaAs epitaxial wafer; etching the dielectric layers and the P-type cap layers of the depletion type gate region, the source drain region and the isolation region, stopping at the first stop layer, and obtaining a first semi-finished product; depositing a dielectric layer on the first semi-finished product; and etching the dielectric layers of the depletion type gate region and the source/drain region, and stopping at the first stop layer.
Obtaining a second semi-finished product after forming the depletion gate trench, the manufacturing method further comprising: and depositing a dielectric layer on the second semi-finished product.
The P-type cap layer adopts low-doped P-type GaAlAs, and the N-type cap layer adopts high-doped N-type GaAs.
And each deposited dielectric layer adopts silicon nitride.
And etching the first stop layer by adopting a wet etching process.
The isolating ion is boron ion.
An E/D integrated GaAs HEMT device is manufactured based on the manufacturing method of the E/D integrated GaAs HEMT device.
A GaAs microwave monolithic integrated circuit comprises the E/D integrated GaAs HEMT device.
An electronic device comprises the GaAs microwave monolithic integrated circuit.
The invention has the beneficial effects that:
The invention is manufactured on the epitaxial wafer comprising two stop layers, the upper one stop layer is beneficial to the etching and forming of the P-type grid electrode, and can provide a high-quality crystal surface for the deposition of the N-type cap layer of the source/drain region, and the seamless integration of two types of devices can be realized through the ion implantation process for isolation, and in addition, the whole process supports the simultaneous formation of the electrodes of the two types of devices, so that the manufacturing process is simple, the manufacturing efficiency is high, and the product quality is higher.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an E/D integrated GaAs HEMT device according to an embodiment of the present invention;
Fig. 2 is a schematic structural diagram of a GaAs epitaxial wafer after deposition of a dielectric layer according to an embodiment of the present invention;
FIG. 3 is a schematic view of a first semi-finished product according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure after depositing a dielectric layer on a first semi-finished product according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a dielectric layer of a depletion gate region and a source drain region after etching according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of a structure of a first stop layer of a depletion gate region and a source drain region after etching according to an embodiment of the present invention;
Fig. 7 is a schematic diagram of a structure of an embodiment of the present invention after depositing N-type cap layers in the depletion gate region and the source drain region;
FIG. 8 is a schematic diagram of an embodiment of the present invention after isolation ions are implanted in the isolation region;
FIG. 9 is a schematic diagram of the structure of a second semi-finished product according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a structure after depositing a dielectric layer on a second semi-finished product according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a structure after forming source and drain metals according to an embodiment of the present invention;
Fig. 12 is a schematic diagram of a structure after formation of an enhanced gate metal and a depleted gate metal in accordance with one embodiment of the present invention.
Reference numerals:
The semiconductor device comprises a GaAs substrate 1, an epitaxial layer 2, a dielectric layer 3, an N-type cap layer 4, an isolation structure 5, a depletion type gate groove 6, source metal 7 of an enhanced GaAs HEMT device, drain metal 8 of the enhanced GaAs HEMT device, source metal 9 of the depletion type GaAs HEMT device, drain metal 10 of the depletion type GaAs HEMT device, enhancement type gate metal 11 and depletion type gate metal 12;
A P-type cap layer 201, a P-type bump 201', a first stop layer 202, a first barrier layer 203, a second stop layer 204, a second barrier layer 205, and a channel layer 206.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, in which like filling indicates like materials. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1 to 12, the method for manufacturing the E/D integrated GaAs HEMT device according to the embodiment of the present invention includes steps S1 to S7:
S1, growing an epitaxial layer 2 on a GaAs substrate 1 to form a GaAs epitaxial wafer, wherein the epitaxial layer 2 is of a multi-layer structure, four layers from top to bottom are a P-type cap layer 201, a first stop layer 202, a first barrier layer 203 and a second stop layer 204 respectively, and the GaAs epitaxial wafer is divided into an enhanced gate region, a depletion gate region, a source drain region and an isolation region.
In one embodiment of the present invention, the epitaxial layer 2 may include a second barrier layer 205 and a channel layer 206 in addition to the four layers described above.
In one embodiment of the present invention, the P-type cap layer 201 may be a low doped P-type (P-type) GaAlAs. The first and second stop layers 202 and 204 may be GaInP, the first and second barrier layers 203 and 205 may be GaAlAs, and the channel layer 206 may be GaInAs.
The E/D integrated GaAs HEMT device to be manufactured in the embodiment of the invention is to integrate an enhanced GaAs HEMT device and a depletion type GaAs HEMT device, and the partition of the GaAs epitaxial wafer is divided according to the boundary of the two types of devices and the position of each electrode.
S2, etching the P-type cap layer 201 of the depletion type gate region, the source drain region and the isolation region, stopping at the first stop layer 202, depositing the dielectric layer 3, forming a P-type protrusion 201 'in the enhancement type gate region, forming a dielectric layer 3 covering the top surface and the side wall of the P-type protrusion 201', and forming the dielectric layer 3 in the isolation region.
Step S2 may specifically include S21 to S24:
and S21, depositing a dielectric layer 3 on the GaAs epitaxial wafer.
The dielectric layer 3 deposited in the embodiments of the present invention may be silicon nitride. The structure after deposition of the dielectric layer 3 on the GaAs epitaxial wafer is shown in fig. 2.
And S22, etching the dielectric layer 3 and the P-type cap layer 201 of the depletion type gate region, the source drain region and the isolation region, and stopping at the first stop layer 202 to obtain a first semi-finished product.
That is, on the basis of the structure of fig. 2, the regions except the enhanced gate region are etched, and the etching process may be a dry-process and a wet-process, so that the portion of the P-type cap layer 201 remaining in the enhanced gate region is referred to as a P-type protrusion 201'. Here, stopping at the first stop layer 202 and stopping at a layer later means that etching is stopped to the upper surface of the layer, and etching is not performed on the layer. The structure of the first semi-finished product is shown in fig. 3.
S23, depositing a dielectric layer 3 on the first semi-finished product.
Here, a second deposition of dielectric layer 3 is used to protect the sidewalls of P-type bump 201' and the upper surface of first stop layer 202. The dielectric layer 3 may still be silicon nitride. The structure after deposition of the dielectric layer 3 on the first semifinished product is shown in fig. 4.
And S24, etching the dielectric layer 3 of the depletion type gate region and the source/drain region, and stopping at the first stop layer 202.
That is, on the basis of the structure of fig. 4, the dielectric layer 3 may be etched in the region other than the enhanced gate region and the isolation region. It should be appreciated that since the enhanced gate region is deposited twice with the dielectric layer 3, where the thickness of the dielectric layer 3 is larger, in another embodiment of the present invention, the dielectric layer 3 in areas other than the isolation region may also be etched to a certain thickness.
The structure after etching the dielectric layer 3 of the depletion gate region and the source drain region is shown in fig. 5, and the dielectric layer 3 covering the top surface and the side wall of the P-type protrusion 201' and the isolation region is remained.
And S3, etching the first stop layer 202 of the depletion type gate region and the source/drain region, stopping on the first barrier layer 203, and depositing an N-type cap layer 4 in the depletion type gate region and the source/drain region.
In one embodiment of the present invention, a wet etch process may be used to etch the first stop layer 202 in order to preserve the quality of the crystalline interface of the first barrier layer 203. The structure after etching the first stopper layer 202 of the depletion gate region and the source drain region is shown in fig. 6.
In one embodiment of the present invention, the N-type cap layer 4 may employ highly doped N-type (n+ -type) GaAs, which may be used to form ohmic contacts for the source and drain electrodes. The structure after depositing the N-type cap layer 4 in the depletion gate region and the source drain region is shown in fig. 7.
S4, implanting isolation ions into the isolation region.
In one embodiment of the invention, the spacer ion is a boron ion. The isolation region can be reserved by covering other regions with photoresist, and the boron ion implantation process is carried out on the reserved isolation region, so that an isolation structure 5 penetrating through each layer above the GaAs substrate 1 and reaching the GaAs substrate 1 shown in fig. 8 can be formed, the isolation structure 5 plays a role in isolating two types of devices, one side of the isolation structure is an enhanced GaAs HEMT device, and the other side of the isolation structure is a depletion type GaAs HEMT device.
And S5, etching the N-type cap layer 4 and the first barrier layer 203 of the depletion type gate region, stopping at the second stop layer 204, and forming the depletion type gate groove 6.
After formation of the depletion gate trench 6, a second semi-finished product is obtained, the structure of which is shown in fig. 9.
Further, a dielectric layer 3 may also be deposited on the second semi-finished product.
Here a third deposition of a dielectric layer 3 is used to protect the exposed surfaces of the second semi-finished product, including the surface of the N-cap layer 4, the bottom and sidewalls of the depletion gate trench 6. The dielectric layer 3 may still be silicon nitride. The structure after deposition of the dielectric layer 3 on the second semifinished product is shown in fig. 10.
And S6, forming source metal and drain metal at corresponding positions of the source-drain region respectively.
As shown in fig. 11, the source metal 7 and the drain metal 8 of the enhancement GaAs HEMT device, and the source metal 9 and the drain metal 10 of the depletion GaAs HEMT device may be formed simultaneously.
S7, forming an enhancement type gate metal and a depletion type gate metal in the enhancement type gate region and the depletion type gate region respectively.
As shown in fig. 12, the gate metal of the enhancement GaAs HEMT device, i.e., enhancement gate metal 11, and the gate metal of the depletion GaAs HEMT device, i.e., depletion gate metal 12, may be formed simultaneously. The bottom surface of the enhanced gate metal 11 is connected with the top surface of the P-type protrusion 201', and the gate structure of the enhanced GaAs HEMT device is formed together.
Thus, the E/D integrated GaAs HEMT device is manufactured.
According to the manufacturing method of the E/D integrated GaAs HEMT device, disclosed by the embodiment of the invention, the upper stop layer is beneficial to etching and forming of the P-type grid electrode and can also provide a high-quality crystal surface for depositing the N-type cap layer of the source/drain region by manufacturing on the epitaxial wafer containing the two stop layers, and the seamless integration of the two types of devices can be realized by an ion implantation process for isolation.
Based on the manufacturing method of the E/D integrated GaAs HEMT device, the invention further provides the E/D integrated GaAs HEMT device.
The E/D integrated GaAs HEMT device of the embodiment of the invention is manufactured by the manufacturing method of the E/D integrated GaAs HEMT device of any embodiment. For the specific structure, reference may be made to the embodiment of the method for manufacturing the E/D integrated GaAs HEMT device and fig. 12, and details are not repeated here.
The E/D integrated GaAs HEMT device provided by the embodiment of the invention has the advantages of simple manufacturing process, high manufacturing efficiency and higher quality.
Based on the E/D integrated GaAs HEMT device of the embodiment, the invention further provides a GaAs microwave monolithic integrated circuit.
The GaAs microwave monolithic integrated circuit comprises the E/D integrated GaAs HEMT device of any embodiment of the invention.
According to the GaAs microwave monolithic integrated circuit provided by the embodiment of the invention, the E/D integrated GaAs HEMT device is simple in manufacturing process, high in manufacturing efficiency and higher in quality.
Based on the GaAs microwave monolithic integrated circuit of the embodiment, the invention further provides electronic equipment.
The electronic equipment of the embodiment of the invention comprises the GaAs microwave monolithic integrated circuit of any embodiment of the invention. The electronic device in the embodiment of the invention can be any device containing the GaAs microwave monolithic integrated circuit, such as a radio frequency device.
According to the electronic equipment provided by the embodiment of the invention, the manufacturing efficiency is high, and the quality is higher.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The meaning of "a plurality of" is two or more, unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (9)
1. The manufacturing method of the E/D integrated GaAs HEMT device is characterized by comprising the following steps of:
The method comprises the steps of S1, growing an epitaxial layer on a GaAs substrate to form a GaAs epitaxial wafer, wherein the epitaxial layer is of a multi-layer structure, four layers from top to bottom are a P-type cap layer, a first stop layer, a first barrier layer and a second stop layer respectively, the GaAs epitaxial wafer is divided into an enhancement type gate region, a depletion type gate region, a source drain region and an isolation region, the first stop layer and the second stop layer adopt GaInP, and the isolation region is positioned between an enhancement type GaAs HEMT device and the depletion type GaAs HEMT device;
S2, etching the P-type cap layers of the depletion type gate region, the source drain region and the isolation region, stopping at the first stop layer, depositing a dielectric layer, forming a P-type bulge in the enhancement type gate region, forming a dielectric layer covering the top surface and the side wall of the P-type bulge, and forming a dielectric layer in the isolation region;
S3, etching the first stop layers of the depletion type gate region and the source drain region, stopping at the first barrier layer, and depositing an N-type cap layer on the depletion type gate region and the source drain region;
s4, implanting ions for isolation into the isolation region, wherein the ions for isolation are boron ions;
S5, etching the N-type cap layer and the first barrier layer of the depletion type gate region, stopping at the second stop layer, and forming a depletion type gate groove;
s6, forming source metal and drain metal at corresponding positions of the source-drain region respectively;
s7, forming an enhancement type gate metal and a depletion type gate metal in the enhancement type gate region and the depletion type gate region respectively.
2. The method for manufacturing an E/D integrated GaAs HEMT device according to claim 1, wherein step S2 specifically comprises:
depositing a dielectric layer on the GaAs epitaxial wafer;
Etching the dielectric layers and the P-type cap layers of the depletion type gate region, the source drain region and the isolation region, stopping at the first stop layer, and obtaining a first semi-finished product;
depositing a dielectric layer on the first semi-finished product;
And etching the dielectric layers of the depletion type gate region and the source/drain region, and stopping at the first stop layer.
3. The method of manufacturing an E/D integrated GaAs HEMT device according to claim 2, wherein the second semi-finished product is obtained after forming the depletion gate trench, said method further comprising:
and depositing a dielectric layer on the second semi-finished product.
4. The method for manufacturing an E/D integrated GaAs HEMT device according to any one of claims 1-3, wherein the P-type cap layer is a low doped P-type GaAlAs and the N-type cap layer is a high doped N-type GaAs.
5. The method of manufacturing an E/D integrated GaAs HEMT device of claim 4, the method is characterized in that each deposited dielectric layer adopts silicon nitride.
6. The method of claim 4, wherein the first stop layer is etched using a wet etching process.
7. An E/D integrated GaAs HEMT device manufactured based on the method of manufacturing an E/D integrated GaAs HEMT device of any of claims 1-6.
8. A GaAs microwave monolithic integrated circuit comprising an E/D integrated GaAs HEMT device according to claim 7.
9. An electronic device comprising the GaAs microwave monolithic integrated circuit according to claim 8.
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