CN118380033A

CN118380033A - Defective pixel repair circuit and memory

Info

Publication number: CN118380033A
Application number: CN202310071033.4A
Authority: CN
Inventors: 赵北游
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-13
Filing date: 2023-01-13
Publication date: 2024-07-23
Also published as: WO2024148750A1

Abstract

The embodiment of the disclosure discloses a dead pixel repair circuit and a memory, the dead pixel repair circuit comprises: an address registering circuit, a detecting circuit and an address searching circuit; the address register circuit is used for receiving and registering two bad point addresses; the input end of the detection circuit is connected with the output end of the address register circuit and is used for acquiring two bad point addresses, outputting a first control signal when the two bad point addresses are detected to belong to the same row, and outputting a second control signal when the two bad point addresses are detected to not belong to the same row; the input end of the address searching circuit is respectively connected with the output end of the detecting circuit and the output end of the address registering circuit, and is controlled by the first control signal to output the row repair address which is commonly corresponding to the two bad point addresses, or is controlled by the second control signal to respectively output the column repair address which is corresponding to each bad point address. The present disclosure improves the utilization ratio of redundant resources.

Description

Defective pixel repair circuit and memory

Technical Field

The present disclosure relates to, but is not limited to, a bad point repair circuit and a memory.

Background

In the integrated circuit, when detecting that a defective pixel exists in a storage unit, a row of array units corresponding to the defective pixel is replaced and repaired by a redundant row (Redundancy row) by utilizing Memery Post Pockege Repair (MPPR) defective pixel repair, and because the redundant resource is limited and the resource occupation ratio of the Redundancy row is large, the Redundancy row is replaced and repaired by the Redundancy row every time when the defective pixel is detected, thereby wasting the redundant resource and leading the utilization ratio of the redundant resource to be lower.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a dead pixel repair circuit and a memory, which can improve the utilization rate of redundant resources.

The technical scheme of the present disclosure is realized as follows:

The embodiment of the disclosure provides a dead pixel repair circuit, which comprises: an address registering circuit, a detecting circuit and an address searching circuit; the address register circuit is used for receiving and registering two bad point addresses; the input end of the detection circuit is connected with the output end of the address register circuit and is used for acquiring the two bad point addresses, outputting a first control signal when the two bad point addresses are detected to belong to the same row, and outputting a second control signal when the two bad point addresses are detected to not belong to the same row; the input end of the address searching circuit is respectively connected with the output end of the detecting circuit and the output end of the address registering circuit, and is controlled by the first control signal to output the row repair address which is commonly corresponding to the two bad point addresses, or is controlled by the second control signal to respectively output the column repair address which is corresponding to each bad point address.

In the above scheme, the two bad point addresses include: a first defective pixel address and a second defective pixel address; the first bad point address includes: a first bank address and a first row address; the second defective pixel address includes: a second bank address and a second row address; the detection circuit is used for outputting the first control signal when detecting that the first memory bank address is the same as the second memory bank address and the first row address is the same as the second row address; the detection circuit is further configured to output the second control signal when detecting that the first bank address is different from the second bank address and/or the first row address is different from the second row address.

In the above aspect, the detection circuit includes: a comparison unit and a control signal generation unit; the input end of the comparison unit is used as the input end of the detection circuit and is used for outputting two first signals when the first bad point address and the second bad point address are detected to belong to the same row of addresses; the input end of the control signal generating unit is connected with the output end of the comparing unit and is controlled by the two first signals to output the first control signals; the comparing unit is further configured to output at least one second signal when detecting that the first defective pixel address and the second defective pixel address do not belong to an address of a same row; the control signal generating unit is also controlled by the at least one second signal to output the second control signal.

In the above scheme, the address register circuit includes: the first register unit, the second register unit and the third register unit; the output end of the first register unit is connected with the input end of the comparison unit and is used for receiving the traversed multiple memory bank addresses, and the first memory bank address or the second memory bank address is selected from the multiple memory bank addresses to be registered according to a selection clock signal; the output end of the second register unit is connected with the input end of the comparison unit and is used for receiving the traversed multiple row addresses, and the first row address or the second row address is selected from the multiple row addresses to be registered according to the selection clock signal; and the output end of the third register unit is connected with the input end of the address search circuit and is used for receiving the traversed multiple column addresses, and selecting the first column address or the second column address from the multiple column addresses to register according to the selection clock signal.

In the above aspect, the comparing unit includes: a first comparator and a second comparator; the input end of the first comparator is connected with the output end of the first register unit, and the output end of the first comparator is connected with the first input end of the control signal generating unit and is used for outputting a first signal when the first memory bank address is detected to be the same as the second memory bank address or outputting a second signal when the first memory bank address is detected to be different from the second memory bank address; and the input end of the second comparator is connected with the output end of the second register unit, and the output end of the second comparator is connected with the second input end of the control signal generating unit and is used for outputting a first signal when the first row address is detected to be the same as the second row address or outputting a second signal when the first row address is detected to be different from the second row address.

In the above scheme, the address lookup circuit includes: a first search circuit and a second search circuit; the input end of the first search circuit is respectively connected with the output ends of the first register unit and the second register unit, the control end of the first search circuit is connected with the output end of the control signal generation unit, the first search circuit is controlled by the first control signal to acquire the second memory bank address from the first register unit, acquire the second row address from the second register unit, and search and output the row repair address by utilizing the second memory bank address and the second row address; the input end of the second search circuit is respectively connected with the output end of the first register unit, the output end of the second register unit and the output end of the third register unit, the control end of the second search circuit is connected with the output end of the control signal generating unit, the second search circuit is controlled by the second control signal to acquire the first memory bank address from the first register unit, acquire the first row address from the second register unit and acquire the first column address from the third register unit, and the column repair address corresponding to the first defective pixel address is searched and output by utilizing the first memory bank address, the first row address and the first column address; the second lookup circuit is further controlled by the second control signal to obtain the second memory bank address from the first register unit, obtain the second row address from the second register unit, obtain the second column address from the third register unit, and use the second memory bank address, the second row address and the second column address to find and output the column repair address corresponding to the second defective pixel address.

In the above aspect, the control signal generating unit includes: and gate and inverter; the first input end of the AND gate is used as the first input end of the control signal generating unit, the second input end of the AND gate is used as the second input end of the control signal generating unit, and the output end of the AND gate is respectively connected with the control end of the first search circuit and the first end of the inverter; the output end of the AND gate outputs the first control signal; and the second end of the inverter is connected with the control end of the second search circuit, and the second end of the inverter outputs the second control signal.

In the above solution, the second search circuit includes: a selection unit and a search unit; and the input end of the selection unit is used as the input end of the second search circuit, and the output end of the selection unit is connected with the input end of the search unit and is used for providing each bad point address for the search unit in sequence according to the selection signal when the second search circuit receives the second control signal.

In the above aspect, the selecting unit includes: a first selector, a second selector, and a third selector; the first selector is configured to receive the first bank address and the second bank address, select the first bank address output according to a first value of the selection signal, or select the second bank address output according to a second value of the selection signal; the second selector is configured to receive the first row address and the second row address, select the first row address output according to the first value, or select the second row address output according to the second value; the third selector is configured to receive the first column address and the second column address, select the first column address output according to the first value, or select the second column address output according to the second value.

In the above solution, the search unit includes: a second memory cell decoder, a second row decoder, and a column lookup unit; the input end of the second memory unit decoder sequentially receives the first memory bank address and the second memory bank address from the first selector, and is used for decoding the first memory bank address or the second memory bank address into second memory unit information to output; the input end of the second row decoder sequentially receives the first row address and the second row address from the second selector, and is used for decoding the first row address or the second row address into second row information to output; and the input end of the column searching unit receives the second storage unit information, the second row information and the corresponding matched column address, and is used for searching and outputting the column repair address by utilizing the second storage unit information, the second row information and the column address.

In the above solution, the first search circuit includes: a first memory cell decoder, a first row decoder, and a row search unit; the input end of the first memory cell decoder receives the first memory bank address or the second memory bank address from the first register cell and is used for decoding the first memory bank address or the second memory bank address into first memory cell information to output; the input end of the first row decoder receives the first row address or the second row address from the second register unit, and is used for decoding the first row address or the second row address into first row information to output; and the control end of the row searching unit receives the first storage unit information and the first row information and is used for searching and outputting the row repair address by utilizing the first storage unit information and the first row information.

In the above aspect, the first register unit includes: a first register and a second register; the selection clock signal includes: a first clock pulse and a second clock pulse, wherein the first clock pulse corresponds to the first bad point address, and the second clock pulse corresponds to the second bad point address; the output end of the first register is connected with the input end of the second register and the first input end of the first selector, the control end of the first register is used for receiving the selection clock signal and is used for receiving the traversed multiple memory bank addresses, selecting the first memory bank address from the multiple memory bank addresses to register according to the first clock pulse, transmitting the first memory bank address to the second register, and selecting the second memory bank address from the multiple memory bank addresses to register according to the second clock pulse; and the input end of the second register is connected with the output end of the first register, the control end of the second register receives the selection clock signal, and the output end of the second register is connected with the second input end of the first selector and is used for receiving the first memory bank address and registering the first memory bank address according to the second clock pulse.

In the above aspect, the second register unit includes: a third register and a fourth register; the selection clock signal includes: a first clock pulse and a second clock pulse; the output end of the third register is connected with the input end of the fourth register and the first input end of the second selector, the control end of the third register is used for receiving the selection clock signal and is used for receiving a plurality of traversed row addresses, selecting the first row address from the row addresses to register according to the first clock pulse, transmitting the first row address to the fourth register, and selecting the second row address from the row addresses to register according to the second clock pulse; and the input end of the fourth register is connected with the output end of the third register, the control end of the fourth register receives the selection clock signal, the output end of the fourth register is connected with the second input end of the second selector, and the fourth register is used for receiving the first row address and registering the first row address according to the second clock pulse.

In the above aspect, the third register unit includes: a fifth register and a sixth register; the selection clock signal includes: a first clock pulse and a second clock pulse; the output end of the fifth register is connected with the input end of the sixth register and the first input end of the third selector, the control end of the fifth register is used for receiving the selection clock signal and is used for receiving the traversed multiple column addresses, selecting the first column address from the multiple column addresses to register according to the first clock pulse, transmitting the first column address to the sixth register, and selecting the second column address from the multiple column addresses to register according to the second clock pulse; and the input end of the sixth register is connected with the output end of the fifth register, the control end of the sixth register receives the selection clock signal, the output end of the sixth register is connected with the second input end of the third selector, and the sixth register is used for receiving the first column address and registering the first column address according to the second clock pulse.

The embodiment of the disclosure also provides a memory, which comprises the dead pixel repair circuit.

In the above scheme, the memory is a dynamic random access memory DRAM

It can be seen that the embodiment of the present disclosure provides a dead pixel repair circuit, which includes: an address registering circuit, a detecting circuit and an address searching circuit; the address register circuit is used for receiving and registering two bad point addresses; the input end of the detection circuit is connected with the output end of the address register circuit and is used for acquiring two bad point addresses, outputting a first control signal when the two bad point addresses are detected to belong to the same row, and outputting a second control signal when the two bad point addresses are detected to not belong to the same row; the input end of the address searching circuit is respectively connected with the output end of the detecting circuit and the output end of the address registering circuit, and is controlled by the first control signal to output the row repair address which is commonly corresponding to the two bad point addresses, or is controlled by the second control signal to respectively output the column repair address which is corresponding to each bad point address. Because the row repair addresses which are commonly corresponding to the two bad point addresses can be output when the two bad point addresses are detected to belong to the same row, and the column repair addresses which are respectively corresponding to the two bad points can be output when the two bad point addresses are detected to not belong to the same row; and performing row repair on the two dead pixels based on the row repair address, or performing column repair on the corresponding dead pixels based on the column repair address. Since among the redundant resources for repair, the redundant column resources are far more than the redundant row resources; according to the embodiment of the disclosure, the redundant column resources are preferentially adopted for row repair according to the specific condition of the defective pixel address, and the redundant row resources are adopted for row repair only when two defective pixels belong to the same row. Thus, redundant row resources are saved, and the utilization ratio of the redundant resources is optimized.

Drawings

Fig. 1 is a schematic diagram of a dead pixel repair circuit according to an embodiment of the present disclosure;

Fig. 2 is a schematic diagram of a dead pixel repair circuit according to a second embodiment of the present disclosure;

fig. 3 is a schematic diagram III of a structure of a dead pixel repair circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a dead pixel repair circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the disclosure;

Fig. 7 is a schematic diagram seventh of a structure of a dead pixel repair circuit according to an embodiment of the disclosure;

fig. 8 is a schematic structural diagram eight of a dead pixel repair circuit according to an embodiment of the disclosure;

Fig. 9 is a schematic diagram nine of a structure of a dead pixel repair circuit according to an embodiment of the disclosure;

fig. 10 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the present disclosure;

FIG. 11 is a schematic flow chart of a method for repairing a defective pixel according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first/second" appears in the present document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first/second/third" may interchange a specific order or precedence, as allowed, to enable embodiments of the disclosure described herein to be implemented in an order other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the related art, the redundant resource library corresponding to MPPR stores 4 rows of redundant resources. When repairing bad pixels, MPPR can only use 2 rows of redundant resources in 4 rows of redundant resources. If 2 of the 4 rows of redundant resources are exhausted or corrupted. MPPR will automatically detect this situation and no longer perform bad point repair. Because the resource proportion of the redundant row is larger in the redundant resource, the utilization rate of the redundant resource is lower in the related art by repairing a dead pixel through the row redundant resource.

Referring to fig. 1, fig. 1 is a schematic diagram of a dead pixel repair circuit according to an embodiment of the disclosure.

The embodiment of the disclosure provides a dead pixel repair circuit 50, the dead pixel repair circuit 50 includes: an address registering circuit 10, a detecting circuit 20, and an address finding circuit 30. The address register circuit 10 is configured to receive and register two bad addresses. The input end of the detection circuit 20 is connected to the output end of the address register circuit 10, and is used for acquiring two bad point addresses, outputting a first control signal when detecting that the two bad point addresses belong to the same row, and outputting a second control signal when detecting that the two bad point addresses do not belong to the same row. The input end of the address lookup circuit 30 is respectively connected with the output end of the detection circuit 20 and the output end of the address register circuit 10, and is controlled by a first control signal to output a row repair address corresponding to the two bad point addresses together, or is controlled by a second control signal to respectively output a column repair address corresponding to each bad point address.

Referring to fig. 1, a plurality of memory cell addresses are obtained by scanning the entire chip through a memory built-in-self test (mBIST), and are supplied to the address register circuit 10, and when mBIST scans a defective pixel, the address register circuit 10 is controlled to register the defective pixel address. That is: the address register circuit 10 receives a plurality of memory cell addresses, and selects a defective pixel address from the plurality of memory cell addresses to register. After registering two defective pixel addresses, the address registering circuit 10 may send the two defective pixel addresses to the detecting circuit 20, where the detecting circuit 20 detects whether the two defective pixel addresses belong to the same row, outputs a first control signal to the address searching circuit 30 when detecting that the two defective pixel addresses belong to the same row, and outputs a second control signal to the address searching circuit 30 when detecting that the two defective pixel addresses do not belong to the same row. The address lookup circuit 30 is responsive to the first control signal for finding a row repair address that corresponds to the two defective pixel addresses in common based on any one of the two defective pixel addresses. The address lookup circuit 30 finds a corresponding column repair address based on each defective pixel address in response to the second control signal.

It should be noted that, each memory cell has a corresponding memory cell address, where the memory cell address includes: a bank address (bank address), a row address (row address), and a column address. The bank address is used for indicating the number of the bank (bank) corresponding to the memory cell, the row address is used for indicating the memory row (row) where the memory cell is located, and the column address is used for indicating the memory column (column) where the memory cell is located. When the storage unit fails, the storage unit becomes a dead pixel, and the storage unit address corresponding to the dead pixel is the dead pixel address.

In some embodiments of the present disclosure, the two bad addresses include: the first defective pixel address and the second defective pixel address. The first bad point address includes: a first bank address and a first row address. The second defective pixel address includes: a second bank address and a second row address. Referring to fig. 2, the detection circuit 20 is configured to output a first control signal when detecting that the first bank address is the same as the second bank address and the first row address is the same as the second row address. Referring to fig. 3, the detecting circuit 20 is further configured to output the second control signal when detecting that the first bank address is different from the second bank address and/or the first row address is different from the second row address.

In connection with fig. 2, after the address lookup circuit 30 outputs the row repair address, the row array units corresponding to the two bad point addresses are repaired by using the row repair address to find the corresponding redundant row in the redundant resource library through MPPR. Referring to fig. 3, after the address lookup circuit 30 outputs the column repair address, a column of array units corresponding to the defective pixel address is repaired by using MPPR to find a corresponding redundant column in the redundant resource library by using the column repair address.

It may be understood that in the embodiment of the present disclosure, when two bad point addresses are detected to belong to the same row, a row repair address that corresponds to the two bad point addresses together may be output, and when two bad points are detected not to belong to the same row, a column repair address that corresponds to the two bad points respectively may be output; and performing row repair on the two dead pixels based on the row repair address, or performing column repair on the corresponding dead pixels based on the column repair address. Since among the redundant resources for repair, the redundant column resources are far more than the redundant row resources; according to the embodiment of the disclosure, the redundant column resources are preferentially adopted for row repair according to the specific condition of the defective pixel address, and the redundant row resources are adopted for row repair only when two defective pixels belong to the same row. Thus, redundant row resources are saved, and the utilization ratio of the redundant resources is optimized.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the disclosure.

Referring to fig. 4, the detection circuit 20 includes: a comparison unit 201 and a control signal generation unit 202. The input terminal of the comparing unit 201 is used as the input terminal of the detecting circuit 20, and is used for outputting two first signals when detecting that the first bad point address and the second bad point address belong to the same row address. The input end of the control signal generating unit 202 is connected with the output end of the comparing unit 201, and is controlled by two first signals to output first control signals. Referring to fig. 5, the comparing unit 201 is further configured to output at least one second signal when detecting that the first defective pixel address and the second defective pixel address do not belong to the same row address. The control signal generating unit 202 is further controlled by at least one second signal output second control signal.

Referring to fig. 4, when the comparing unit 201 detects that the first bank address and the second bank address are consistent, and the first row address and the second row address are consistent, that is, the two bad addresses are on the same row address, the comparing unit 201 outputs two 1's (the first signal is the output value 1). The control signal generation unit 202 forms a first control signal. The address lookup circuit 30 uses the second bank address and the second row address to lookup and output the row repair address which corresponds to the two defective pixel addresses in common in response to the first control signal.

Referring to fig. 5, the comparing unit 201 outputs a second signal when it detects that the first bank address and the second bank address are not identical, or outputs a second signal when it detects that the first row address and the second row address are not identical. The comparing unit 201 detects that the first bank address and the second bank address are not identical, and outputs two second signals when the first row address and the second row address are not identical. As long as there is one second signal or two second signals in the output of the comparison unit 201, it indicates that two defective pixel addresses do not appear on the same row address. The control signal generation unit 202 forms a second control signal when the comparison unit 201 outputs a value of 0 (the second signal is the output value of 0) when two dead pixels do not appear on the same row of the same bank. The address lookup circuit 30 responds to the second control signal and uses each defective pixel address to lookup and output a corresponding column repair address.

In the embodiment of the disclosure, when the first and second defective pixel addresses belong to the same row address, the comparison unit 201 outputs two first signals to enable the control signal generating unit 202 to output the first control signals according to the two first signals, and the address searching circuit 30 is controlled by the first control signals to search the row repair address commonly corresponding to the two defective pixel addresses, so that the same row corresponding to the two defective pixel addresses is repaired by using one row repair address, and redundant row resources are saved. When the first and second defective pixel addresses do not belong to the same row address, the comparing unit 201 outputs at least one second signal to enable the control signal generating unit 202 to output a second control signal, and the address searching circuit 30 searches the column repair addresses corresponding to the two defective pixel addresses respectively in response to the second control signal, and repairs each column corresponding to the defective pixel address by using the column repair address.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the disclosure.

Referring to fig. 6, the address register circuit 10 includes: a first register unit 101, a second register unit 102, and a third register unit 103. The output end of the first register unit 101 is connected to the input end of the comparing unit 201, and is configured to receive the traversed multiple memory bank addresses, and select the first memory bank address or the second memory bank address from the multiple memory bank addresses according to the selection clock signal for registering. The output end of the second register unit 102 is connected to the input end of the comparing unit 201, and is configured to receive the traversed row addresses, and select the first row address or the second row address from the row addresses according to the selection clock signal for registering. The output end of the third register unit 103 is connected to the input end of the address lookup circuit 30, and is used for receiving the traversed multiple column addresses, and selecting the first column address or the second column address from the multiple column addresses according to the selection clock signal for registering.

In the embodiment of the disclosure, since the three register units register the bank address, the row address and the column address in each of the bad point addresses according to the selection clock signals, when the comparing unit 201 performs address comparison, the first register unit 101 may respectively transmit the corresponding bank address in each of the bad point addresses to the comparing unit 201, and the second register unit 102 may respectively transmit the corresponding row address in each of the bad point addresses to the comparing unit 201, so that the comparing unit 201 accurately compares the bank address and the row address of two bad point addresses, which is beneficial to improving the accuracy of comparing two bad points by respectively comparing the bank address and the row address.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the disclosure.

Referring to fig. 7, the comparison unit 201 includes: a first comparator 2011 and a second comparator 2012. The input end of the first comparator 2011 is connected to the output end of the first register unit 101, and the output end of the first comparator 2011 is connected to the first input end of the control signal generating unit 202, and is configured to output a first signal when detecting that the first bank address is the same as the second bank address, or output a second signal when detecting that the first bank address is different from the second bank address.

Referring to fig. 7, the second comparator 2012 has an input terminal connected to the output terminal of the second register unit 102 and an output terminal connected to the second input terminal of the control signal generating unit 202, and is configured to output the first signal when the first row address and the second row address are detected to be the same, or output the second signal when the first row address and the second row address are detected to be different.

Referring to fig. 7, when the first comparator 2011 detects that the first bank address matches the second bank address, it outputs 1. When the first comparator 2011 detects that the first bank address and the second bank address do not match, it outputs 0. The second comparator 2012 outputs 1 when detecting that the first row address matches the second row address. The second comparator 2012 outputs 0 when it detects that the first row address does not match the second row address.

The first comparator 2011 and the second comparator 2012 may be equal value comparators, and the equal value comparators are used to check whether the values are equal. The inputs to the equivalence comparator may be a and B. A and B are equal to each other, 1 is output, and A and B are unequal to each other, 0 is output.

In the embodiment of the disclosure, when two bad addresses belong to the same row, two comparators output two first signals, so that the control signal generating unit 202 outputs the first control signal to control the address searching circuit 30 to search the row repair address corresponding to the two bad addresses in common. And then, the same row corresponding to the two bad point addresses is repaired by using one row repair address, so that the same row corresponding to the two bad point addresses is repaired by using one row repair address, and redundant row resources are saved. When the two defective pixel addresses do not belong to the same row, the two comparators output at least one second signal, so that the control signal generating unit 202 outputs the second control signal to control the address searching circuit 30 to search the column repair addresses respectively corresponding to the two defective pixel addresses. And then, each bad point address corresponding column is repaired by using the column repair address, and the redundant column resources are more than the redundant row resources, so that the redundant row resources are saved by repairing each bad point address corresponding column by using the column repair address.

Referring to fig. 8, fig. 8 is a schematic structural diagram eight of a dead pixel repair circuit according to an embodiment of the disclosure.

Referring to fig. 8, the address lookup circuit 30 includes: a first search circuit 301 and a second search circuit 302. The input end of the first search circuit 301 is respectively connected with the output ends of the first register unit 101 and the second register unit 102, the control end of the first search circuit 301 is connected with the output end of the control signal generating unit 202, the first search circuit is controlled by the first control signal to acquire a second memory bank address from the first register unit 101, acquire a second row address from the second register unit 102, and search and output a row repair address by using the second memory bank address and the second row address.

Referring to fig. 8, the second lookup circuit 302 has its input terminals connected to the output terminal of the first register unit 101, the output terminal of the second register unit 102, and the output terminal of the third register unit 103, and its control terminal connected to the output terminal of the control signal generating unit 202, and is controlled by the second control signal to obtain the first bank address from the first register unit 101, obtain the first row address from the second register unit 102, obtain the first column address from the third register unit 103, and find and output the column repair address corresponding to the first dead point address using the first bank address, the first row address, and the first column address.

Referring to fig. 8, the second lookup circuit 302 is further controlled by a second control signal to obtain a second memory bank address from the first register unit 101, obtain a second row address from the second register unit 102, obtain a second column address from the third register unit 103, and use the second memory bank address, the second row address and the second column address to lookup and output a column repair address corresponding to the second defective pixel address.

Referring to fig. 8, when the first bank address and the second bank address are identical, it means that two bad points appear in the same bank. When the first row address and the second row address are consistent, the bad point appears in the same row address. So when two dead pixels appear on the same row of the same bank, the output values of the first comparator 2011 and the second comparator 2012 are simultaneously 1, and the control signal generating unit 202 outputs a first control signal (row repair enable signal) to the first search circuit 301. The first lookup circuit 301 decodes via the second bank address and the second row address. And obtaining decoded bank and section addresses, fixing the corresponding row repair address value to be 1 according to a row blown fuse lookup table mode to enable the row repair address value to be effective, and replacing the damaged row with a redundant row after the row repair address is effective, so that automatic repair of the array is realized.

Referring to fig. 8, when the first bank address and the second bank address are not identical, when the first row address and the second row address are not identical, or when the first bank address and the second bank address are not identical, and the first row address and the second row address are not identical, the output values of the first comparator 2011 and the second comparator 2012 are not 1, and the control signal generating unit 202 outputs the second control signal (column repair enable signal) to the second search circuit 302. The second lookup circuit 302 decodes each defective pixel address to determine a bank and a section address, and then combines column plane error bit to fix the corresponding column repair address value to 1 in the form of a lookup table, and the defective column is replaced by a redundant column after the column repair address is validated, thereby realizing automatic repair of the column array.

In the embodiment of the present disclosure, when two bad point addresses are detected to belong to the same row, the first lookup circuit 301 may output a row repair address that corresponds to the two bad point addresses together. And then, the same row corresponding to the two bad point addresses is repaired by using one row repair address, so that the same row corresponding to the two bad point addresses is repaired by using one row repair address, and redundant row resources are saved. When it is detected that two bad points do not belong to the same row, the second lookup circuit 302 may output column repair addresses corresponding to the two bad points, and repair each column corresponding to the bad point address by using the column repair address.

Referring to fig. 9, fig. 9 is a schematic diagram of a dead pixel repair circuit according to an embodiment of the disclosure.

Referring to fig. 9, the control signal generation unit 202 includes: and gate 2021 and inverter 2022. The and gate 2021 has a first input terminal as the first input terminal of the control signal generating unit 202, a second input terminal as the second input terminal of the control signal generating unit 202, and an output terminal connected to the control terminal of the first search circuit 301 and the first terminal of the inverter 2022, respectively. The output of the and gate 2021 outputs a first control signal. The second terminal of the inverter 2022 is connected to the control terminal of the second search circuit 302, and the second terminal of the inverter 2022 outputs the second control signal.

In the embodiment of the disclosure, the and gate 2021 determines the first signal and the second signal output by the first comparator 2011 and the second comparator 2012, so that the first control signal can be output when the output of both comparators is the first signal. When the two comparator outputs include at least one second signal, the control inverter 2022 outputs a second control signal. In the present disclosure, the first control signal or the second control signal may be flexibly and accurately output according to whether the two defective pixel addresses belong to the same row, so as to control the address lookup circuit 30 to correspondingly output one row repair address corresponding to the two defective pixel addresses or a column repair address corresponding to each defective pixel address, and then perform row repair on the two defective pixels based on the row repair address or perform column repair on the corresponding defective pixel based on the column repair address. Since among the redundant resources for repair, the redundant column resources are far more than the redundant row resources; according to the embodiment of the disclosure, the redundant column resources are preferentially adopted for row repair according to the specific condition of the defective pixel address, and the redundant row resources are adopted for row repair only when two defective pixels belong to the same row. Thus, redundant row resources are saved, and the utilization ratio of the redundant resources is optimized.

In connection with fig. 9, the second search circuit 302 includes: a selection unit 3021 and a search unit 3022. And a selection unit 3021, an input end of which is used as an input end of the second search circuit 302, and an output end of which is connected with an input end of the search unit 3022, and is used for providing each defective pixel address to the search unit 3022 in turn according to the selection signal when the second search circuit 302 receives the second control signal.

In this embodiment of the disclosure, the selecting unit 3021 may select each of the two defective pixel addresses according to the second control signal, and provide the selected defective pixel address to the searching unit 3022, and the searching unit 3022 may search for a corresponding column repair address according to each defective pixel address, so as to repair each column corresponding to the defective pixel address by using the column repair address.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a dead pixel repair circuit according to an embodiment of the disclosure.

Referring to fig. 10, the selecting unit 3021 includes: the first selector 30211, the second selector 30212, and the third selector 30213. The first selector 30211 is configured to receive the first bank address and the second bank address, select the first bank address output according to the first value of the selection signal, or select the second bank address output according to the second value of the selection signal. A second selector 30212 for receiving the first row address and the second row address, selecting the first row address output according to the first value, or selecting the second row address output according to the second value. The third selector 30213 is configured to receive the first column address and the second column address, select the first column address output according to the first value, or select the second column address output according to the second value.

The control terminals of the first selector 30211, the second selector 30212, and the third selector 30213 receive the same selection signal, and when the selection signal is a first value, the first selector 30211 outputs a first bank address to the lookup unit 3022, the second selector 30212 outputs a first row address to the lookup unit 3022, and the third selector 30213 outputs a first column address to the lookup unit 3022. The first bank address, the first row address, and the first column address belong to a first defective pixel address. When the selection signal is a second value, the second selector 30212 outputs the second bank address to the lookup unit 3022, the second selector 30212 outputs the second row address to the lookup unit 3022, and the third selector 30213 outputs the second column address to the lookup unit 3022. The second bank address, the second row address, and the second column address belong to a second defective pixel address.

In the embodiment of the disclosure, the first selector 30211, the second selector 30212 and the third selector 30213 convey the first defective pixel address to the lookup unit 3022 according to the first value of the selection signal, and convey the second defective pixel address to the lookup unit 3022 according to the second value of the selection signal, so that the lookup unit 3022 can accurately find the corresponding column repair address for each defective pixel address, further repair each column of the defective pixel address by using the column repair address, and since the redundant column resources are more than the redundant row resources, the manner of repairing each column of the defective pixel address by using the column repair address also saves the redundant row resources.

Referring to fig. 10, the search unit 3022 includes: a second memory cell decoder 30221, a second row decoder 30222, and a column lookup unit 30223. The second memory cell decoder 30221 has an input terminal for sequentially receiving the first memory bank address and the second memory bank address from the first selector 30211 and decoding the first memory bank address or the second memory bank address into the second memory cell information to output. The second row decoder 30222 has an input terminal receiving the first row address and the second row address in sequence from the second selector 30212, and is configured to decode the first row address or the second row address into the second row information and output the second row information. And the input end of the column searching unit 30223 receives the second storage unit information, the second row information and the corresponding matched column address, and is used for searching and outputting a column repair address by using the second storage unit information, the second row information and the column address.

Referring to fig. 10, when the first and second defective addresses do not belong to the same row, the first selector 30211 selects the first bank address according to the first value of the selection signal and transmits it to the second memory cell decoder 30221, and the second memory cell decoder 30221 may decode the first bank address into the second memory cell information and output it. The second selector 30212 selects the first row address based on the first value of the selection signal and supplies the selected first row address to the second row decoder 30222, and the second row decoder 30222 decodes the first row address into the second row information and outputs the second row information. The third selector 30213 selects the first column address to be supplied to the column lookup unit 30223 according to the first value of the selection signal. The column searching unit 30223 receives the second storage unit information, the second row information and the first column address, and searches and outputs a column repair address corresponding to the first defective pixel address by using the second storage unit information, the second row information and the first column address. The column searching unit 30223 searches the column repair address corresponding to the first defective pixel address in the column repair address 1 to the column repair address 64 based on the second control signal, thereby implementing automatic repair of the column.

Referring to fig. 10, when the first and second defective addresses do not belong to the same row, the first selector 30211 selects the second bank address according to the second value of the selection signal and transmits the second bank address to the second memory cell decoder 30221, and the second memory cell decoder 30221 may decode the second bank address into second memory cell information and output the second memory cell information. The second selector 30212 selects the second row address based on the second value of the selection signal and supplies the selected second row address to the second row decoder 30222, and the second row decoder 30222 decodes the second row address into the second row information and outputs the second row information. The third selector 30213 selects the second column address to be supplied to the column lookup unit 30223 according to the second value of the selection signal. The column searching unit 30223 receives the second storage unit information, the second row information, and the second column address, and searches and outputs a column repair address corresponding to the second defective pixel address using the second storage unit information, the second row information, and the second column address. The column searching unit 30223 searches the column repair address corresponding to the second defective pixel address in the column repair address 1 to the column repair address 64 based on the second control signal, thereby implementing automatic repair of the column.

In the embodiment of the disclosure, the column searching unit 30223 uses the second storage unit information, the second row information and the corresponding matched column address to search the column repair address corresponding to the defective pixel address for outputting, so that the column corresponding to the defective pixel address is repaired by using the column repair address, and since the redundant column resources are more than the redundant row resources, the redundant row resources are also saved by repairing the defective pixel column by the column repair address.

Referring to fig. 10, the first search circuit 301 includes: a first memory cell decoder 3011, a first row decoder 3012, and a row lookup unit 3013. The first memory cell decoder 3011 has an input terminal receiving the first memory bank address or the second memory bank address from the first register unit 101, and decodes the first memory bank address or the second memory bank address into first memory cell information and outputs the first memory cell information. The first row decoder 3012 has an input terminal receiving the first row address or the second row address from the second register unit 102, and decodes the first row address or the second row address into first row information to output. And a row searching unit 3013, the control end of which receives the first storage unit information and the first row information and is used for searching and outputting the row repair address by using the first storage unit information and the first row information.

Referring to fig. 10, when the first and second defective pixel addresses belong to the same row. The first register unit 101 supplies a first bank address to the first memory unit decoder 3011, and the second register unit 102 supplies a second row address to the first row decoder 3012. The first memory cell decoder 3011 decodes the second bank address into first memory cell information and outputs the first memory cell information, and the first row decoder 3012 decodes the second row address into first row information and outputs the first row information. The row search unit 3013 receives the first memory cell information and the first row information, and searches for a row repair address corresponding to the second defective pixel address from the row repair address 1 to the row repair address 64 using the first memory cell information and the first row information, thereby implementing the automatic repair of the row.

In the embodiment of the present disclosure, the row searching unit 3013 searches and outputs a row repair address, which corresponds to two bad point addresses in common, by using the first storage unit information and the first row information. And repairing a corresponding row of two dead pixels by using the row repairing address, so that compared with a mode of repairing a corresponding row of one dead pixel address by using one redundant row resource, the redundant row resource is saved.

Referring to fig. 10, the first register unit 101 includes: a first register 1011 and a second register 1012. Selecting the clock signal includes: the clock signal generating circuit comprises a first clock pulse and a second clock pulse, wherein the first clock pulse corresponds to a first bad point address, and the second clock pulse corresponds to a second bad point address.

The output end of the first register 1011 is connected to the input end of the second register 1012 and the first input end of the first selector 30211, and the control end thereof receives a selection clock signal for receiving the traversed plurality of memory bank addresses, selecting the first memory bank address from the plurality of memory bank addresses according to the first clock pulse for registering, and transmitting the first memory bank address to the second register 1012, and selecting the second memory bank address from the plurality of memory bank addresses according to the second clock pulse for registering.

The second register 1012 has an input terminal connected to the output terminal of the first register 1011, a control terminal receiving a selection clock signal, and an output terminal connected to the second input terminal of the first selector 30211, and is configured to receive the first bank address, and register the first bank address according to the second clock pulse.

In the embodiment of the disclosure, the two registers may accurately register the bank addresses in the first and second bad addresses according to the clock pulse, so that the first comparator 2011 can accurately compare the bank addresses of the two bad addresses. Therefore, the method of simultaneously comparing whether the memory bank address and the row address of the two bad points are the same is adopted, and is beneficial to improving the comparison accuracy of the two bad points.

Referring to fig. 10, the second register unit 102 includes: a third register 1021 and a fourth register 1022. Selecting the clock signal includes: a first clock pulse and a second clock pulse.

The output terminal of the third register 1021 is connected to the input terminal of the fourth register 1022 and the first input terminal of the second selector 30212, and the control terminal thereof receives a selection clock signal for receiving a plurality of row addresses traversed, selecting a first row address from the plurality of row addresses according to a first clock pulse for registering, and transmitting the first row address to the fourth register 1022, and selecting a second row address from the plurality of row addresses according to a second clock pulse for registering.

The fourth register 1022 has an input terminal connected to the output terminal of the third register 1021, a control terminal connected to the second input terminal of the second selector 30212, and an output terminal connected to the second input terminal of the second selector 30212, for receiving the first row address, and registering the first row address according to the second clock pulse.

In the embodiment of the disclosure, the two registers may accurately register the row addresses in the first and second bad addresses according to the clock pulse, so that the second comparator 2012 accurately compares the row addresses of the two bad addresses. Therefore, the method of simultaneously comparing whether the memory bank address and the row address of the two bad points are the same is adopted, and is beneficial to improving the comparison accuracy of the two bad points.

Referring to fig. 10, the third register unit 103 includes: a fifth register 1031 and a sixth register 1032. Selecting the clock signal includes: a first clock pulse and a second clock pulse.

The fifth register 1031 has an output terminal connected to the input terminal of the sixth register 1032 and the first input terminal of the third selector 30213, and a control terminal receiving a selection clock signal for receiving a plurality of column addresses traversed, selecting a first column address from the plurality of column addresses according to a first clock pulse for registering, and supplying the first column address to the sixth register 1032, and selecting a second column address from the plurality of column addresses according to a second clock pulse for registering.

The sixth register 1032 has an input terminal connected to the output terminal of the fifth register 1031, a control terminal receiving the selection clock signal, and an output terminal connected to the second input terminal of the third selector 30213, and is configured to receive the first column address and register the first column address according to the second clock pulse.

In the embodiment of the disclosure, the two registers may accurately register the column addresses in the first and second bad addresses according to the clock pulse, respectively, so as to provide the column lookup unit 30223 with the corresponding column addresses according to the selection signal. The lookup unit 3022 accurately looks up the corresponding column repair address for each defective pixel address. The column repair addresses are used for repairing each column corresponding to the defective pixel addresses, and redundant column resources are more than redundant row resources, so that the column repair addresses are used for repairing each column corresponding to the defective pixel addresses, and redundant row resources are saved.

Referring to fig. 11, fig. 11 is a flow chart of a dead pixel repairing method according to an embodiment of the disclosure. The description will be made in connection with the steps.

S101, performing built-in self-test scanning on the memory.

In the embodiment of the disclosure, the bad point repairing device detects the chip and scans the chip mBIST. The value of the output mode register MR27<6> during mBIST scans monitors the chip state and if MR27<6> =0, no bad point is found, no MPPR bad point repair will be performed. If MR27<6> =1, then a bad point is found, which is repaired by MPPR.

In the embodiment of the disclosure, the bad point repairing device traverses a plurality of memory cell addresses in the detection chip, and judges whether the memory cell addresses are bad point addresses or not according to MR27<6 >. And an address register circuit for recording the defective pixel address and transmitting the plurality of memory cell addresses to if the memory cell address is the defective pixel address. The address register circuit registers the bad point address according to the clock signal.

S102, reading a register and judging whether a defective pixel address exists or not.

In the embodiment of the disclosure, an address register circuit read by a dead pixel repairing device. Judging whether the address register circuit has a bad point address, and if the address register circuit has no bad point address, finishing the bad point repair. If there are a first defective pixel address and a second defective pixel address in the address register circuit, S103 is performed.

S103, reading the register output MPPR resources.

In the embodiment of the disclosure, when detecting that two bad point addresses belong to the same row, the bad point repair device outputs a row repair address which corresponds to the two bad point addresses together. When detecting that two bad point addresses do not belong to the same row, the bad point repair device outputs column repair addresses corresponding to the bad point addresses respectively.

S104, executing MPPR.

In the embodiment of the disclosure, the bad point repairing device precharges all the memory cells, and the chip enters an idle state. Using MR37 < 2 > = 1 enable MPPR. The bad point repair device obtains mBist the key, sends out an Active command, and responds to the Active command to execute MPPR the bad point repair. MPPR the dead pixel repair is completed and MPPR is exited by setting MR37:op [2] =0. The bad point repairing apparatus reads MR27 < 6 >, and if there are still other bad points, the controller may perform S101 to S104.

S105, repairing the damaged array.

The conventional MPPR repair can only indiscriminately replace a whole broken row with a redundant row, and the embodiment of the disclosure can avoid the problem, and when only one column address on a certain row is broken, only the broken point on the column can be specially repaired, so that the repair of the whole redundant row can be avoided, the resources of the redundant row are saved, and the utilization rate of the redundant resources is improved. Meanwhile, when more than two column addresses are broken on the same row, the embodiment of the disclosure can also automatically select to replace the whole row, so that the flexibility and the utilization rate of automatic repair are improved.

Fig. 12 is a schematic diagram of an alternative structure of a memory according to an embodiment of the disclosure, and as shown in fig. 12, a memory 60 includes the dead pixel repair circuit 50 provided in the foregoing embodiment.

In some embodiments of the present disclosure, referring to fig. 12, memory 60 is a dynamic random access memory DRAM.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A dead pixel repair circuit, characterized in that the dead pixel repair circuit comprises: an address registering circuit, a detecting circuit and an address searching circuit;

The address register circuit is used for receiving and registering two bad point addresses;

The input end of the detection circuit is connected with the output end of the address register circuit and is used for acquiring the two bad point addresses, outputting a first control signal when the two bad point addresses are detected to belong to the same row, and outputting a second control signal when the two bad point addresses are detected to not belong to the same row;

The input end of the address searching circuit is respectively connected with the output end of the detecting circuit and the output end of the address registering circuit, and is controlled by the first control signal to output the row repair address which is commonly corresponding to the two bad point addresses, or is controlled by the second control signal to respectively output the column repair address which is corresponding to each bad point address.

2. The dead pixel repair circuit of claim 1, wherein two of the dead pixel addresses comprise: a first defective pixel address and a second defective pixel address; the first bad point address includes: a first bank address and a first row address; the second defective pixel address includes: a second bank address and a second row address;

The detection circuit is used for outputting the first control signal when detecting that the first memory bank address is the same as the second memory bank address and the first row address is the same as the second row address;

The detection circuit is further configured to output the second control signal when detecting that the first bank address is different from the second bank address and/or the first row address is different from the second row address.

3. The dead pixel repair circuit of claim 2, wherein the detection circuit comprises: a comparison unit and a control signal generation unit;

the input end of the comparison unit is used as the input end of the detection circuit and is used for outputting two first signals when the first bad point address and the second bad point address are detected to belong to the same row of addresses;

The input end of the control signal generating unit is connected with the output end of the comparing unit and is controlled by the two first signals to output the first control signals;

The comparing unit is further configured to output at least one second signal when detecting that the first defective pixel address and the second defective pixel address do not belong to an address of a same row;

The control signal generating unit is also controlled by the at least one second signal to output the second control signal.

4. The dead pixel repair circuit of claim 3, wherein the address registration circuit comprises: the first register unit, the second register unit and the third register unit;

The output end of the first register unit is connected with the input end of the comparison unit and is used for receiving the traversed multiple memory bank addresses, and the first memory bank address or the second memory bank address is selected from the multiple memory bank addresses to be registered according to a selection clock signal;

The output end of the second register unit is connected with the input end of the comparison unit and is used for receiving the traversed multiple row addresses, and the first row address or the second row address is selected from the multiple row addresses to be registered according to the selection clock signal;

And the output end of the third register unit is connected with the input end of the address search circuit and is used for receiving the traversed multiple column addresses, and selecting a first column address or a second column address from the multiple column addresses to register according to the selection clock signal.

5. The dead pixel restoration circuit according to claim 4, wherein the comparing unit includes: a first comparator and a second comparator;

The input end of the first comparator is connected with the output end of the first register unit, and the output end of the first comparator is connected with the first input end of the control signal generating unit and is used for outputting a first signal when the first memory bank address is detected to be the same as the second memory bank address or outputting a second signal when the first memory bank address is detected to be different from the second memory bank address;

And the input end of the second comparator is connected with the output end of the second register unit, and the output end of the second comparator is connected with the second input end of the control signal generating unit and is used for outputting a first signal when the first row address is detected to be the same as the second row address or outputting a second signal when the first row address is detected to be different from the second row address.

6. The dead pixel repair circuit of claim 5, wherein the address lookup circuit comprises: a first search circuit and a second search circuit;

The input end of the first search circuit is respectively connected with the output ends of the first register unit and the second register unit, the control end of the first search circuit is connected with the output end of the control signal generation unit, the first search circuit is controlled by the first control signal to acquire the second memory bank address from the first register unit, acquire the second row address from the second register unit, and search and output the row repair address by utilizing the second memory bank address and the second row address;

The input end of the second search circuit is respectively connected with the output end of the first register unit, the output end of the second register unit and the output end of the third register unit, the control end of the second search circuit is connected with the output end of the control signal generating unit, the second search circuit is controlled by the second control signal to acquire the first memory bank address from the first register unit, acquire the first row address from the second register unit and acquire the first column address from the third register unit, and the column repair address corresponding to the first defective pixel address is searched and output by utilizing the first memory bank address, the first row address and the first column address;

The second lookup circuit is further controlled by the second control signal to obtain the second memory bank address from the first register unit, obtain the second row address from the second register unit, obtain the second column address from the third register unit, and use the second memory bank address, the second row address and the second column address to find and output the column repair address corresponding to the second defective pixel address.

7. The dead pixel restoration circuit according to claim 6, wherein the control signal generating unit includes: and gate and inverter;

the first input end of the AND gate is used as the first input end of the control signal generating unit, the second input end of the AND gate is used as the second input end of the control signal generating unit, and the output end of the AND gate is respectively connected with the control end of the first search circuit and the first end of the inverter; the output end of the AND gate outputs the first control signal;

and the second end of the inverter is connected with the control end of the second search circuit, and the second end of the inverter outputs the second control signal.

8. The dead pixel restoration circuit according to claim 6, wherein the second search circuit comprises: a selection unit and a search unit;

and the input end of the selection unit is used as the input end of the second search circuit, and the output end of the selection unit is connected with the input end of the search unit and is used for providing each bad point address for the search unit in sequence according to the selection signal when the second search circuit receives the second control signal.

9. The dead pixel repair circuit of claim 8, wherein the selecting unit includes: a first selector, a second selector, and a third selector;

the first selector is configured to receive the first bank address and the second bank address, select the first bank address output according to a first value of the selection signal, or select the second bank address output according to a second value of the selection signal;

The second selector is configured to receive the first row address and the second row address, select the first row address output according to the first value, or select the second row address output according to the second value;

The third selector is configured to receive the first column address and the second column address, select the first column address output according to the first value, or select the second column address output according to the second value.

10. The dead pixel restoration circuit according to claim 9, wherein the search unit includes: a second memory cell decoder, a second row decoder, and a column lookup unit;

the input end of the second memory unit decoder sequentially receives the first memory bank address and the second memory bank address from the first selector, and is used for decoding the first memory bank address or the second memory bank address into second memory unit information to output;

the input end of the second row decoder sequentially receives the first row address and the second row address from the second selector, and is used for decoding the first row address or the second row address into second row information to output;

And the input end of the column searching unit receives the second storage unit information, the second row information and the corresponding matched column address, and is used for searching and outputting the column repair address by utilizing the second storage unit information, the second row information and the column address.

11. The dead pixel restoration circuit according to claim 6, wherein the first search circuit comprises: a first memory cell decoder, a first row decoder, and a row search unit;

The input end of the first memory cell decoder receives the first memory bank address or the second memory bank address from the first register cell and is used for decoding the first memory bank address or the second memory bank address into first memory cell information to output;

the input end of the first row decoder receives the first row address or the second row address from the second register unit, and is used for decoding the first row address or the second row address into first row information to output;

And the control end of the row searching unit receives the first storage unit information and the first row information and is used for searching and outputting the row repair address by utilizing the first storage unit information and the first row information.

12. The dead pixel restoration circuit according to claim 9, wherein the first register unit includes: a first register and a second register; the selection clock signal includes: a first clock pulse and a second clock pulse, wherein the first clock pulse corresponds to the first bad point address, and the second clock pulse corresponds to the second bad point address;

The output end of the first register is connected with the input end of the second register and the first input end of the first selector, the control end of the first register is used for receiving the selection clock signal and is used for receiving the traversed multiple memory bank addresses, selecting the first memory bank address from the multiple memory bank addresses to register according to the first clock pulse, transmitting the first memory bank address to the second register, and selecting the second memory bank address from the multiple memory bank addresses to register according to the second clock pulse;

And the input end of the second register is connected with the output end of the first register, the control end of the second register receives the selection clock signal, and the output end of the second register is connected with the second input end of the first selector and is used for receiving the first memory bank address and registering the first memory bank address according to the second clock pulse.

13. The dead pixel restoration circuit according to claim 9, wherein the second register unit includes: a third register and a fourth register; the selection clock signal includes: a first clock pulse and a second clock pulse;

The output end of the third register is connected with the input end of the fourth register and the first input end of the second selector, the control end of the third register is used for receiving the selection clock signal and is used for receiving a plurality of traversed row addresses, selecting the first row address from the row addresses to register according to the first clock pulse, transmitting the first row address to the fourth register, and selecting the second row address from the row addresses to register according to the second clock pulse;

and the input end of the fourth register is connected with the output end of the third register, the control end of the fourth register receives the selection clock signal, the output end of the fourth register is connected with the second input end of the second selector, and the fourth register is used for receiving the first row address and registering the first row address according to the second clock pulse.

14. The dead pixel restoration circuit according to claim 9, wherein the third register unit includes: a fifth register and a sixth register; the selection clock signal includes: a first clock pulse and a second clock pulse;

the output end of the fifth register is connected with the input end of the sixth register and the first input end of the third selector, the control end of the fifth register is used for receiving the selection clock signal and is used for receiving the traversed multiple column addresses, selecting the first column address from the multiple column addresses to register according to the first clock pulse, transmitting the first column address to the sixth register, and selecting the second column address from the multiple column addresses to register according to the second clock pulse;

and the input end of the sixth register is connected with the output end of the fifth register, the control end of the sixth register receives the selection clock signal, the output end of the sixth register is connected with the second input end of the third selector, and the sixth register is used for receiving the first column address and registering the first column address according to the second clock pulse.

15. A memory comprising a dead pixel repair circuit according to any one of claims 1 to 14.

16. The memory of claim 15, wherein the memory is a dynamic random access memory, DRAM.