CN118366850A

CN118366850A - Method for manufacturing semiconductor device and semiconductor device

Info

Publication number: CN118366850A
Application number: CN202410533992.8A
Authority: CN
Inventors: 吴剑波; 周玉华; 冷国庆; 李�杰
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2024-04-29
Filing date: 2024-04-29
Publication date: 2024-07-19

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate, and forming a groove in the semiconductor substrate; irradiating a second portion of the semiconductor substrate adjacent to the first portion of the trench with a femtosecond laser beam such that non-thermal melting of the second portion of the semiconductor substrate occurs; and performing a thermal oxidation treatment on the semiconductor substrate after the irradiation of the femtosecond laser beam is completed, so that the second portion of the semiconductor substrate forms an oxide layer.

Description

Method for manufacturing semiconductor device and semiconductor device

Technical Field

The present disclosure relates generally to the field of semiconductors, and more particularly, to methods for fabricating semiconductor devices and semiconductor devices.

Background

Silicon carbide (SiC), which is represented by a third generation semiconductor material, has more excellent electrical characteristics such as a large forbidden bandwidth, a high critical breakdown electric field, a high thermal conductivity, a high carrier saturation drift rate, and a strong irradiation resistance, as compared with silicon (Si). By virtue of the electrical characteristics of SiC, semiconductor devices more suitable for application fields of high voltage, high temperature, high frequency, strong radiation, and the like can be developed, and among them, siC metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field-Effect Transistor, MOSFETs) are attracting more attention.

SiC MOSFETs commonly used in high-voltage low-power consumption scenarios are classified into trench-type SiC MOSFETs and planar-type SiC MOSFETs. The vertical planar SiC MOSFET has a Junction Field-Effect Transistor (JFET) region, which makes the output dc resistance of the semiconductor device large, and limits the power threshold of the semiconductor device. In addition, planar SiC MOSFETs have a problem of degradation of channel mobility due to channel ion implantation. Compared to conventional planar SiC MOSFETs, trench SiC MOSFETs have no JFET region, can avoid parasitic JFET effects (e.g., additional resistance created by the JFET region), can achieve increased wafer density, and also have improved electrical performance with higher blocking voltages, better switching characteristics, and lower on-loss.

Disclosure of Invention

The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. It should be understood that this summary is not an exhaustive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its purpose is to present some concepts related to the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method comprises the following steps: providing a semiconductor substrate, and forming a groove in the semiconductor substrate; irradiating a second portion of the semiconductor substrate adjacent to the first portion of the trench with a femtosecond laser beam such that non-thermal melting of the second portion of the semiconductor substrate occurs; and performing a thermal oxidation treatment on the semiconductor substrate after the irradiation of the femtosecond laser beam is completed, so that the second portion of the semiconductor substrate forms an oxide layer.

In some embodiments, in a perfect (intact) crystal structure of the semiconductor substrate, an oxidation rate of a crystal plane of the trench at a first portion is lower than an oxidation rate of a crystal plane of a third portion of the trench different from the first portion.

In some embodiments, the femtosecond laser beam is a first femtosecond laser beam, the method further comprising: irradiating a fourth portion of the semiconductor substrate adjacent to the third portion of the trench with a second femtosecond laser beam before performing a thermal oxidation process on the semiconductor substrate such that non-thermal melting of the fourth portion of the semiconductor substrate occurs; after the irradiation of the first and second femtosecond laser beams is completed, performing a thermal oxidation process on the semiconductor substrate such that the second and fourth portions of the semiconductor substrate form an oxide layer, wherein the irradiation of the first and second femtosecond laser beams is configured such that a depth of a region where non-thermal melting occurs in the second portion of the semiconductor substrate is greater than a depth of a region where non-thermal melting occurs in the fourth portion of the semiconductor substrate.

In some embodiments, the method satisfies at least one of: the irradiation duration of the first femtosecond laser beam is longer than the irradiation duration of the second femtosecond laser beam; or the intensity of the first femtosecond laser beam is greater than the intensity of the second femtosecond laser beam; or the first and second femtosecond laser beams are irradiated in the form of pulses, and the pulse frequency of the first femtosecond laser beam is greater than that of the second femtosecond laser beam.

In some embodiments, the first portion of the trench is a bottom surface of the trench and the third portion of the trench is a side surface of the trench.

In some embodiments, the semiconductor substrate comprises silicon carbide.

In some embodiments, the femtosecond laser beam is provided by a femtosecond laser.

In some embodiments, during the irradiation of the femtosecond laser beam, a ratio of the non-thermal melting process energy contribution of the second portion of the semiconductor substrate to the thermal melting process energy contribution of the second portion of the semiconductor substrate exceeds a preset ratio.

In some embodiments, the preset ratio is determined based on a value of a ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution at a maximum slope of a trend of variation of the laser parameter with the femtosecond laser beam.

In some embodiments, the laser parameter of the femtosecond laser beam is configured to be not less than a first laser parameter threshold at which the second portion of the semiconductor substrate begins to melt.

In some embodiments, the laser parameter of the femtosecond laser beam is configured to be no greater than a second laser parameter threshold at which the second portion of the semiconductor substrate is completely melted.

In some embodiments, the laser parameters of the femtosecond laser beam are configured to make the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution as large as possible.

In some embodiments, the first laser parameter threshold and the second laser parameter threshold are determined based on a carrier number density balance, a carrier system energy conservation, and a lattice system energy balance of the semiconductor substrate.

In some embodiments, the carrier number density balance requirement of the semiconductor substrate Energy conservation requirements of carrier systems of semiconductor substrates Lattice system energy balance requirements for semiconductor substratesThe second portion of the semiconductor substrate begins to melt the requirement ρc _L(T_m-T₀)＝ρC_L(T_Lm-T₀)+N_CE_g; The second partial complete melting requirement ρC_L(T_m-T₀)+L_m＝ρC_L(T_Lm-T₀)+N_CE_g, of the semiconductor substrate, where N _C is carrier concentration, t is time, a ₁ is single photon absorption coefficient, I is intensity of the femtosecond laser beam, hv is photon energy corresponding to wavelength of the femtosecond laser beam, Beta is a two-photon absorption coefficient, delta is an impact ionization coefficient, gamma is an Auger recombination coefficient, U _C is total energy of a carrier system, alpha _FCA is a free carrier absorption coefficient, k _B is a Boltzmann constant, tau _C is carrier-lattice relaxation time, T _C is the carrier temperature, T _L is the lattice temperature, U _L is the total energy of the lattice system, z is the spatial coordinates, κ _L is the lattice thermal conductivity, ρ is the density of the semiconductor substrate, C _L is the lattice heat capacity, T _m is the melting point of the semiconductor substrate at room temperature, T ₀ is the lattice temperature at room temperature, T _Lm is the melting point of the semiconductor substrate at carrier concentration N _C, E _g is the band gap width of the semiconductor substrate, and L _m is the latent heat of fusion of the semiconductor substrate.

In some embodiments, the laser parameters of the femtosecond laser beam are set based on a relationship of a desired thickness of the oxide layer to be formed by the second portion of the semiconductor substrate relative to a first reference thickness that is a thickness of the oxide layer to be formed by the second portion of the semiconductor substrate if the femtosecond laser beam is irradiated with a first laser parameter threshold value and a second reference thickness that is a thickness of the oxide layer to be formed by the second portion of the semiconductor substrate if the femtosecond laser beam is irradiated with a second laser parameter threshold value.

In some embodiments, the laser parameters of the femtosecond laser beam include intensity, wavelength, or a combination thereof.

In some embodiments, irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes irradiating the second portion of the semiconductor substrate with the femtosecond laser beam in pulses. In such embodiments, the femtosecond laser beam may be referred to as a pulsed femtosecond laser beam. In some examples, the laser parameters of the pulsed femtosecond laser beam include pulse width, energy density, wavelength, or a combination thereof. The pulse width and energy density of the pulsed femtosecond laser beam together determine the intensity of the pulsed femtosecond laser beam.

In some embodiments, the pulse width of the femtosecond laser beam is set to be between 50 femtoseconds (fs) and 150 fs.

In some embodiments, the pulse frequency of the femtosecond laser beam is configured such that the non-thermal melting of the second portion of the semiconductor substrate continues to occur.

In some embodiments, the pulse frequency of the femtosecond laser beam is set to be greater than 1 megahertz (MHz).

In some embodiments, the femtosecond laser beam is configured to be irradiated in a direction parallel to a depth direction of the trench, and an irradiation region of the femtosecond laser beam is configured to cover the trench in a width direction of the trench.

In some embodiments, irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes causing the single femtosecond laser beam or the plurality of femtosecond laser beams to scan the second portion of the semiconductor substrate in a scan direction parallel to a length direction of the trench.

In some embodiments, when the single femtosecond laser beam is caused to scan the second portion of the semiconductor substrate in the scanning direction, a previous irradiation region and a next irradiation region of the single femtosecond laser beam partially overlap each other in the scanning direction; or when the plurality of femtosecond laser beams are caused to scan the second portion of the semiconductor substrate in the scanning direction, irradiation regions of each adjacent two of the plurality of femtosecond laser beams partially overlap each other in the scanning direction.

In some embodiments, the method further includes forming a gate over the oxide layer.

In some embodiments, the method further comprises: forming one of a source region and a drain region in a fifth portion of the semiconductor substrate at one side of the trench top, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the trench top; or forming one of the source region and the drain region in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate located under the trench.

In some embodiments, providing a semiconductor substrate having a trench formed therein includes: forming a hard mask layer on a semiconductor substrate; a photoresist pattern is formed on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate.

In some embodiments, the method further comprises: the hard mask layer is removed after the irradiation of the femtosecond laser beam is completed and before the thermal oxidation treatment is performed on the semiconductor substrate.

In some embodiments, the femtosecond laser beam is a first femtosecond laser beam, the method further comprising: before performing thermal oxidation treatment on the semiconductor substrate, performing pullback treatment on the hard mask layer to expose one or both of a fifth part and a sixth part of the semiconductor substrate, which are respectively positioned on two sides of the top of the trench; irradiating one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam such that the one or both of the fifth portion and the sixth portion of the semiconductor substrate is non-thermally melted; and performing a thermal oxidation treatment on the semiconductor substrate after the irradiation of the first and third femtosecond laser beams is completed, such that the second portion and the one or both of the fifth and sixth portions of the semiconductor substrate form an oxide layer.

In some embodiments, the third femtosecond laser beam is the same as the first femtosecond laser beam.

In some embodiments, the irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that a depth of a region where the non-thermal melting occurs in the second portion of the semiconductor substrate is equal to a depth of a region where the non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate.

In some embodiments, the method further comprises forming a gate over the oxide layer, and wherein the method further comprises: forming one of a source region and a drain region in an eighth portion of the semiconductor substrate at a side of the fifth portion remote from the trench, and forming the other of the source region and the drain region in a ninth portion of the semiconductor substrate at a side of the sixth portion remote from the trench; or forming one of a source region and a drain region in one or both of the eighth portion and the ninth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate located under the trench.

According to a second aspect of the present disclosure, there is provided a semiconductor device manufactured by the method according to the first aspect of the present disclosure.

In some embodiments, the semiconductor device includes a MOSFET, wherein the oxide layer is configured to provide a gate oxide layer of the MOSFET.

Drawings

The foregoing and other features and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, as illustrated in the accompanying drawings. The accompanying drawings, which are incorporated herein and form a part of the specification, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure. Wherein:

Fig. 1 shows a schematic cross section of a conventional trench SiC MOSFET;

Fig. 2 illustrates a flowchart of a method for fabricating a semiconductor device, according to some embodiments of the present disclosure;

fig. 3A to 3J show schematic cross-sectional views of a semiconductor device corresponding to respective steps of a non-limiting example process for implementing the method shown in fig. 2, respectively;

fig. 4A illustrates a schematic top view of a semiconductor device when scanning a semiconductor substrate with a single femtosecond laser beam according to some embodiments of the disclosure;

fig. 4B illustrates a schematic top view of a semiconductor device when scanning a semiconductor substrate with a multi-femtosecond laser beam according to some embodiments of the disclosure;

Fig. 5 shows schematic cross-sectional views of a semiconductor device corresponding to respective steps of a non-limiting example process for implementing methods for manufacturing semiconductor devices according to some embodiments of the present disclosure;

Fig. 6 shows a schematic cross-sectional view of a semiconductor device corresponding to respective steps of another non-limiting example process for implementing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same parts or parts having the same functions, and a repetitive description thereof may be omitted. In some cases, like numbers and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.

For ease of understanding, the positions, dimensions, ranges, etc. of the respective structures shown in the drawings and the like may not represent actual positions, dimensions, ranges, etc. Accordingly, the present disclosure is not limited to the disclosed positions, dimensions, ranges, etc. as illustrated in the accompanying drawings.

Detailed Description

Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the structures and methods herein are shown by way of example to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will appreciate that they are merely illustrative of the exemplary ways in which the disclosure may be practiced, and not exhaustive. Moreover, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

In addition, techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be considered part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values.

The same or similar characters may be used herein to denote the same or similar variables, and thus, once a variable is defined in an embodiment, a repeated description thereof is not necessary in subsequent embodiments.

Since the electric field strength of the gate oxide layer in the SiC MOSFET is higher than that of the SiC material, when the SiC material has not yet been broken down, the gate oxide layer has already been broken down, leading to early failure of the semiconductor device. In this case, to produce a high-quality SiC MOSFET, reliability problems of the gate oxide layer of the SiC MOSFET need to be considered.

The gate oxide of SiC MOSFETs is typically prepared by thermally oxidizing SiC to form silicon dioxide (SiO ₂). This thermal oxidation process has anisotropy, and the oxidation rates at different crystal planes of SiC are greatly different, which can adversely affect the performance of the semiconductor device. Specifically, in a hexagonal SiC structure, one chemical bond of tetrahedrally bonded Si atoms is along the C-axis (< 0001 >) on a (0001) crystal plane, which is referred to as a "Si crystal plane". And atOne chemical bond of the tetrahedrally bonded C atom on the crystal plane is along the C-axisThis crystal plane is called "C crystal plane". In addition to the Si and C crystal planes,The crystal plane is called "a crystal plane",The crystal plane is called "M crystal plane". The surface energy, chemical reaction activation and electronic properties are significantly related to the crystal planes.

SiC thermal oxidation can be expressed as the following equation:

It can be seen that the oxidation rate of SiC is strongly dependent on the crystal orientation of SiC. The root cause is that when Si atoms on the surface of the SiC substrate are oxidized, one Si-C bond on the C crystal face is to be broken, two Si-C bonds on the A crystal face are to be broken, and three Si-C bonds on the Si crystal face are to be broken. Because the ratio of activation energy is the same as the difference in the number of broken Si-C bonds between crystal plane orientations, the oxidation activation energy in the rate limiting interfacial reaction should be related to the broken Si-C bond energy on the crystal plane. Thus, the C crystal plane The oxidation rate is the fastest and the oxidation rate of the Si crystal plane (0001) is the slowest. A crystal planeAnd M crystal planeIs between Si crystal face (0001) and C crystal faceIs provided between the oxidation rates of (a).

In preparing a trench in a SiC substrate, the bottom of the trench is typically oriented with Si (0001) planes, and the sidewalls of the trench are typically oriented with a planesOr M crystal planeThat is, the thickness of the oxide layer formed at the bottom of the trench of the SiC substrate may be smaller than the thickness of the oxide layer formed at the sidewall of the trench under conditions that ensure that the respective crystal planes are heated uniformly during thermal oxidation. For example, fig. 1 shows a schematic cross section of a trench-type SiC MOSFET 10 after a conventional thermal oxidation process (the gist of blurring is not avoided, and components not discussed are not shown in fig. 1). As shown in fig. 1, the thickness of the gate oxide layer 13 at the bottom of the trench 11 is about one third of the thickness of the gate oxide layer 12 at the side wall of the trench 11. However, in the trench type SiC MOSFET, an electric field is concentrated at the trench corners, and the oxide layer is easily broken down, thereby limiting the blocking voltage of the semiconductor device.

Although SiC is described above as an example, it should be understood that other substrate materials may similarly suffer from gate oxide reliability problems if they also have different oxidation rates on different crystal planes, resulting in anisotropic thermal oxidation processes.

Accordingly, a new method of manufacturing a semiconductor device is desired to optimize the formation of an oxide layer of the semiconductor device to improve the performance of the semiconductor device.

To this end, the present disclosure provides a method for manufacturing a semiconductor device, which enables non-thermal melting of a portion of a semiconductor substrate by irradiating the portion of the semiconductor substrate adjacent to a specific portion of a trench with a femtosecond laser beam, thereby enabling the thickness of an oxide layer formed on the portion of the semiconductor substrate to meet a demand, increasing the reliability of the oxide layer, and improving the blocking voltage and reliability of the semiconductor device. In addition, the thickness distribution of the oxide layer formed can be further adjusted by changing the laser parameters and irradiation parameters of the femtosecond laser beam so as to meet various requirements in actual semiconductor manufacturing.

The types of melting include both hot melting and non-hot melting. It is to be noted that, in this context, "non-thermal melting occurs" means that in melting, a non-thermal melting process is entirely or predominately and there is a certain thermal melting process, but excluding the case of an entirely thermal melting process and the case of a thermal melting process predominately and there is a certain non-thermal melting process. That is, the form of melting depends on the contribution of each of the non-thermal melting process and the thermal melting process to the energy required for melting, and is referred to as "non-thermal melting" if the non-thermal melting process predominates.

Methods for manufacturing a semiconductor device and corresponding semiconductor devices according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be understood that other steps may exist for an actual method, and other components may also exist for an actual semiconductor device, and that the figures are not shown and other steps/other components are not discussed herein in order to avoid obscuring the gist of the present disclosure.

Fig. 2 illustrates a flowchart of a method 100 for manufacturing a semiconductor device 200, according to some embodiments of the present disclosure. Fig. 3A to 3J show schematic cross-sectional views of a semiconductor device corresponding to respective steps of a non-limiting example process of implementing the method shown in fig. 2, respectively.

For convenience of explanation, in the present disclosure, a direction parallel to a thickness direction of a transistor is denoted by z, a direction perpendicular to the thickness direction of the transistor is denoted by x, and directions perpendicular to x and z are denoted by y. In addition, herein, for convenience of explanation, "high", "low", "upper", "lower", "deep", "shallow", etc. may be used to describe the relative relationship of the transistor in z, "left", "right", etc. may be used to describe the relative relationship of the transistor in x, and "front", "rear", etc. may be used to describe the relative relationship of the transistor in y.

As shown in fig. 2, the method 100 includes: at step S102, a semiconductor substrate is provided, in which a trench is formed.

For example, the semiconductor substrate may include semiconductor materials having different oxidation rates on different crystal planes. In some embodiments, the semiconductor substrate comprises silicon carbide. For purposes of illustration, a semiconductor substrate whose semiconductor material comprises silicon carbide (SiC) is given as a non-limiting example in the following description.

In some embodiments, in the intact crystal structure of the semiconductor substrate (i.e., the crystal structure is unchanged), the oxidation rate of the crystal plane of the first portion of the trench is lower than the oxidation rate of the crystal plane of a third portion of the trench that is different from the first portion. For example, in a perfect crystal structure of a semiconductor substrate, the number of bonds that need to be broken when oxidation occurs in the crystal plane of the first portion of the trench may be greater than the number of bonds that need to be broken when oxidation occurs in the crystal plane of the third portion of the trench. In some examples, the first portion of the trench is a bottom surface of the trench and the third portion of the trench is a side surface of the trench. For example, in a SiC semiconductor substrate, the bottom surface of the trench is typically the Si crystal plane (0001), and the side surface is typically the a crystal planeOr M crystal planeThe oxidation rate of Si crystal plane (0001) is lower than that of A crystal planeAnd M crystal planeIs used for the oxidation rate of (a).

A semiconductor substrate having a trench formed therein may be provided, or an untreated semiconductor substrate may be provided and then a trench may be formed therein. In some embodiments, providing a semiconductor substrate having a trench formed therein may include: forming a hard mask layer on a semiconductor substrate; a photoresist pattern is formed on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate. For example, refer to fig. 3A to 3D.

As shown in fig. 3A, a semiconductor substrate 201 is provided.

As shown in fig. 3B, a hard mask layer 202 is formed (e.g., may be formed by deposition (such as, but not limited to, chemical vapor deposition, etc.) or a thermal oxide growth process, etc.) on the semiconductor substrate 201.

The hard mask layer 202 may include, for example, but is not limited to, an oxide or nitride of a semiconductor material or a combination thereof, such as silicon dioxide and/or silicon nitride, and the like. In some embodiments, the hard mask layer 202 may be a single layer or a multi-layer structure, for example, may include a stack of silicon dioxide layers and silicon nitride layers. The hard mask layer 202 may have any suitable thickness, for example, its thickness may be between 1 nanometer (nm) and 2 micrometers (μm), or may be between 50nm and 1 μm, or may be between 100nm and 500 nm. The hard mask layer 202 may help ensure that the portions of the hard mask layer 202 that are also irradiated with the femtosecond laser beam and the underlying thin layer of the semiconductor substrate 201 near the upper surface of the substrate do not melt during the subsequent laser processing process while the thin layer of the semiconductor substrate 201 near the trench surface (which is not covered by the hard mask layer 202) is irradiated with the femtosecond laser beam. Since the unetched portions of the upper surface of the semiconductor substrate 201 remain a good native interface, the hard mask layer 202 may protect the good native interface.

As shown in fig. 3C, a photoresist pattern 203 is formed on the hard mask layer 202. For example, the photoresist pattern 203 may be formed by first coating a photoresist on the hard mask layer 202 and then developing by exposure. The photoresist pattern 203 may define the position, shape, and size of a trench to be fabricated in the semiconductor substrate 201. The photoresist pattern 203 may be formed on the hard mask layer 202 using any suitable means such as Spin-on Coating, spray Coating, drop Coating, brush Coating, or evaporation.

As shown in fig. 3D, the hard mask layer 202 and the semiconductor substrate 201 are etched to form a trench 204 in the semiconductor substrate 201. For example, the hard mask layer 202 may be etched using the photoresist pattern 203, and then the semiconductor substrate 201 may be etched using the etched hard mask layer 202 after the photoresist pattern 203 is removed (the photoresist pattern 203 may be removed in any suitable manner such as a dry and/or wet process, which is not particularly limited herein) to form the trench 204. As shown in fig. 3D, the groove 204 includes a bottom surface 2041 (first portion) and a side surface 2042 (third portion).

Referring back to fig. 2, the method 100 further includes: at step S104, a second portion of the semiconductor substrate adjacent to the first portion of the trench is irradiated with the femtosecond laser beam such that non-thermal melting of the second portion of the semiconductor substrate occurs.

For example, as shown in fig. 3E, the second portion 2011 of the semiconductor substrate 201 adjacent to the bottom surface 2041 of the trench 204 is irradiated with the femtosecond laser beam 205, so that the second portion 2011 of the semiconductor substrate 201 is non-thermally melted. Meanwhile, the fourth portion 2012 of the semiconductor substrate 201 adjacent to the side surface 2042 of the trench 204 is not irradiated with the femtosecond laser beam 205.

The physical process caused by laser irradiation of the semiconductor substrate may be as follows.

(1) The carriers are excited. The semiconductor substrate absorbs laser energy to cause carrier excitation therein. Single photon absorption can occur when the photon energy of the laser is greater than or equal to the bandgap width of the semiconductor substrate; multiphoton absorption can occur when the photon energy of the laser is less than the bandgap width of the semiconductor substrate. Free carrier absorption increases the energy of the carriers without changing the number density of the carriers. In addition, when the energy of one electron in a high energy state exceeds the band gap energy of the smallest conduction band, it can ionize another electron in the valence band, thereby generating two excited electrons at the conduction band minimum, and a collision ionization process occurs. These electrons can be heated again by the laser electromagnetic field through free carrier absorption, and once they have sufficient energy, they strike more valence band electrons. This process is repeated as long as there is a sufficiently strong laser electromagnetic field, resulting in a so-called electron avalanche.

(2) The carrier lattice is thermalized. After carrier excitation, electrons and holes are redistributed in the conduction and valence bands by carrier-to-carrier and carrier-to-carrier scattering. This requires about several hundred femtoseconds. The carrier-carrier does not change the total energy or number of carriers of the excited carrier system. In carrier-phonon scattering, free carriers lose or gain energy by emitting or absorbing phonons. Although carrier-phonon scattering does not change the number of carriers, the total energy of the carrier system is reduced because spontaneous phonon emission transfers energy into the lattice. In semiconductors, carrier-carrier scattering and carrier-phonon scattering occur simultaneously within the first few hundred femtoseconds after excitation. Because the energy carried by the emitted phonons during carrier-phonon scattering is very small, the carrier system and lattice system are initially in a non-thermal equilibrium state, requiring many scattering processes to reach thermal equilibrium states, which require from a few picoseconds to tens of picoseconds.

(3) Carrier removal. Once the carriers and lattice reach equilibrium, the material is at a well-defined temperature. Although the carriers have the same temperature as the crystal lattice, the number of free carriers is excessive compared to that at the time of thermal equilibrium. Excess carriers are removed by recombination of electrons and holes or by diffusion out of the excitation region. The compounding process includes both radiative compounding and non-radiative compounding processes. During radiative recombination, as opposed to photoexcitation, excess carrier energy is released in the form of photons. Non-radiative recombination processes include auger recombination, defect recombination, and surface recombination. For silicon, germanium and other indirect bandgap semiconductors, auger recombination dominates during recombination. In auger recombination, an electron and a hole recombine, and the excess energy excites a higher electron in the conduction band, which reduces carrier density as with other recombination mechanisms. However, it keeps the total energy of the free carrier system constant while the average energy of the remaining carriers increases. Carrier diffusion simply removes carriers from the sample region where they were initially excited and does not reduce the total number of free carriers in the material.

(4) Thermal effects and changes in lattice structure. When the free carriers and lattice reach equilibrium temperature and excess free carriers are removed, the material is essentially the same as the material heated by conventional means. The material reaches an equilibrium temperature within a few picoseconds after laser irradiation, but longer time is required to remove excess carriers. If the lattice temperature exceeds the melting point or boiling point, melting or vaporization may occur, but not on the picosecond timescale. If no phase change occurs, the temperature will revert to ambient on the microsecond time scale. If melting or vaporization occurs, resolidification or liquefaction occurs when the temperature is below the melting or boiling point, respectively, but the material does not necessarily return to its original structure or phase.

Therefore, to achieve non-thermal melting, it is desirable that the carriers and crystal lattice have not yet reached a thermal equilibrium state. Since the scattering process required to reach thermal equilibrium typically takes up to several picoseconds to tens of picoseconds, it may be advantageous to control the laser duration to within one picosecond (ps), more advantageously to control the laser duration to be on the order of femtoseconds (less than one picosecond, for example, in the range of several femtoseconds to hundreds of femtoseconds). Such a laser beam having a duration on the order of femtoseconds is referred to herein as a femtosecond laser beam.

In some embodiments, the femtosecond laser beam is provided by a femtosecond laser. The femtosecond laser can be configured, for example, to generate extremely short femtosecond-order pulses (pulse widths on the order of femtoseconds, i.e., less than one picosecond, typically between a few femtoseconds and a few hundred femtoseconds). In some embodiments, the second portion of the semiconductor substrate may be pulsed with a femtosecond laser beam. By way of example, the pulse width of the femtosecond laser beam may be set to be between 50fs and 150fs, for example, about 100fs. In some embodiments, the pulse frequency of the femtosecond laser beam may be configured such that the non-thermal melting of the second portion of the semiconductor substrate continues to occur. That is, the next pulse is irradiated onto the second portion of the semiconductor before the non-thermal melting process by the previous pulse is completed, thereby ensuring a good non-thermal melting effect. Specifically, the pulse frequency of the femtosecond laser beam may be set to be greater than 1MHz, for example.

Taking a SiC semiconductor substrate as an example, when a femtosecond laser beam is irradiated to the SiC surface, dense light-excited high-density plasma can weaken the crystal lattice, improve the mobility of atoms, and does not significantly increase their thermal energy. When about ten percent of the valence electrons are excited to the conduction band, the bond energy between crystal lattices is weakened under the action of plasma, the ion kinetic energy is increased, and the ions can drift greatly from the initial position, so that permanent structural change is caused. According to observation, siC shows a molten state within hundreds of femtoseconds after laser irradiation. This non-thermal melting is accompanied by cleavage of part of the carbon-silicon bonds of the laser-irradiated region, so that the number of carbon-silicon bonds that the laser-irradiated region needs to break during the subsequent oxidation is reduced and thus has an increased oxidation rate. In contrast, if a pulse laser beam (e.g., picosecond laser beam) having a pulse width on the order of picosecond or more is selected, according to observations, the irradiated region of SiC during irradiation undergoes a thermal melting process, carbon-silicon bonds are not broken but bond lengths of the carbon-silicon bonds are elongated by about fifteen percent, and in such a laser irradiation process having a large pulse width, the heat affected zone range of the inside of SiC in the laser irradiation direction is large and the irradiation zone modification process is severe, which is unfavorable for the growth of the subsequent oxide layer.

In addition, the wavelength of the femtosecond laser beam may be determined based on the band gap width of the semiconductor substrate. In some embodiments, the wavelength of the femtosecond laser beam may be selected such that the semiconductor substrate preferentially performs single photon absorption. For example, for a SiC semiconductor substrate, the wavelength of the femtosecond laser beam may be selected to be 248nm. Of course, laser wavelengths that allow multiphoton absorption of the semiconductor substrate are also feasible, but may require increased laser intensity.

In some embodiments, step S104 may be performed under an inert gas (such as, but not limited to, nitrogen, helium, etc.) atmosphere, or may be performed under a vacuum environment. This is to avoid water oxygen and keep clean, preventing the molten portion of the semiconductor substrate from being doped with impurity particles during the laser treatment process.

Still referring to fig. 3E, in some embodiments, the femtosecond laser beam 205 is configured to illuminate in a direction parallel to the depth direction (z-direction) of the trench 204. In other embodiments, the femtosecond laser beam 205 may also be configured to illuminate at an angle relative to the z-direction. In some examples, such an angle is no more than 15 degrees, or no more than 10 degrees, or no more than 5 degrees.

In some embodiments, the irradiation region of the femtosecond laser beam 205 is configured to cover the trench 204 in the width direction (x direction) of the trench 204. As already mentioned above, the hard mask layer 202 can protect the thin layer located near the upper surface of the semiconductor substrate 201 thereunder from melting even under the irradiation region of the femtosecond laser beam 205, which can make the requirement for the spot size of the femtosecond laser beam 205 less strict as long as the coverage of the trench 204 in the width direction (x direction) of the trench 204 is ensured, which can also eliminate the need to scan the femtosecond laser beam in the x direction or to increase the femtosecond laser beam.

If the irradiation region of the femtosecond laser beam 205 (which may be formed by connecting irradiation regions of a plurality of femtosecond laser beams) is large enough to cover the entirety of the second portion 2011 of the semiconductor substrate 201, the second portion 2011 of the semiconductor substrate 201 may be simultaneously processed. But this is subject to limitations, such as the second portion 2011 of the applicable semiconductor substrate 201 not being too wide and/or too long, requiring an excessive number of combinations of lasers, etc. Thus, a manner of scanning the femtosecond laser beam can be adopted. In some embodiments, illuminating the second portion 2011 of the semiconductor substrate 201 with the femtosecond laser beam 205 may include causing a single femtosecond laser beam or multiple femtosecond laser beams to scan the second portion 2011 of the semiconductor substrate 201 in a scan direction parallel to a length direction (y-direction) of the trench 204. A preset dwell time may be set for each scanning location to ensure that sufficient non-thermal melting of the locations occurs. In some embodiments, the preset dwell time may be on the order of milliseconds, for example, between a few milliseconds and a few hundred milliseconds. By scanning the femtosecond laser beam, a wider and/or larger second portion of the semiconductor substrate can be effectively applied, and also a case where the same semiconductor substrate has a plurality of second portions requiring a non-thermal melting process (e.g., a plurality of trenches 204 are present), and the number of lasers used can be reduced.

In some embodiments, when a single femtosecond laser beam is caused to scan the second portion 2011 of the semiconductor substrate 201 in the scanning direction, a previous irradiation region and a next irradiation region of the single femtosecond laser beam partially overlap each other in the scanning direction. For example, as shown in fig. 4A, the femtosecond laser beam 205 is a single femtosecond laser beam, where an overlap region 2500 exists between the upper irradiation region 250 and the next irradiation region 250' in the scanning direction. By providing the overlapping region, the time during which each position is subjected to the laser treatment can be equivalently prolonged.

In some embodiments, when the plurality of femtosecond laser beams are caused to scan the second portion 2011 of the semiconductor substrate 201 in the scanning direction, irradiation regions of each adjacent two of the plurality of femtosecond laser beams partially overlap each other in the scanning direction. For example, as shown in fig. 4B, the femtosecond laser beam 205 includes a femtosecond laser beam 251 and a femtosecond laser beam 252, and when the second portion 2011 of the semiconductor substrate 201 is scanned, an irradiation region of the adjacent femtosecond laser beam 251 and the femtosecond laser beam 252 has an overlapping region 2500' in the scanning direction. By providing the overlapping region, the strength of each position subjected to the laser treatment can be equivalently enhanced.

Further, in order to promote non-thermal melting of the second portion of the semiconductor substrate, it may be required that a ratio of a non-thermal melting process energy contribution of the second portion of the semiconductor substrate to a thermal melting process energy contribution of the second portion of the semiconductor substrate exceeds a preset ratio during irradiation of the femtosecond laser beam. In some examples, the preset ratio may be determined based on a value of a ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution at a maximum slope of a trend of the laser parameter of the femtosecond laser beam. For example, it is possible to determine a trend of a ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution with respect to the intensity of the femtosecond laser beam in a case where the wavelength of the femtosecond laser beam is fixed, and determine a preset ratio based on a ratio value at a maximum slope of the trend of the change. If the femtosecond laser beam is a pulsed femtosecond laser beam, a variation trend of a ratio of non-thermal melting process energy contribution to thermal melting process energy contribution with an energy density of the pulsed femtosecond laser beam can be determined under a certain wavelength and pulse width of the pulsed femtosecond laser beam, and a preset ratio is determined based on a ratio value at a maximum slope of the variation trend. Of course, the preset ratio may be a ratio corresponding to the maximum slope, or may be any ratio within a desired range determined based on the maximum slope.

The non-thermal melting process energy contribution may be determined based on a carrier concentration in the semiconductor substrate and a band gap width of the semiconductor substrate under irradiation of the femtosecond laser beam. Specifically, for example, the non-thermal melting process energy contribution may be represented as N _CE_g, where N _C is the carrier concentration and E _g is the bandgap width of the semiconductor substrate. The bandgap width generally varies with carrier concentration and lattice temperature. For example, in the case where the carrier concentration of 4H-SiC is 1X 10 ¹²/cm³, the band gap width E _g can be expressed asWherein T _L is the lattice temperature.

The thermal melting process energy contribution may be determined based on the density of the semiconductor substrate, the lattice heat capacity of the semiconductor substrate, the melting point of the semiconductor substrate associated with the concentration of carriers in the semiconductor substrate under irradiation of the femtosecond laser beam. Specifically, for example, the heat melting process energy contribution may be represented as ρc _L(T_Lm-T₀), where ρ is the density of the semiconductor substrate, C _L is the lattice heat capacity of the semiconductor substrate, T _Lm is the melting point of the semiconductor substrate (or lattice temperature at this time) at a carrier concentration of N _C, and T ₀ is the lattice temperature at room temperature (typically 300K).

The ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution can be controlled by controlling the laser parameters of the femtosecond laser beam, so that the degree of non-thermal melting of the semiconductor substrate is controlled. In some embodiments, the laser parameters may include intensity, wavelength, or a combination thereof. When the femtosecond laser beam is a pulsed femtosecond laser beam, the intensity of the femtosecond laser beam can be determined by a pulse width and an energy density.

In particular, the decay of the femtosecond laser beam along the propagation direction z inside the material can be expressed as

Therefore, the intensity I of the femtosecond laser beam can be expressed as

Where α ₁ is a single photon absorption coefficient, β is a two photon absorption coefficient, α _FCA is a free carrier absorption coefficient, z is a spatial coordinate, and I ₀ is a surface (z=0) laser intensity. If the pulsed femtosecond laser beam is modeled as a Gaussian beam, the temporal and spatial evolution of I ₀ can be expressed as

Where R is the off-axis radial distance (distance between a point in the femtosecond laser beam and the central axis), t is time, R is reflectivity, J is energy density, τ _p is pulse width, and t ₀＝3τ_p.

For example, for indirect bandgap semiconductors (e.g., silicon carbide), the photon absorption process can only occur with the help of phonons, and therefore the absorption coefficients α ₁, β, and α _FCA are dependent on lattice temperature. In addition, α _FCA also depends on the carrier concentration, the greater the absorption coefficient. Alpha _FCA can be expressed asWhere N _C is carrier concentration, e is electron charge, c ₀ is light velocity, λ is wavelength, m _eff is electron effective mass, ε ₀ is vacuum dielectric constant, N is refractive index, μ (T) is electron mobility dependent on temperature.

It should be noted that during laser irradiation, the change in the free carrier concentration affects not only α _FCA but also the reflectance R. It is generally assumed that the reflectivity is dependent only on the lattice temperature when simulating the irradiation, which, although simplifying the calculation process, may affect the accuracy of the simulation result. For this purpose, a Drude model may be used, taking into account the effect of the instantaneous carrier concentration on the reflectivity, the reflectivity under this model framework being expressed as

Where k is the extinction coefficient, ε is the dielectric constant of the semiconductor substrate and Re (ε) is the real part of ε. The carrier concentration N _C affects the dielectric constant epsilon, and thus the extinction coefficient k and the refractive index N, and ultimately the reflectivity R.

In some embodiments, the laser parameter of the femtosecond laser beam 205 is configured to be not less than a first laser parameter threshold at which the second portion 2011 of the semiconductor substrate 201 begins to melt. That is, during irradiation of the femtosecond laser beam 205 with the first laser parameter threshold, the sum of the non-thermal melting process energy contribution and the thermal melting process energy contribution provides exactly the amount of heat that the semiconductor substrate 201 needs to absorb from room temperature to the melting point. Additionally, in some embodiments, the laser parameters of the femtosecond laser beam 205 are also configured to be no greater than a second laser parameter threshold at which the second portion 2011 of the semiconductor substrate 201 is completely melted. That is, during irradiation of the femtosecond laser beam 205 with the second laser parameter threshold, the sum of the non-thermal melting process energy contribution and the thermal melting process energy contribution provides exactly the amount of heat that the semiconductor substrate 201 needs to absorb from room temperature to the melting point and the latent heat of fusion of the semiconductor substrate 201. It will be appreciated that the laser parameter configuration of the femtosecond laser beam 205 is equally applicable to other femtosecond laser beams as will be described below. Further, in order to enable non-thermal melting of the semiconductor substrate as much as possible to increase the thickness of an oxide layer formed later in the thermal oxidation process, the laser parameters of the femtosecond laser beam are also configured to make the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution as large as possible.

In some embodiments, the first laser parameter threshold and the second laser parameter threshold are determined based on a carrier number density balance, a carrier system energy conservation, and a lattice system energy balance of the semiconductor substrate. In particular, for example, carrier number density balance requirements of semiconductor substrates

Energy conservation requirements of carrier systems of semiconductor substrates

Lattice system energy balance requirements for semiconductor substrates

Second part onset melting requirement of semiconductor substrate

ρC_L(T_m-T₀)＝ρC_L(T_Lm-T₀)+N_CE_g (4)

The second partial complete melting requirement of the semiconductor substrate

ρC_L(T_m-T₀)+L_m＝ρC_L(T_Lm-T₀)+N_CE_g (5)

Wherein N _C is carrier concentration, t is time, alpha ₁ is single photon absorption coefficient, I is intensity of femtosecond laser beam, hν is photon energy corresponding to wavelength of femtosecond laser beam, beta is two photon absorption coefficient, delta is collision ionization coefficient, gamma is Auger recombination coefficient, U _C is total energy of carrier system, Alpha _FCA is the free carrier absorption coefficient, k _B is the boltzmann constant, τ _C is the carrier-lattice relaxation time, T _C is the carrier temperature, T _L is the lattice temperature, U _L is the total energy of the lattice system, z is the spatial coordinates, κ _L is the lattice thermal conductivity, ρ is the density of the semiconductor substrate, C _L is the lattice thermal capacity, T _m is the melting point of the semiconductor substrate at room temperature, T ₀ is the lattice temperature at room temperature, T _Lm is the melting point of the semiconductor substrate at carrier concentration N _C (or, Lattice temperature at this time), E _g is the band gap width of the semiconductor substrate, and L _m is the latent heat of fusion of the semiconductor substrate.

The laser interaction with the semiconductor results in the generation of unbalanced carriers and increases the carrier temperature and lattice temperature. In equation (1), the first two terms on the right side of the equal sign describe a single photon absorption process and a two photon absorption process, and the third and fourth terms describe a collision ionization process and an auger recombination process. It will be appreciated that more photon absorption processes are similarly contemplated.

The total energy of the carrier system is regulated and controlled by a laser absorption process and a transport process. In equation (2), the first term on the right of the equal sign describes the energy source that the carrier system obtains through a single photon absorption process and a free carrier absorption process, the second term is the energy source obtained through two photon absorption, and the third term is the energy transfer between the carrier system and the lattice system.

Laser pulse energy cannot be directly transferred to the lattice system, from which lattice system energy is obtained by a carrier-lattice relaxation process. In equation (3), the first term on the right of the equal sign is the lattice system energy transfer term, and the second term is the energy exchange between the lattice system and the carrier system.

If the optical phonon and the acoustic phonon are assumed to be in thermodynamic equilibrium, the lattice system can be considered as a single thermodynamic system. Under the above assumption, the carrier system and lattice system energy can be described as U _C＝N_CE_g+C_CT_C and U _L＝C_LT_L, respectively, where C _C is the carrier heat capacity.

In equations (4) and (5), the first term on the right of the equal sign is the heat melting process energy contribution, and the second term on the right of the equal sign is the non-heat melting process energy contribution.

For example, in the case where the femtosecond laser beam wavelength (corresponding to v) is fixed, by combining the above equations (1) - (5), the femtosecond laser beam intensity when equation (4) is solved as the first laser intensity threshold, the femtosecond laser beam intensity when equation (5) is solved as the second laser intensity threshold, and then the intensity of the femtosecond laser beam can be controlled between the first laser intensity threshold and the second laser intensity threshold, for example, an intensity value within this range such that the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution is maximized can be selected as the femtosecond laser beam intensity to be applied.

For example, for a pulsed femtosecond laser beam, the femtosecond laser beam energy density (corresponding J) when equation (4) is established may be solved as a first laser energy density threshold by combining the above equations (1) - (5) with the femtosecond laser beam wavelength (corresponding v) and the pulse width (τ _p) fixed, the femtosecond laser beam energy density when equation (5) is established may be solved as a second laser energy density threshold, and then the energy density of the pulsed femtosecond laser beam may be controlled between the first laser energy density threshold and the second laser intensity energy density, for example, an energy density value within this range such that the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution is maximized may be selected as the energy density of the pulsed femtosecond laser beam to be applied.

Referring back to fig. 2, the method 100 further includes: at step S106, after the irradiation of the femtosecond laser beam is completed, the semiconductor substrate is subjected to a thermal oxidation process such that the second portion of the semiconductor substrate forms an oxide layer.

For example, referring to fig. 3F, the hard mask layer 202 may be removed after the irradiation of the femtosecond laser beam 205 is completed and before the thermal oxidation treatment is performed on the semiconductor substrate 201.

As shown in fig. 3G, after the thermal oxidation process is performed on the semiconductor substrate 201, an oxide layer 206 is formed on the surface of the semiconductor substrate 201, including an oxide layer formed by the second portion 2011 and the fourth portion 2012 of the semiconductor substrate 201. As shown in fig. 3G, it can be seen that, even in the perfect crystal structure of the semiconductor substrate 201, the oxidation rate of the crystal plane where the bottom surface of the trench 204 is located is lower than that of the crystal plane where the side surface of the trench 204 is located, since the second portion 2011 of the semiconductor substrate 201 is subjected to the non-thermal melting treatment, the thickness d1 of the oxide layer formed can be close to or even greater than the thickness d2 of the oxide layer formed by the other portions (e.g., the fourth portion 2012) which are not subjected to the non-thermal melting treatment.

In addition, the thickness of the oxide layer formed on the semiconductor substrate can be controlled by controlling the degree to which the semiconductor substrate is non-thermally melted. For example, laser parameters of the femtosecond laser beam (such as intensity (or pulse width, energy density, etc. in the case of a pulsed femtosecond laser beam), wavelength, etc.), and irradiation parameters of the femtosecond laser beam (such as irradiation duration, pulse frequency in the case of a pulsed femtosecond laser beam, preset dwell time of scanning in the case of a scanned femtosecond laser beam, spot overlapping area, etc.), can be used to control the extent to which non-thermal melting of the semiconductor substrate occurs.

In some embodiments, the laser parameters of the femtosecond laser beam may be set based on a relationship of a desired thickness of the oxide layer to be formed by the second portion of the semiconductor substrate with respect to a first reference thickness and a second reference thickness, wherein the first reference thickness is a thickness of the oxide layer to be formed by the second portion of the semiconductor substrate with the femtosecond laser beam irradiated with a first laser parameter threshold, and the second reference thickness is a thickness of the oxide layer to be formed by the second portion of the semiconductor substrate with the femtosecond laser beam irradiated with a second laser parameter threshold, thereby achieving flexible setting of the oxide layer thickness of the semiconductor substrate to meet different requirements of an actual semiconductor manufacturing process.

Additionally, in some embodiments, the method 100 may further comprise: a gate is formed over the oxide layer. For example, as shown in fig. 3H, a layer of conductive material may be deposited as a gate 207 over the oxide layer 206 within the trench 204. The excess conductive material layer and oxide layer may be removed by means such as, but not limited to, chemical mechanical polishing. As non-limiting examples, the conductive material of the gate 207 may include one or more of the following: polysilicon, doped polysilicon (such as polysilicon doped with phosphorus ions, polysilicon doped with arsenic ions, polysilicon doped with antimony ions), metals (e.g., copper), and the like. Here, the oxide layer 206 provides a gate oxide layer for the gate electrode 207.

In some embodiments, the method 100 may further comprise: one of a source region and a drain region is formed in a fifth portion of the semiconductor substrate at one side of the trench top, and the other of the source region and the drain region is formed in a sixth portion of the semiconductor substrate at the other side of the trench top. For example, as shown in fig. 3H and 3I, the source region 208 is formed in the fifth portion 2013 of the semiconductor substrate 201 at one side of the top of the trench 204 and the drain region 209 is formed in the sixth portion 2014 of the semiconductor substrate 201 at the other side of the top of the trench 204 by means such as an ion implantation process. Of course, in other embodiments, the drain region 209 may also be formed in the fifth portion 2013 of the semiconductor substrate 201, while the source region 208 is formed in the sixth portion 2014 of the semiconductor substrate 201. In the transistor structure shown in fig. 3I (herein referred to as a first type transistor structure), the channel region is located in the active region of the semiconductor substrate 201 between the source region 208 and the drain region 209 and is at least partially defined by the trench 204. When the transistor is on, a conductive channel will be formed in the channel region extending at least partially along the oxide layer 206 to connect the source region 208 and the drain region 209. Due to the presence of the trench 204, the length of the conductive channel is increased compared to the lateral (x-direction) distance between the source region 208 and the drain region 209, thereby facilitating the avoidance or improvement of short channel effects when the transistor is miniaturized (i.e., the lateral distance between the source region 208 and the drain region 209 is shortened).

Alternatively, in some embodiments, the method 100 may further comprise: one of a source region and a drain region is formed in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and the other of the source region and the drain region is formed in a seventh portion of the semiconductor substrate located under the trench. For example, as shown in fig. 3H and 3J, the source region 208 is formed in the fifth and sixth portions 2013 and 2014 of the semiconductor substrate 201 and the drain region 209 is formed in the seventh portion 2015 of the semiconductor substrate 201 under the trench 204 by means such as an ion implantation process. Of course, in other embodiments, the drain region 209 may also be formed in the fifth and sixth portions 2013, 2014 of the semiconductor substrate 201, while the source region 208 is formed in the seventh portion 2015 of the semiconductor substrate 201. In the transistor structure shown in fig. 3J (referred to herein as a second type transistor structure), the channel region is located in the active region of the semiconductor substrate 201 between the source region 208 and the drain region 209 and is at least partially defined by the trench 204. When the transistor is on, a conductive channel will be formed in the channel region extending at least partially along the oxide layer 206 to connect the source region 208 and the drain region 209.

In addition, according to the thickness requirement of the oxide layer in different areas, corresponding femtosecond laser irradiation is respectively carried out on corresponding parts of the semiconductor substrate adjacent to different parts of the groove, and the thickness of the oxide layer formed by the corresponding parts is controlled by controlling the non-thermal melting degree of the corresponding parts.

Assuming that the femtosecond laser beam used to irradiate the second portion of the semiconductor substrate in step S104 is the first femtosecond laser beam, in some embodiments, the method 100 may further include: irradiating a fourth portion of the semiconductor substrate adjacent to a third portion (e.g., a side surface) of the trench with a second femtosecond laser beam before performing a thermal oxidation process on the semiconductor substrate such that the fourth portion of the semiconductor substrate is non-thermally melted; after the irradiation of the first and second femtosecond laser beams is completed, the semiconductor substrate is subjected to a thermal oxidation process such that the second and fourth portions of the semiconductor substrate form an oxide layer.

For example, in the case where the oxidation rate of the crystal plane where the first portion of the trench is located is lower than the oxidation rate of the crystal plane where the third portion of the trench is located, the irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam may be configured such that the depth of the region where the non-thermal melting occurs in the second portion of the semiconductor substrate is greater than the depth of the region where the non-thermal melting occurs in the fourth portion of the semiconductor substrate. In this way, the thickness of the subsequent oxide layer formed by the second portion of the semiconductor substrate may be close to or even greater than the thickness of the oxide layer formed by the fourth portion of the semiconductor substrate. Specifically, any thickness of the oxide layer desired to be formed by the second and fourth portions of the semiconductor substrate, respectively, may be achieved by controlling the laser parameters and irradiation parameters of the first and second femtosecond laser beams, respectively, to adjust the degree of non-thermal melting of the second and fourth portions of the semiconductor substrate.

Referring to fig. 5, fig. 5 shows a schematic cross-sectional view of a semiconductor device corresponding to respective steps of implementing a non-limiting example process for manufacturing a semiconductor device. Although fig. 5 illustrates the foregoing second type transistor structure as an example, the teachings thereof may be similarly applied to various transistor structures such as the foregoing first type transistor structure or other semiconductor device structures. As shown in (a) to (d) of fig. 5, a trench is formed in a semiconductor substrate by the method as mentioned above. As shown in fig. 5 (e), a second portion of the semiconductor substrate adjacent to the bottom surface of the trench is irradiated with a first femtosecond laser beam 2051 to cause non-thermal melting thereof. As shown in fig. 5 (f), a fourth portion of the semiconductor substrate adjacent to the side surfaces of the trench is irradiated with a second femtosecond laser beam 2052 to cause non-thermal melting thereof. It will be appreciated that although the irradiation of the first and second femtosecond laser beams 2051 and 2052 is described with (f) and (g) of fig. 5, respectively, the irradiation of the second femtosecond laser beam 2051 may be at least partially parallel or serial to the irradiation of the first femtosecond laser beam 2051. Specifically, the irradiation of the first femtosecond laser beam 2051 and the irradiation of the second femtosecond laser beam 2052 are configured such that the depth of the region where the non-thermal melting occurs in the second portion of the semiconductor substrate is greater than the depth of the region where the non-thermal melting occurs in the fourth portion of the semiconductor substrate. For example, the configuration of the first and second femtosecond laser beams 2051 and 2052 may satisfy one or more of the following: the irradiation duration of the first femtosecond laser beam 2051 is longer than the irradiation duration of the second femtosecond laser beam 2052; the intensity of the first femtosecond laser beam 2051 is greater than the intensity of the second femtosecond laser beam 2052 (for example, in the case where both the first and second femtosecond laser beams 2051 and 2052 are pulse laser beams and the pulse width is the same, the energy density of the first femtosecond laser beam 2051 is greater than the energy density of the second femtosecond laser beam 2052); the first and second femtosecond laser beams 2051 and 2052 are irradiated in the form of pulses, and the pulse frequency of the first femtosecond laser beam 2051 is greater than that of the second femtosecond laser beam 2052; etc. As shown in (g) of fig. 5, after the irradiation of the first and second femtosecond laser beams 2051 and 2052 is completed, the hard mask layer may be removed. Then, as shown in (h) of fig. 5, the semiconductor substrate is subjected to a thermal oxidation treatment such that the oxide layer thickness d1 formed in the second portion of the semiconductor substrate is greater than the oxide layer thickness d3 formed in the fourth portion of the semiconductor substrate. In addition, it can be understood that since the fourth portion of the semiconductor substrate is irradiated with the second femtosecond laser beam 2052 in fig. 5, the oxide layer thickness d3 formed at the fourth portion of the semiconductor substrate at this time is greater than the oxide layer thickness d2 formed at the fourth portion of the semiconductor substrate not irradiated with the femtosecond laser beam shown in fig. 3G. With continued reference to fig. 5, as shown in fig. 5 (h), the gate, source and drain regions may be further prepared to form a second type transistor structure.

In some embodiments, the method 100 further comprises: performing a Pull-back (Pull-back) process on the hard mask layer before performing the thermal oxidation process on the semiconductor substrate to expose one or both of a fifth portion and a sixth portion of the semiconductor substrate respectively located on both sides of the trench top; irradiating the one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam such that the one or both of the fifth portion and the sixth portion of the semiconductor substrate is non-thermally melted; and performing a thermal oxidation treatment on the semiconductor substrate after the irradiation of the first and third femtosecond laser beams is completed, such that the second portion and the one or both of the fifth and sixth portions of the semiconductor substrate form an oxide layer. Additionally, in some embodiments, the third femtosecond laser beam is the same as the first femtosecond laser beam. The irradiation of the third femtosecond laser beam and the irradiation of the first femtosecond laser beam (and the irradiation of the second femtosecond laser beam, if any) may be at least partially parallel or serial. The irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that a depth of a region where the non-thermal melting occurs in the second portion of the semiconductor substrate is equal to a depth of a region where the non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate. Of course, any thickness of the oxide layer desired to be formed by the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion of the semiconductor substrate may be achieved by controlling the laser parameters and the irradiation parameters of the first and third femtosecond laser beams, respectively, to adjust the degree of non-thermal melting of the second portion of the semiconductor substrate and the one or both of the fifth and sixth portions, respectively.

Referring to fig. 6, fig. 6 shows a schematic cross-sectional view of a semiconductor device corresponding to respective steps of implementing a non-limiting example process for manufacturing a semiconductor device. Although fig. 6 illustrates the foregoing first type transistor structure and second type transistor structure as examples, the teachings thereof are similarly applicable to a variety of other transistor structures or other semiconductor device structures. As shown in (a) to (d) of fig. 6, a trench 204 is formed in a semiconductor substrate by the method as mentioned above, and a second portion of the semiconductor substrate adjacent to the bottom surface of the trench is irradiated with a first femtosecond laser beam 2051. As shown in fig. 6 (e), a pullback process is performed on the hard mask layer to expose fifth and sixth portions of the semiconductor substrate respectively located at both sides of the trench top. As shown in fig. 6 (f), the fifth and sixth portions of the semiconductor substrate are irradiated with a third femtosecond laser beam 2053 identical to the first femtosecond laser beam 2051 to cause non-thermal melting thereof. It will be appreciated that although the irradiation processes of the first and third femtosecond laser beams 2051 and 2053 are described with (d) and (f) of fig. 6, respectively, the irradiation of the third femtosecond laser beam 2053 may be at least partially parallel or serial to the irradiation of the first femtosecond laser beam 2051. As shown in fig. 6 (g), after the irradiation of the first and third femtosecond laser beams 2051 and 2053 is completed, the hard mask layer is removed. Then, as shown in (h) of fig. 6, the semiconductor substrate is subjected to a thermal oxidation treatment such that the oxide layer thickness d4 formed by each of the fifth and sixth portions of the semiconductor substrate is substantially equal to the oxide layer thickness d1 formed by the second portion 2011 of the semiconductor substrate 201 and is greater than the oxide layer thickness d5 formed at the horizontal surface of the semiconductor substrate previously under the hard mask layer, which has not been irradiated with the first and third femtosecond laser beams 2051 and 2053, and is also greater than the oxide layer thickness d3 formed at the vertical surface of the semiconductor substrate, which has not been subjected to the femtosecond laser treatment. By providing thick oxide layers at both the corners of the trench top and the trench bottom, the blocking voltage of the semiconductor device can be further increased, improving the electrical performance.

Further, the oxide layer formed in (h) of fig. 6 may be utilized as a gate oxide layer to form transistor structures such as the aforementioned first-type transistor structure and second-type transistor structure. For example, as shown in (i 1) of fig. 6, a gate electrode is formed over the oxide layer in the trench of the semiconductor substrate, one of a source region and a drain region is formed in an eighth portion of the semiconductor substrate located at a side of the fifth portion remote from the trench and a ninth portion of the semiconductor substrate located at a side of the sixth portion remote from the trench, and the other of the source region and the drain region is formed in a seventh portion of the semiconductor substrate located under the trench. Alternatively, as shown in (i 2) of fig. 6, a gate electrode is formed over the oxide layer in the trench of the semiconductor substrate, one of a source region and a drain region is formed in the eighth portion of the semiconductor substrate, and the other of the drain region and the source region is formed in the ninth portion of the semiconductor substrate. The transistor structures shown in (I1) and (I2) of fig. 6 can realize a further extended conduction channel length than the transistor structures shown in fig. 3J and 3I, respectively.

The present disclosure also provides, in another aspect, a semiconductor device manufactured according to the method of any one of the embodiments of the present disclosure. In some embodiments, the semiconductor device includes a MOSFET, wherein the oxide layer is configured to provide a gate oxide layer of the MOSFET. Semiconductor devices fabricated according to the teachings of the present disclosure have highly reliable oxide layers and thus improved electrical performance.

The words "left", "right", "front", "rear", "top", "bottom", "upper", "lower", "high", "low", and the like in the description and in the claims, if present, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. For example, when the device in the figures is inverted, features that were originally described as "above" other features may be described as "below" the other features. The device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the relative spatial relationship will be explained accordingly.

In the description and claims, an element is referred to as being "on," "attached to," connected to, "coupled to," or "contacting" another element, and the like, the element may be directly on, attached to, connected to, coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly attached to," directly connected to, "directly coupled to," or "directly contacting" another element, there are no intervening elements present. In the description and claims, a feature being disposed "adjacent" to another feature may refer to a feature having a portion that overlaps with, or is located above or below, the adjacent feature.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be replicated accurately. Any implementation described herein by way of example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited by any expressed or implied theory presented in the technical field, background, brief summary or the detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation due to design or manufacturing imperfections, tolerances of the device or element, environmental effects and/or other factors. The word "substantially" also allows for differences from perfect or ideal situations due to parasitics, noise, and other practical considerations that may be present in a practical implementation.

In addition, for reference purposes only, the terms "first," "second," and the like may also be used herein, and are thus not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

In this disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/setting," "installing/assembling," and/or "ordering" an object, etc.

As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Those skilled in the art will recognize that the boundaries between the above described operations are merely illustrative. The operations may be combined into a single operation, the single operation may be distributed among additional operations, and the operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in other various embodiments. Other modifications, variations, and alternatives are also possible. Aspects and elements of all of the embodiments disclosed above may be combined in any manner and/or in combination with aspects or elements of other embodiments to provide a number of additional embodiments. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The embodiments disclosed herein may be combined in any desired manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications might be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising:

Providing a semiconductor substrate, wherein a groove is formed in the semiconductor substrate;

Irradiating a second portion of the semiconductor substrate adjacent to the first portion of the trench with a femtosecond laser beam such that non-thermal melting of the second portion of the semiconductor substrate occurs; and

After the irradiation of the femtosecond laser beam is completed, the semiconductor substrate is subjected to a thermal oxidation treatment such that the second portion of the semiconductor substrate forms an oxide layer.

2. The method of claim 1, wherein in a perfect crystal structure of the semiconductor substrate, an oxidation rate of a crystal plane of the trench in which the first portion is located is lower than an oxidation rate of a crystal plane of the trench in which a third portion different from the first portion is located.

3. The method of claim 2, wherein the femtosecond laser beam is a first femtosecond laser beam, the method further comprising:

Irradiating a fourth portion of the semiconductor substrate adjacent to the third portion of the trench with a second femtosecond laser beam before performing thermal oxidation treatment on the semiconductor substrate such that non-thermal melting of the fourth portion of the semiconductor substrate occurs;

After the irradiation of the first and second femtosecond laser beams is completed, performing a thermal oxidation process on the semiconductor substrate such that the second and fourth portions of the semiconductor substrate form an oxide layer,

Wherein the irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam are configured such that a depth of a region where non-thermal melting occurs in the second portion of the semiconductor substrate is greater than a depth of a region where non-thermal melting occurs in the fourth portion of the semiconductor substrate.

4. A method according to claim 3, wherein at least one of the following is satisfied:

the irradiation duration of the first femtosecond laser beam is longer than the irradiation duration of the second femtosecond laser beam; or alternatively

The intensity of the first femtosecond laser beam is greater than the intensity of the second femtosecond laser beam; or alternatively

The first and second femtosecond laser beams are irradiated in a pulse form, and a pulse frequency of the first femtosecond laser beam is greater than a pulse frequency of the second femtosecond laser beam.

5. The method of claim 2, wherein the first portion of the trench is a bottom surface of the trench and the third portion of the trench is a side surface of the trench.

6. The method of claim 1, wherein the semiconductor substrate comprises silicon carbide.

7. The method of claim 1, wherein a ratio of a non-thermal melting process energy contribution of the second portion of the semiconductor substrate to a thermal melting process energy contribution of the second portion of the semiconductor substrate exceeds a preset ratio during the irradiation of the femtosecond laser beam.

8. The method of claim 7, wherein the preset ratio is determined based on a value of a ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution at a maximum slope of a trend thereof with a laser parameter of the femtosecond laser beam.

9. The method of claim 1, wherein a laser parameter of the femtosecond laser beam is configured to be not less than a first laser parameter threshold at which the second portion of the semiconductor substrate begins to melt.

10. The method of claim 9, wherein a laser parameter of the femtosecond laser beam is configured to be no greater than a second laser parameter threshold at which the second portion of the semiconductor substrate is completely melted.

11. The method of claim 10, wherein the laser parameters of the femtosecond laser beam are set based on a relationship of a desired thickness of an oxide layer to be formed by the second portion of the semiconductor substrate relative to a first reference thickness that is a thickness of an oxide layer to be formed by the second portion of the semiconductor substrate if the femtosecond laser beam is irradiated with the first laser parameter threshold and a second reference thickness that is a thickness of an oxide layer to be formed by the second portion of the semiconductor substrate if the femtosecond laser beam is irradiated with the second laser parameter threshold.

12. The method of any of claims 8-11, wherein the laser parameters of the femtosecond laser beam include intensity, wavelength, or a combination thereof.

13. The method of claim 1, wherein irradiating the second portion of the semiconductor substrate with the femtosecond laser beam comprises irradiating the second portion of the semiconductor substrate with the femtosecond laser beam in pulses.

14. The method of claim 13, wherein a pulse width of the femtosecond laser beam is set to be between 50fs and 150 fs.

15. The method of claim 13, wherein a pulse frequency of the femtosecond laser beam is configured such that non-thermal melting of the second portion of the semiconductor substrate continues to occur.

16. The method of claim 13, wherein a pulse frequency of the femtosecond laser beam is set to be greater than 1MHz.

17. The method of claim 1, wherein the femtosecond laser beam is configured to be irradiated in a direction parallel to a depth direction of the trench, and an irradiation region of the femtosecond laser beam is configured to cover the trench in a width direction of the trench.

18. The method of claim 1, wherein irradiating the second portion of the semiconductor substrate with the femtosecond laser beam comprises scanning the second portion of the semiconductor substrate with a single femtosecond laser beam or multiple femtosecond laser beams along a scanning direction parallel to a length direction of the trench.

19. The method of claim 18, wherein,

When a single femtosecond laser beam is caused to scan the second portion of the semiconductor substrate in the scanning direction, a previous irradiation region and a next irradiation region of the single femtosecond laser beam partially overlap each other in the scanning direction; or alternatively

When a plurality of femtosecond laser beams are caused to scan the second portion of the semiconductor substrate in the scanning direction, irradiation regions of each adjacent two of the plurality of femtosecond laser beams partially overlap each other in the scanning direction.

20. The method of claim 1, further comprising forming a gate over the oxide layer.

21. The method of claim 20, further comprising:

forming one of a source region and a drain region in a fifth portion of the semiconductor substrate at one side of the trench top, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the trench top; or alternatively

One of a source region and a drain region is formed in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and the other of a source region and a drain region is formed in a seventh portion of the semiconductor substrate located under the trench.

22. The method of claim 1, wherein providing a semiconductor substrate having a trench formed therein comprises:

Forming a hard mask layer on a semiconductor substrate;

Forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate,

Wherein the femtosecond laser beam is a first femtosecond laser beam, the method further comprises:

performing a pullback process on the hard mask layer to expose one or both of a fifth portion and a sixth portion of the semiconductor substrate respectively located on both sides of the trench top before performing a thermal oxidation process on the semiconductor substrate;

irradiating the one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam such that non-thermal melting of the one or both of the fifth portion and the sixth portion of the semiconductor substrate occurs; and

After the irradiation of the first and third femtosecond laser beams is completed, the semiconductor substrate is subjected to a thermal oxidation treatment such that the second portion and the one or both of the fifth and sixth portions of the semiconductor substrate form an oxide layer.

23. The method of claim 22, wherein the irradiation of the first and third femtosecond laser beams is configured such that a depth of a region in the second portion of the semiconductor substrate where non-thermal melting occurs is equal to a depth of a region in the one or both of the fifth and sixth portions of the semiconductor substrate where non-thermal melting occurs.

24. The method of claim 22, further comprising forming a gate over the oxide layer,

And wherein the method further comprises:

Forming one of a source region and a drain region in an eighth portion of the semiconductor substrate at a side of the fifth portion remote from the trench, and forming the other of the source region and the drain region in a ninth portion of the semiconductor substrate at a side of the sixth portion remote from the trench; or alternatively

One of a source region and a drain region is formed in one or both of the eighth portion and the ninth portion of the semiconductor substrate, and the other of a source region and a drain region is formed in a seventh portion of the semiconductor substrate located under the trench.

25. A semiconductor device manufactured by the method according to any one of claims 1 to 24.