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CN118316451B - Analog-to-digital conversion method and circuit of multi-resolution mode - Google Patents

Analog-to-digital conversion method and circuit of multi-resolution mode Download PDF

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Publication number
CN118316451B
CN118316451B CN202410731204.6A CN202410731204A CN118316451B CN 118316451 B CN118316451 B CN 118316451B CN 202410731204 A CN202410731204 A CN 202410731204A CN 118316451 B CN118316451 B CN 118316451B
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mode
sar adc
flash
dac
adc circuit
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CN118316451A (en
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朱朝峰
邓欢
李振涛
戴超雄
唐金波
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Hunan Guliang Microelectronics Co ltd
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Hunan Guliang Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/38—Circuit design at the mixed level of analogue and digital signals

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  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The application relates to an analog-to-digital conversion method and a circuit of a multi-resolution mode, which control a FLASH SAR ADC circuit to be compatible with different analog-to-digital conversion resolutions by providing a brand new multi-resolution mode switching technology based on FLASH SAR ADC circuits: according to the currently set resolution mode, the current working mode of the FLASH SAR ADC circuit can be controlled by the SAR logic control module of the circuit to be switched to the latest selected target resolution mode, such as any one of a high-precision full-differential mode, a medium-precision full-differential mode, a low-precision full-differential mode and a single-ended mode with different resolutions, so that the FLASH SAR ADC circuit performs signal conversion processing according to the newly set target resolution mode in the subsequent analog-to-digital conversion processing, and the aim of greatly reducing the design and production cost of FLASH SAR ADC is fulfilled.

Description

Analog-to-digital conversion method and circuit of multi-resolution mode
Technical Field
The invention belongs to the technical field of analog-to-digital conversion, and relates to an analog-to-digital conversion method and circuit of a multi-resolution mode.
Background
Along with the development of technology, SAR ADC is applied to different products by virtue of low power consumption, simple structure and the like. Hybrid ADC based on SAR ADC is also increasing, wherein FLASH SAR ADC is one of them, which changes the disadvantage that SAR ADC can only be quantized serially by introducing Flash ADC quantized in parallel, so that the speed of ADC is increased. However, FLASH SAR ADC supports only one resolution, and if it is desired to meet the requirements of different occasions, different FLASH SAR ADC circuits need to be designed, which seriously increases the design cost and the production cost, and has a technical problem of high cost.
Disclosure of Invention
Aiming at the problems in the traditional method, the invention provides a multi-resolution mode analog-to-digital conversion method and a multi-resolution mode FLASH SAR ADC circuit, which can greatly reduce the design and production cost of FLASH SAR ADC.
In order to achieve the above object, the embodiment of the present invention adopts the following technical scheme:
In one aspect, an analog-to-digital conversion method of a multi-resolution mode is provided, and the analog-to-digital conversion method is applied to FLASH SAR ADC circuits of the multi-resolution mode, and includes:
acquiring a resolution mode conversion instruction which is currently set;
According to the resolution mode conversion instruction, the control FLASH SAR ADC circuit is switched from the current working mode to a target resolution mode corresponding to the resolution mode conversion instruction;
The control FLASH SAR ADC circuit performs conversion operation of a sampling stage and a quantization stage on an input signal in a target resolution mode, and outputs a final analog-digital conversion result; the target resolution mode comprises a high-precision full-differential mode, a medium-precision full-differential mode, a low-precision full-differential mode or a single-ended mode;
In a high-precision full-differential mode, all capacitors of a DAC in a SAR ADC of a FLASH SAR ADC circuit participate in switching use, and a Flash ADC of the FLASH SAR ADC circuit works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC;
In a medium-precision full-differential mode, one part of capacitors of a DAC in the SAR ADC participate in switching and the other part of capacitors do not participate in switching, and the Flash ADC works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC;
under a low-precision full-differential mode, selecting partial capacitors of a DAC in the SAR ADC to participate in switching, wherein the Flash ADC works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC; the capacitance of the DAC in the SAR ADC which participates in switching is smaller than that of the DAC in the medium-precision full-differential mode;
In the single-ended mode, one part of capacitors of a DAC in the SAR ADC participate in switching and the other part of capacitors do not participate in switching, the Flash ADC works in the single-ended mode and transmits a high-order digital code to a positive-end DAC or a negative-end DAC in the SAR ADC, and unused sampling ends in the Flash ADC and the SAR ADC are kept grounded in the conversion process.
In one embodiment, the Flash ADC is a Flash ADC circuit supporting single-ended and differential modes, and the SAR ADC comprises a fixed bit number or variable bit number SAR ADC circuit.
In one embodiment, the DAC capacitive array of the SAR ADC comprises a capacitive array of one-segment, two-segment, three-segment, or four-segment configuration.
On the other hand, a FLASH SAR ADC circuit with a multi-resolution mode is also provided, which comprises a Flash ADC circuit and a SAR ADC circuit;
When the SAR logic of the SAR ADC circuit acquires a currently set resolution mode conversion instruction, the control FLASH SAR ADC circuit switches from a current working mode to a target resolution mode corresponding to the resolution mode conversion instruction, and then controls the FLASH SAR ADC circuit to perform conversion operation of a sampling stage and a quantization stage on an input signal in the target resolution mode, and outputs a final analog-digital conversion result; the target resolution mode comprises a high-precision full-differential mode, a medium-precision full-differential mode, a low-precision full-differential mode or a single-ended mode;
under a high-precision full-differential mode, all capacitors of a DAC in the SAR ADC circuit participate in switching, and the Flash ADC circuit works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit;
in a medium-precision full-differential mode, one part of capacitors of a DAC in the SAR ADC circuit participate in switching and the other part of capacitors do not participate in switching, and the Flash ADC circuit works in a differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit;
Under a low-precision full-differential mode, selecting partial capacitors of a DAC in the SAR ADC circuit to participate in switching, wherein the Flash ADC circuit works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit; the capacitance of the DAC in the SAR ADC circuit which participates in switching is smaller than that of the DAC in the medium-precision full-differential mode;
In the single-ended mode, one part of capacitors of a DAC in the SAR ADC circuit participate in switching and the other part of capacitors do not participate in switching, the Flash ADC circuit works in the single-ended mode and transmits a high-bit digital code to a positive-end DAC or a negative-end DAC in the SAR ADC circuit, and unused sampling ends in the Flash ADC circuit and the SAR ADC circuit are kept grounded in the conversion process.
In one embodiment, the Flash ADC circuit is a Flash ADC circuit supporting single-ended mode and differential mode, and the SAR ADC circuit comprises a fixed bit number or a variable bit number SAR ADC circuit.
In one embodiment, the DAC capacitor array of the SAR ADC circuit comprises a capacitor array of a one-segment structure, a two-segment structure, a three-segment structure or a four-segment structure.
One of the above technical solutions has the following advantages and beneficial effects:
According to the analog-to-digital conversion method and the analog-to-digital conversion circuit with the multi-resolution modes, a novel multi-resolution mode switching technology is provided based on the FLASH SAR ADC circuit, so that one FLASH SAR ADC circuit is controlled to be compatible with different analog-to-digital conversion resolutions at the same time: according to the currently set resolution mode, the current operation mode of the FLASH SAR ADC circuit may be controlled by the SAR logic control module of the circuit to switch to the newly selected target resolution mode, for example, any one of a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode, and a single-ended mode, which are different in resolution from each other, so that the FLASH SAR ADC circuit performs signal conversion processing according to the newly set target resolution mode in the subsequent analog-to-digital conversion processing.
Therefore, compared with the prior art, the working mode switching with different resolutions and different conversion rates can be directly realized on the same FLASH SAR ADC circuit in a SAR logic control mode, the differential mode and single-ended mode switching is supported, and a special FLASH SAR ADC circuit is not required to be independently designed, so that the design cost and the production cost overhead can be greatly reduced, and the aims of greatly reducing the design and the production cost of FLASH SAR ADC are fulfilled.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a block diagram of the architecture of FLASH SAR ADC circuits for multi-resolution mode in one embodiment;
FIG. 2 is a schematic circuit diagram of a Flash ADC according to an embodiment, wherein (a) is a structure in a differential mode and (b) is a structure in a single-ended mode;
FIG. 3 is a schematic diagram of a comparison unit circuit of a single Flash ADC in one embodiment;
FIG. 4 is a schematic diagram of a capacitive array circuit in a high-precision fully differential mode in one embodiment;
FIG. 5 is a schematic diagram of a capacitive array circuit in a medium precision fully differential mode in one embodiment;
FIG. 6 is a schematic diagram of a single-ended mode capacitor array circuit in one embodiment;
fig. 7 is a flow chart of an analog-to-digital conversion method of a multi-resolution mode in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It is noted that reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Those skilled in the art will appreciate that the embodiments described herein may be combined with other embodiments. The term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to and integrated with the other element or intervening elements may also be present. The terms "one end," "the other end," and the like are used herein for illustrative purposes only.
Embodiments of the present invention will be described in detail below with reference to the attached drawings in the drawings of the embodiments of the present invention.
In one embodiment, as shown in FIG. 1, an embodiment of the present application provides a multi-resolution mode FLASH SAR ADC circuit, including a Flash ADC circuit 102 and a SAR ADC circuit 104. When the SAR logic of the SAR ADC circuit 104 obtains the currently set resolution mode conversion instruction, the control FLASH SAR ADC switches the current operation mode to the target resolution mode corresponding to the resolution mode conversion instruction, and then controls the FLASH SAR ADC circuit to perform the operations of the sampling stage and the quantization stage on the input signal in the target resolution mode, and outputs the final analog-digital conversion result.
The target resolution mode comprises a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode or a single-ended mode. In the high-precision fully-differential mode, all capacitors of the DACs in the SAR ADC circuit 104 are involved in the switching, and the Flash ADC circuit 102 operates in the differential mode and transfers high-order digital codes to the positive-side DAC and the negative-side DAC in the SAR ADC circuit 104, respectively. In the medium-precision fully-differential mode, a part of capacitors of the DAC in the SAR ADC circuit 104 participate in the switching use, and the other part of capacitors do not participate in the switching use, and the Flash ADC circuit 102 operates in the differential mode and transfers high-bit digital codes to the positive-side DAC and the negative-side DAC in the SAR ADC circuit 104, respectively.
In the low-precision fully-differential mode, partial capacitors of the DAC in the SAR ADC circuit 104 can be selected to participate in switching according to design requirements, and the Flash ADC circuit 102 works in the differential mode and transmits high-order digital codes to a positive-side DAC and a negative-side DAC in the SAR ADC circuit 104 respectively. The precision of the low-precision fully-differential mode and the precision of the medium-precision fully-differential mode may be not greatly different, except that the number of bits of the low-precision fully-differential mode is smaller, and the capacitance involved in switching in the SAR ADC circuit 104 is also smaller than that of the medium-precision fully-differential mode.
In the single-ended mode, a part of the capacitors of the DAC in the SAR ADC circuit 104 participate in the switching operation, and another part of the capacitors do not participate in the switching operation, the Flash ADC circuit 102 operates in the single-ended mode and transfers a high-order digital code to the positive-side DAC or the negative-side DAC in the SAR ADC circuit 104, and the unused sampling ends in the Flash ADC circuit 102 and the SAR ADC circuit 104 are kept at ground during the conversion process.
It will be appreciated that the main circuit components of the multi-resolution mode FLASH SAR ADC circuit shown in fig. 1 include the Flash ADC circuit 102, the SAR ADC circuit 104, etc., and may also include other existing necessary circuit components, such as a clock generator, a channel selector, a digital processing module, an encoder, etc., where DAC (P) is a positive side DAC circuit module of the SAR ADC circuit 104, DAC (N) is a negative side DAC circuit module of the SAR ADC circuit 104, COMP is a comparator thereof, and the signal A0 includes a clock and a mode selection signal (i.e., a resolution mode conversion instruction). The internal structure of each circuit structure component, its functional implementation, etc. can be understood by referring to the same circuit structure existing in the art, and will not be described in detail in this specification.
The FLASH SAR ADC circuit is a hybrid structure based on the SAR ADC circuit 104 as a core, and the combination of the Flash ADC circuit 102 and the SAR ADC circuit 104 mainly completes the cooperation with the Flash ADC circuit 102 by controlling the switching mode and the starting time of the SAR ADC circuit 104 through the SAR logic in the SAR ADC circuit 104. Different operation modes can be selected through the SAR logic, and more precisely, a mode selection signal is used for simultaneously controlling the SAR logic and the Flash ADC circuit 102 to mutually cooperate to realize multiple mode switching. Therefore, the switching of the operation mode of the FLASH SAR ADC circuit with multi-resolution mode and the control of the analog-to-digital conversion process can be realized through SAR logic control, such as mode switching, signal transmission channel selection, quantization function under each mode, digital code storage (used for encoding process for the later module) and the like.
In particular, in order to make FLASH SAR ADC circuits suitable for more applications and thereby reduce design and production costs, one of the above-mentioned block diagrams of the multi-resolution FLASH SAR ADC circuit is shown In fig. 1, where In0 to In15 are each input terminal,AndThe input signals of the two ends respectively can form differential input signals when in a differential mode, and correspondingly form differential input; in single ended mode, a single channel may be supported as an input (e.g., fromInput orInputs are all possible), the number of single-ended channels is twice that of differential channels. The selection of different resolution modes is achieved by controlling the difference of the mode selection signals (such as resolution mode switching instructions), and different signal transmission channels are selected and used through the channel selection signals. The specific modes can be as follows:
High precision fully differential mode: the high-precision mode set to be greater than or equal to 14-bit (such as 14-bit, 16-bit, 18-bit, etc.) precision can be used, and the DAC (capacitor array) in the SAR ADC circuit 104 needs to design redundant bit capacitors enough to ensure the precision requirement, and all capacitors in the DAC are used for switching (i.e. during analog-to-digital conversion processing). The Flash ADC circuit 102 is responsible for high M bit quantization, the SAR ADC circuit 104 is responsible for low L bit quantization, and finally, the digital codes output by the Flash ADC circuit and the SAR ADC circuit are combined and encoded to obtain the final output digital code of the whole FLASH SAR ADC circuit. Specifically, the Flash ADC circuit 102 operates in the differential mode, and may output two sets of digital codes P and N, which are respectively transferred to the positive-side DAC (P) in fig. 1) and the negative-side DAC (N) in fig. 1) in the SAR ADC circuit 104, and then the SAR ADC circuit 104 continues to quantize in the differential mode, so as to finally obtain digital codes of the Flash ADC circuit 102 and the SAR ADC circuit 104.
Medium precision fully differential mode: the medium precision fully differential mode set to greater than or equal to 10 bits and less than 14 bits precision may be, but is not limited to. This mode is based on a high-precision fully differential mode, which increases the slew rate of the ADC by reducing the precision. The redundancy requirement of the DAC capacitor array in the SAR ADC circuit 104 under the medium precision is not high under the high precision, so that redundancy bits can be reduced, at the moment, partial capacitors in the DAC are involved in switching, the potential of the capacitors which are not used in the mode is fixed and is not used for switching, the cycle number of SAR logic conversion is reduced, and meanwhile, the clock frequency is increased to further increase the conversion rate; the rest of the circuit operates in a consistent manner with the high-precision fully differential mode. The low-precision full-differential mode is similar to the medium-precision full-differential mode, and the conversion rate of the ADC is better improved by further reducing the precision.
Single-ended mode: the single ended structure, if using the same capacitor array as in the medium precision fully differential mode, will typically (but not necessarily) have one bit lower precision than in the medium precision fully differential mode, while the FLASH SAR ADC circuits will have a slew rate consistent with that of the medium precision fully differential mode. In this mode, the combined operation mode of Flash ADC circuit 102 and SAR ADC circuit 104 is modified to realize a single-ended mode, and in this mode, the capacitor that is not used in this mode is fixed in potential, and is not used for switching. The Flash ADC circuit 102 and the SAR ADC circuit 104 only need to sample single-ended (e.g., P-terminal or N-terminal) signals when sampling, wherein unused sampling terminals in the Flash ADC circuit 102 and the SAR ADC circuit 104 are grounded; the Flash ADC circuit 102 works in a single-ended mode and outputs a group of digital codes, and when the high-order bits of the SAR ADC circuit 104 are sampled by the positive-side DAC, the Flash ADC circuit 102 transmits the output digital codes to the positive-side DAC of the SAR ADC circuit 104; conversely, when the high order of SAR ADC circuit 104 uses negative side DAC sampling, flash ADC circuit 102 transfers the output digital code to the negative side DAC of SAR ADC circuit 104, and the other side DAC not used in SAR ADC circuit 104 remains grounded throughout the conversion process. The accuracy of the single ended mode may be selected according to specific design requirements, such as, but not limited to, 14 bits or 12 bits, and any combination of two or more accuracy may be suitable for this embodiment.
The FLASH SAR ADC circuit with the multi-resolution mode controls one FLASH SAR ADC circuit to be compatible with different analog-to-digital conversion resolutions by providing a brand new multi-resolution mode switching technology based on the FLASH SAR ADC circuit: according to the currently set resolution mode, the current operation mode of the FLASH SAR ADC circuit may be controlled by the SAR logic control module of the circuit to switch to the newly selected target resolution mode, for example, any one of a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode, and a single-ended mode, which are different in resolution from each other, so that the FLASH SAR ADC circuit performs signal conversion processing according to the newly set target resolution mode in the subsequent analog-to-digital conversion processing.
Therefore, compared with the prior art, the working mode switching with different resolutions and different conversion rates can be directly realized on the same FLASH SAR ADC circuit in a SAR logic control mode, the differential mode and single-ended mode switching is supported, and a special FLASH SAR ADC circuit is not required to be independently designed, so that the design cost and the production cost overhead can be greatly reduced, and the aims of greatly reducing the design and the production cost of FLASH SAR ADC are fulfilled. Furthermore, high precision ADCs often require calibration, which can integrate different resolutions; the low-precision ADC can realize high performance without repeated calibration, and the calibration cost can be reduced; the ADC processing with different sampling rates in different modes of multiple channels can be realized by using flexible resolution switching, so that the application scene is wider and diversified.
It should be noted that the four target resolution modes may be all used in the same FLASH SAR ADC circuits, or any one or two of them may be used, and specifically may be selected according to the needs of the practical application.
In one embodiment, further, flash ADC circuit 102 may be a Flash ADC circuit 102 that supports single-ended mode and differential mode. The SAR ADC circuit 104 may include a fixed number of bits or a variable number of bits SAR ADC circuit 104.
It will be appreciated that the number of bits of Flash ADC circuit 102 is typically greater than 2 bits and less than the number of bits of SAR ADC circuit 104, but that a too large number of bits of Flash ADC circuit 102 is typically not selected for design in view of the area power consumption requirements in practical applications. In this embodiment, in mode switching, for example, but not limited to, a combination of a 16-bit or 14-bit SAR ADC circuit 104 and a 5-bit Flash ADC circuit 102, a combination of a 16-bit SAR ADC circuit 104 and a 3-bit Flash ADC circuit 102, and a combination of a 14-bit SAR ADC circuit 104 and a 3-bit Flash ADC circuit 102 can form the above-mentioned FLASH SAR ADC circuit with multiple resolution modes, so as to implement switching supporting differential mode and single-ended mode, as long as it can be ensured that the capacitor array satisfies the designed weight relationship in the analog-to-digital conversion process, and in specific use, multiple resolution support can be implemented only by adjusting the number of capacitors used by the DAC. Therefore, the FLASH SAR ADC circuit supporting multiple resolutions is applicable to the multi-resolution mode switching function, and the application cost is further reduced.
In one embodiment, further, the DAC capacitive array of SAR ADC circuit 104 comprises a capacitive array of one-segment, two-segment, three-segment, or four-segment configuration.
It can be appreciated that in the present embodiment, the DAC capacitor array of the SAR ADC circuit 104 may also be a three-segment structure existing in the art, such as a high, medium, and low three-segment structure, respectively; the array can be a traditional DAC capacitor array with a one-segment structure, or can be a DAC capacitor array with a high-segment structure and a low-segment structure existing in the field, or can be a DAC capacitor array with a four-segment structure with finer segmentation in the field. The segmentation mode of selecting different DAC capacitor arrays is determined according to the area and power consumption required by ADC design, so that other DAC capacitor array structures capable of meeting the multi-resolution mode switching target are applicable besides the three-segment structure used in the embodiment, the circuit area can be flexibly designed and adjusted according to application requirements, the application of multiple SAR ADCs is compatible, and the circuit design and production cost are further reduced.
In one embodiment, some examples of alternative design applications are also provided to facilitate a better understanding of the above-described aspects. It should be noted that this example is only illustrative, and not the only limitation of the above solution in practical application, and those skilled in the art may implement different design applications according to the design concept of the above solution.
The design example provides a 16-bit and 13-bit fully differential 8-channel FLASH SAR ADC circuit and a 12-bit single-ended 16-channel FLASH SAR ADC to more intuitively demonstrate the technical scheme.
Firstly, a Flash ADC supporting a single-ended mode and a differential mode is designed, and in order to meet the above modes and consider the influence of speed and area, a 5-bit Flash ADC is designed, the whole structure block diagram of which can be shown in figure 2, wherein (a) is the structure in the differential mode, and (b) is the structure in the single-ended mode, and consists of 31 comparison unit circuits, and 31-bit temperature codes are output, and a single comparison unit circuit can be shown in figure 3, and when the Flash ADC works in the differential mode, the voltage is outputInput range isReference voltageThe reference sub-voltages V < x >, V < x > and V <32-x > are generated by dividing the resistor string consisting of 32 identical resistors to form a differential reference voltage (wherein x=1, 2, … …, 31), and the differential reference voltage is compared with an input signal to obtain an output result, and then the output result is fed into a coding module to obtain a 5-bit output code. Wherein V < P > and V < N > are the partial voltages of the resistor string pair V REF, PRE-COMP is the PRE-amplifying stage of the comparator, SW1 to SW8 are branch switches, C1 to C4 are capacitors, S1 to S3 are switches, LATCH is a LATCH, OUT and OUTN are the outputs of the RS LATCH respectively, and are the comparison result outputs of a single comparison unit circuit.
In fully differential mode, as shown in fig. 3, comparator positive input selection 401 is on, 402 should be off, while comparator negative input 403 is on, 404 transmission gate remains off,AndThe positive and negative input voltages of the comparator are respectively. Single-ended mode, supporting 16-channel input, signal can be arbitrarily selected from N-channel input or P-channel input, input signal rangeThe single resistor string voltage division signal range is alsoThe reference sub-voltage V < x > generated by dividing the resistor string is directly compared with an input signal to obtain a single-ended output digital code, and then the obtained output digital code is sent to a corresponding DAC, and is switched according to the result, and the method can be specifically divided into the following two cases:
First, flash ADC sampling should be used when selecting input from P-channel At this time, the positive input terminal 401 of the comparator in fig. 3 is turned on, the negative input terminal 403 is turned off, the negative input terminal 404 is turned on, the input N channel in fig. 1 is controlled to be grounded, the sampling is not affected, the Flash ADC obtains the output digital code to correspondingly control the DAC (P), the control channel of the DAC (N) is turned off, the DAC (N) is correspondingly grounded to the upper five-bit capacitor control, so that the sampling channel is grounded, the corresponding coding module (encoder (N)) in fig. 1 is turned off, the encoder (P) is started to encode, and the output digital code of the whole ADC is finally combined with the output digital code of the SAR ADC.
Secondly, flash ADC sampling should be used when selecting input from N channelAt this time, the positive input end 402 of the comparator in fig. 3 is turned on, 401 is turned off, the negative input end 404 is turned off, 403 is turned on, the input P-channel in fig. 1 is controlled to be grounded, the sampling is not affected, the Flash ADC obtains the output digital code to correspondingly control the DAC (N), the control channel of the DAC (P) is turned off, the DAC (N) is correspondingly grounded through five-bit capacitor control, so that the sampling channel is grounded, the corresponding coding module (encoder (P)) in fig. 1 is turned off, the encoder (N) is started to perform coding, and finally the output digital code of the whole ADC is combined with the output digital code of the SAR ADC.
The design can realize the single-ended mode 16-channel input. Secondly, SAR ADCs are designed based on different modes of operation.
High precision fully differential mode:
Firstly, a 16-bit SAR ADC is designed, the working mode of the SAR ADC is mainly determined by a DAC capacitor array of the SAR ADC, so that the DAC capacitor array is mainly designed, the influence of speed, precision and array area is considered, the whole DAC designed by the example is shown in a figure 4, the array adopts a three-section structure which is respectively in a high section, a middle section and a low section, particularly a 7+5+3 structure, the area can be reduced by adopting the three-section structure, the Vcm_based switching mode is adopted by adopting the switching mode, the highest capacitor can be saved, and the area can be reduced. Taking the influence of the gain error of the capacitor array and the influence of switching of different modes into consideration, high-order 6-bit capacitor sampling in a high stage is used, wherein 501 is a P-end sampling capacitor, and 502 is an N-end sampling capacitor.
The whole ADC works in the following way: (1) sampling phase: the Flash ADC and the SAR ADC sample input differential signals at the same time, wherein a group of channels corresponding to the input N and the input P are opened to form differential input, and the capacitors participating in sampling in the Flash ADC and the SAR ADC are used as load capacitors of a sampling switch.
(2) Quantization stage: after the sampling is completed, the Flash ADC will obtain a 5-bit digital code, which is sent to the upper five bits 503 of DAC (P) and the upper five bits 504 of DAC (N) as inputs to the DAC (i.eAnd) The DAC switches internal logic to update DAC output according to the input digital codes, then the comparator performs first comparison to obtain an output result, and then the comparator sequentially makes comparison of all subsequent bits according to a successive approximation algorithm until the quantization is completed; the specific implementation herein may be understood by reference to the FLASH SAR ADC conversion method as known in the art. After the conversion is completed, the output digital codes of the Flash ADC and the SAR ADC are encoded to obtain the final 16-bit digital code.
Medium precision fully differential mode:
In this example, a 7+5 two-stage structure is designed to be used in a 13-bit fully differential mode. The same Vcm_based switching mode is adopted, the redundant capacitor of the high bit C H3r is reserved, the high bit is not processed, the redundant bit can increase the redundancy of the output result of the Flash ADC, the high-stage middle-high 6 bit capacitor is used for sampling, as shown in figure 5, 601 is the P-end sampling capacitor, 602 is the N-end sampling capacitor, and thus, the circuit can be reused to the greatest extent, and the complexity of the circuit is reduced.
In the mode, the middle-stage capacitor array and the low-stage capacitor array are changed and combined to be used, non-binary redundancy is used in the 16-bit fully differential mode, and a large number of redundant capacitors are not needed in the 13-bit fully differential mode, so that a lower plate of a capacitor 10C at the highest position 605 in the middle stage is fixedly connected with a common mode voltage V CM and does not participate in quantification of an SAR ADC at 13 bits, meanwhile, in order to ensure binary relation of the capacitors, two 8C are combined to be 16C (606), two 4C are combined to be 8C (607), and two 2C are combined to be 4C (608), the combination mode can enable the capacitor array at 13 bits to meet the binary relation, coding difficulty is reduced, in addition, the residual capacitors 2C (609) and 1C (610) in the middle stage directly participate in conversion, and the low-stage capacitors 611 are all fixedly connected and do not participate in quantification of the SAR at 611, and C LEQ is equivalent capacitance from the low-stage capacitor and the bridge capacitor to the middle stage.
The working mode of the whole ADC is similar to that of a high-precision fully differential mode, the SAR ADC quantization period is reduced, and the method specifically comprises the following steps: (1) sampling phase: the Flash ADC and the SAR ADC sample input differential signals at the same time, wherein a group of input N and input P corresponding channels are opened to form differential input, and capacitors participating in sampling in the Flash ADC and the SAR ADC are used as load capacitors of a sampling switch, so that the sampling switch can use a grid voltage bootstrap sampling switch to ensure the precision requirement.
(2) Quantization stage: after the sampling is finished, the Flash ADC will obtain a 5-bit digital code, send the 5-bit digital code to the upper five bits 603 of the DAC (P) and the upper five bits 604 of the DAC (N) as inputs of the DAC, the DAC switches the internal logic to update the DAC output according to the input digital code, then the comparator performs the first comparison to obtain an output result, and then the comparator sequentially makes the comparator compare and determine all subsequent bits until the quantization is completed according to the successive approximation algorithm, where the specific implementation process can be understood by referring to the FLASH SAR ADC conversion method existing in the art. After the conversion is completed, the output digital codes of the Flash ADC and the SAR ADC are encoded to obtain the final 13-bit digital code.
Single-ended mode:
In this example, a two-stage structure 7+5 is designed in a 12-bit single-ended mode, and the capacitor array is the same as that in a medium-precision fully-differential mode. The high bit is in a single-ended structure, the low bit is in a differential structure, the same as the 16 bit and 13 bit full differential modes, a Vcm_based switching mode is adopted, the redundant capacitor of the high bit C H3r is reserved, the high bit is not processed, and the redundancy of the output result of the Flash ADC can be increased.
Because the sampling is a single-ended ADC, special processing is needed for sampling, only one end DAC is needed to participate in sampling, as shown in FIG. 6, sampling is needed for sampling an input signal by using a capacitance sample with a height of Duan Gao bits of DAC (P), 701 is a sampling capacitance, six bits of the upper six ends of corresponding DAC (N) 702 are fixedly Grounded (GND) during sampling, and because only the P end is used for sampling, the Flash ADC also needs to work in a single-ended mode, only the digital code output by the Flash ADC is needed to be sent to five bits of upper five bits 703 of the P end, and special processing is needed for the corresponding DAC of the N end, which is as follows: the high-order bits do not participate in sampling and do not need to participate in conversion, the lower plate of the capacitor with the high five-order bits 704 is completely and fixedly grounded, meanwhile, the Flash ADC digital code is sent to the access cut off 706 of the high five-order bits of the DAC (N), the corresponding switch is fixedly grounded by accessing a specific potential, and the redundant bit C H3r of the DAC at the N end participates in conversion, so that the lower plate is grounded during sampling, and the conversion is participated in according to SAR logic control during conversion.
The above-mentioned is a DAC switching structure corresponding to the selection of the input P channel by the channel selector in fig. 1, when the input N channel is used, the DAC (P) in fig. 6 is fixed in the upper five bits, and the DAC (N) is used for sampling, and meanwhile, the digital code input to the P end by the Flash ADC is cut off, and the structure is symmetrical and will not be described again here.
The DAC low-order structure is the same as the medium-precision fully differential mode, and the switching mode is the same.
The working mode of the whole ADC is consistent with a medium-precision full-differential mode, and the sampling phase is different from the middle-precision full-differential mode, specifically: (1) sampling phase: one end of a DAC in the single-ended Flash ADC and the SAR ADC samples an input single-ended signal at the same time, one of an input N channel and an input P channel is opened and is required to correspond to a sampling end of the DAC, and capacitors participating in sampling in the Flash ADC and the SAR ADC are used as load capacitors of sampling switches, so that the sampling switches can use grid voltage bootstrap sampling switches to ensure the precision requirement.
(2) Quantization stage: after sampling is finished, one end of the Flash ADC is used for obtaining a 5-bit digital code, then the 5-bit digital code is sent to the upper five bits 703 of the DAC (P) and the upper five bits 704 of the DAC (N) to be used as the input of the DAC, the DAC switches internal logic to update DAC output according to the input digital code, then a comparator performs first comparison to obtain an output result, and then the comparator sequentially enables the comparator to compare and determine all subsequent bits until the quantization is finished according to a successive approximation algorithm; the implementation of the process herein may be understood by reference to the FLASH SAR ADC conversion method known in the art. After the conversion is completed, the output digital codes of the Flash ADC and the SAR ADC are encoded to obtain the final 12-bit digital code.
Finally, after determining the ADC core structure, other peripheral circuits may be adaptively designed, for example, SAR logic may be designed to be suitable for executing all the switching sequences, and the working process is controlled by SAR logic, for example, mode switching is supported, channel selection is performed, quantization functions in the modes are implemented, digital codes can be stored, and encoding processing is performed on the subsequent modules, which may be understood by referring to similar implementation manners existing in the art, and no further description is given in this specification.
The above is a schematic test design performed according to the above technical solution for this example, and for the remaining non-core module circuits FLASH SAR ADC, the function of FLASH SAR ADC can be implemented by designing according to the corresponding conventional circuit in the field, which is not described in detail in this example.
In one embodiment, as shown in fig. 7, the embodiment of the present application further provides an analog-to-digital conversion method of a multi-resolution mode, which is applied to FLASH SAR ADC circuits of the multi-resolution mode, and the analog-to-digital conversion method includes steps S12 to S16:
S12, acquiring a currently set resolution mode conversion instruction;
S14, controlling FLASH SAR ADC a circuit to switch from a current working mode to a target resolution mode corresponding to the resolution mode conversion instruction according to the resolution mode conversion instruction;
s16, the control FLASH SAR ADC circuit performs conversion operation of a sampling stage and a quantization stage on the input signal in a target resolution mode, and outputs a final analog-digital conversion result.
The target resolution mode comprises a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode or a single-ended mode. In a high-precision fully-differential mode, all capacitors of a DAC in a SAR ADC of the FLASH SAR ADC circuit participate in switching, and a Flash ADC of the FLASH SAR ADC circuit works in a differential mode and transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC respectively. In the medium-precision full-differential mode, one part of capacitors of a DAC in the SAR ADC participate in switching and the other part of capacitors do not participate in switching, and the Flash ADC works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC. Under a low-precision full-differential mode, selecting partial capacitors of a DAC in the SAR ADC to participate in switching, wherein the Flash ADC works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC; the capacitance of the DAC in the SAR ADC which participates in switching is smaller than that of the DAC in the medium-precision full-differential mode. In the single-ended mode, one part of capacitors of a DAC in the SAR ADC participate in switching and the other part of capacitors do not participate in switching, the Flash ADC works in the single-ended mode and transmits a high-order digital code to a positive-end DAC or a negative-end DAC in the SAR ADC, and unused sampling ends in the Flash ADC and the SAR ADC are kept grounded in the conversion process.
It will be appreciated that for explanation of each step in this embodiment, reference may be made to the corresponding parts in the embodiment of FLASH SAR ADC circuit in the multi-resolution mode for understanding the same, and the detailed description is not repeated here.
According to the analog-to-digital conversion method of the multi-resolution mode, a novel multi-resolution mode switching technology is provided based on FLASH SAR ADC circuits, so that one FLASH SAR ADC circuit is controlled to be compatible with different analog-to-digital conversion resolutions at the same time: according to the currently set resolution mode, the current operation mode of the FLASH SAR ADC circuit may be controlled by the SAR logic control module of the circuit to switch to the newly selected target resolution mode, for example, any one of a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode, and a single-ended mode, which are different in resolution from each other, so that the FLASH SAR ADC circuit performs signal conversion processing according to the newly set target resolution mode in the subsequent analog-to-digital conversion processing.
Therefore, compared with the prior art, the working mode switching with different resolutions and different conversion rates can be directly realized on the same FLASH SAR ADC circuit in a SAR logic control mode, the differential mode and single-ended mode switching is supported, and a special FLASH SAR ADC circuit is not required to be independently designed, so that the design cost and the production cost overhead can be greatly reduced, and the aims of greatly reducing the design and the production cost of FLASH SAR ADC are fulfilled.
In one embodiment, the Flash ADC is a Flash ADC circuit supporting single-ended and differential modes, the SAR ADC comprising a fixed bit number or variable bit number SAR ADC circuit.
In one embodiment, the DAC capacitive array of the SAR ADC comprises a capacitive array of one-segment structure, two-segment structure, three-segment structure, or four-segment structure.
It will be appreciated that, for the explanation of the content of the embodiments of the analog-to-digital conversion method in the multi-resolution mode, the same explanation can be referred to in the embodiments of the FLASH SAR ADC circuit in the multi-resolution mode, and the description is omitted here.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description. The foregoing examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it is possible for those skilled in the art to make several variations and modifications without departing from the spirit of the present application, which fall within the protection scope of the present application. The scope of the application is therefore intended to be covered by the appended claims.

Claims (4)

1. A method for analog-to-digital conversion in a multi-resolution mode, applied to FLASH SAR ADC circuits in the multi-resolution mode, the method comprising:
acquiring a resolution mode conversion instruction which is currently set;
According to the resolution mode conversion instruction, the FLASH SAR ADC circuit is controlled to switch from a current working mode to a target resolution mode corresponding to the resolution mode conversion instruction;
Controlling the FLASH SAR ADC circuit to perform conversion operation of a sampling stage and a quantization stage on an input signal in the target resolution mode, and outputting a final analog-digital conversion result; the target resolution mode comprises a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode or a single-ended mode;
In the high-precision fully differential mode, all capacitors of a DAC in a SAR ADC of the FLASH SAR ADC circuit participate in switching, and a Flash ADC of the FLASH SAR ADC circuit works in a differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC; the input signal of the FLASH SAR ADC circuit is a differential input signal in the differential mode, and the Flash ADC works in the differential mode to output two groups of digital codes P and N, and the two groups of digital codes are respectively transmitted to a positive-end DAC and a negative-end DAC in the SAR ADC;
in the medium-precision fully-differential mode, one part of capacitors of a DAC in the SAR ADC participate in switching use, and the other part of capacitors do not participate in switching use, and the Flash ADC works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC;
Selecting partial capacitors of a DAC in the SAR ADC to participate in switching in the low-precision full-differential mode, wherein the Flash ADC works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC; the capacitance of the DAC in the SAR ADC which participates in switching is smaller than that of the DAC in the medium-precision full-differential mode;
In the single-ended mode, one part of capacitors of a DAC in the SAR ADC participate in switching and the other part of capacitors do not participate in switching, the Flash ADC works in the single-ended mode and transmits a high-order digital code to a positive-end DAC or a negative-end DAC in the SAR ADC, and unused sampling ends in the Flash ADC and the SAR ADC are kept grounded in the conversion process; the FLASH SAR ADC circuit supports a single channel as an input in a single-ended mode, the Flash ADC works in the single-ended mode to output a group of digital codes, and when the high-order of the SAR ADC uses a positive-side DAC for sampling, the Flash ADC transmits the output digital codes to the positive-side DAC of the SAR ADC; when the high order of the SAR ADC uses negative end DAC sampling, the Flash ADC transmits an output digital code to the negative end DAC of the SAR ADC.
2. The multi-resolution mode analog-to-digital conversion method of claim 1, wherein the Flash ADC is a Flash ADC circuit supporting single-ended mode and differential mode, the SAR ADC comprising a fixed bit number or a variable bit number SAR ADC circuit.
3. A F LASH SAR ADC circuit in a multi-resolution mode, which is characterized by comprising a Flash ADC circuit and a SAR ADC circuit;
When a currently set resolution mode conversion instruction is acquired by SAR logic of the SAR ADC circuit, controlling the FLASH SAR ADC circuit to switch from a current working mode to a target resolution mode corresponding to the resolution mode conversion instruction, controlling the FLASH SAR ADC circuit to perform conversion operation of a sampling stage and a quantization stage on an input signal in the target resolution mode, and outputting a final analog-digital conversion result; the target resolution mode comprises a high-precision fully-differential mode, a medium-precision fully-differential mode, a low-precision fully-differential mode or a single-ended mode;
In the high-precision full-differential mode, all capacitors of a DAC in the SAR ADC circuit participate in switching, and the Flash ADC circuit works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit; the input signal of the FLASH SAR ADC circuit is a differential input signal in a differential mode, and the Flash ADC circuit works in the differential mode to output two groups of digital codes P and N and respectively transmits the two groups of digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit;
in the medium-precision fully-differential mode, one part of capacitors of a DAC in the SAR ADC circuit participate in switching use, and the other part of capacitors do not participate in switching use, and the Flash ADC circuit works in the differential mode and respectively transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit;
Selecting partial capacitors of a DAC in the SAR ADC circuit to participate in switching in the low-precision full-differential mode, wherein the Flash ADC circuit works in the differential mode and transmits high-order digital codes to a positive-end DAC and a negative-end DAC in the SAR ADC circuit respectively; the capacitance of the DAC in the SAR ADC circuit which participates in switching is smaller than that of the DAC in the medium-precision full-differential mode;
In the single-ended mode, one part of capacitors of a DAC in the SAR ADC circuit participate in switching use, and the other part of capacitors do not participate in switching use, the Flash ADC circuit works in the single-ended mode and transmits a high-bit digital code to a positive-end DAC or a negative-end DAC in the SAR ADC circuit, and unused sampling ends in the Flash ADC circuit and the SAR ADC circuit are kept grounded in the conversion process; the FLASH SAR ADC circuit supports a single channel as an input in a single-ended mode, the Flash ADC circuit works in the single-ended mode to output a group of digital codes, and when the high-order of the SAR ADC circuit uses a positive-side DAC for sampling, the Flash ADC circuit transmits the output digital codes to the positive-side DAC of the SAR ADC circuit; when the high order of the SAR ADC circuit uses negative end DAC sampling, the Flash ADC circuit transmits an output digital code to the negative end DAC of the SAR ADC circuit.
4. The multi-resolution mode FLASH SAR ADC circuit according to claim 3, wherein the Flash ADC circuit is a Flash ADC circuit supporting single-ended mode and differential mode, the SAR ADC circuit comprising a fixed bit number or a variable bit number SAR ADC circuit.
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