CN118316438A - Differential clock signal driving circuit - Google Patents
Differential clock signal driving circuit Download PDFInfo
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- CN118316438A CN118316438A CN202410741217.1A CN202410741217A CN118316438A CN 118316438 A CN118316438 A CN 118316438A CN 202410741217 A CN202410741217 A CN 202410741217A CN 118316438 A CN118316438 A CN 118316438A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application provides a differential clock signal driving circuit, and relates to the field of circuits. The differential clock signal driving circuit comprises a driving circuit and a low-power-consumption high-speed current control logic circuit, wherein the driving circuit is connected with the low-power-consumption high-speed current control logic circuit; the driving circuit comprises a plurality of enabling ends and a plurality of pairs of differential signal transmission paths, the enabling ends correspond to the pairs of differential signal transmission paths one by one, and at least one pair of differential signal transmission paths in the pairs of differential signal transmission paths outputs differential driving signals to the low-power-consumption high-speed current control logic circuit based on control of the corresponding enabling ends; the low-power-consumption high-speed current control logic circuit comprises a plurality of groups of transistors which are arranged in parallel, and at least one group of transistors in the plurality of groups of transistors is conducted based on the control of the differential driving signal so as to generate a differential clock signal. By implementing the technical scheme provided by the application, the scene that the same LP-HCSL is matched with various output impedances can be realized, and the flexibility of LP-HCSL is improved.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a differential clock signal driving circuit.
Background
High-speed current control logic (HCSL, high-speed Current Steering Logic) for defining a reference clock level standard in the PCIe electrical specification; thus, the level compatibility among different manufacturers can be kept.
Compared with the traditional HCSL, the Low Power consumption HCSL (LP-HCSL, low Power-HCSL) has the same swing (for example 750 mV) of clock signal output, can consume less current, greatly reduces the Power consumption of the system and becomes the main stream direction. However, the existing LP-HCSL typically has a fixed magnitude (e.g., 50 ohms) output impedance, i.e., the LP-HCSL output impedance is single, and the same LP-HCSL cannot meet different output impedance scenarios, which requires designing different LP-HCSL for different output impedance scenarios, increasing the design and production cost of LP-HCSL, and reducing the flexibility of LP-HCSL.
Disclosure of Invention
The differential clock signal driving circuit provided by the embodiment of the application can realize the scene that the same LP-HCSL can be matched with various output impedances, reduces the design and production cost of LP-HCSL and improves the flexibility of LP-HCSL.
In a first aspect, an embodiment of the present application provides a differential clock signal driving circuit, including: the driving circuit is connected with the low-power-consumption high-speed current control logic circuit; the driving circuit comprises a plurality of enabling ends and a plurality of pairs of differential signal transmission paths, the enabling ends correspond to the pairs of differential signal transmission paths one by one, and at least one pair of differential signal transmission paths in the pairs of differential signal transmission paths outputs differential driving signals to the low-power-consumption high-speed current control logic circuit based on control of the corresponding enabling ends; the low-power-consumption high-speed current control logic circuit comprises a plurality of groups of transistors which are arranged in parallel, and at least one group of transistors in the plurality of groups of transistors is conducted based on the control of the differential driving signal so as to generate a differential clock signal.
According to the embodiment of the application, the plurality of pairs of differential signal transmission paths are arranged in the driving circuit, and the plurality of groups of transistors are arranged in the low-power-consumption high-speed current control logic circuit, so that the on or off of the plurality of groups of transistors is controlled by changing the on or off of the differential signal transmission paths, and because the plurality of groups of transistors are arranged in parallel, the magnitude of the output impedance of the differential clock signal can be changed by changing the number of the transistors which are arranged in parallel, namely, the size of the transistors is equivalent to the change, therefore, compared with the fixed impedance of the LP-HCSL output in the prior art, the embodiment of the application can provide the output impedance with different magnitudes, so that more scenes can be matched, namely, compared with the prior art, the flexibility of the LP-HCSL can be improved.
In one possible implementation, the driving circuit further includes a forward signal input terminal and a reverse signal input terminal, and any one of the plurality of pairs of differential signal transmission paths includes a forward signal transmission path and a reverse signal transmission path; the forward signal transmission path comprises a plurality of cascaded first inverters, wherein the plurality of cascaded first inverters are arranged between the same-direction signal input end and the output end of the forward signal transmission path, and the control end of one first inverter is connected with a first enabling end in a plurality of enabling ends.
In one possible implementation, the reverse signal transmission path includes a plurality of cascaded second inverters, and the plurality of cascaded second inverters are disposed between the reverse signal input terminal and the output terminal of the reverse signal transmission path, wherein the control terminal of one of the second inverters is connected to the first enable terminal.
In one possible implementation, a plurality of cascaded third inverters are further provided between the forward signal transmission path and the reverse signal transmission path.
In one possible implementation, the plurality of sets of transistors includes a first set of transistors and a second set of transistors; the first group of transistors includes a first transistor, a second transistor, a third transistor, and a fourth transistor; the second group of transistors includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first transistor and the fifth transistor are arranged in parallel between a power supply end of the low-power-consumption high-speed current control logic circuit and a first differential signal output end of the differential clock signal driving circuit, the second transistor and the sixth transistor are arranged in parallel between the power supply end and a second differential signal output end of the differential clock signal driving circuit, the third transistor and the seventh transistor are arranged in parallel between the first differential signal output end and the common ground, and the fourth transistor and the eighth transistor are arranged in parallel between the second differential signal output end and the common ground.
In one possible implementation, the differential clock signal driving circuit further includes a decoder; the input end of the decoder is connected with the external controller, and a plurality of output ends of the decoder are correspondingly connected with a plurality of enabling ends; the decoder is used for receiving a control word from an external controller, converting the control word into a control signal and respectively providing the control signal to a plurality of enabling terminals.
In one possible implementation, the driving circuit includes a plurality of; the driving circuits are arranged in parallel between the enabling end of the decoder and the low-power consumption high-speed current control logic circuit.
In one possible implementation, the low-power-consumption high-speed current control logic circuit includes a plurality of low-power-consumption high-speed current control logic circuits respectively and correspondingly connected with the plurality of driving circuits.
According to the embodiment of the application, more output impedance can be further provided by arranging the plurality of driving circuits and the plurality of low-power-consumption high-speed current control logic circuits, so that LP-HCSL can be matched with more scenes, and the flexibility of LP-HCSL is further improved.
In one possible implementation manner, the differential clock signal driving circuit further includes a linear voltage regulator, the linear voltage regulator includes an operational amplifier and a ninth transistor, a gate of the ninth transistor is connected with an output end of the operational amplifier, and an inverting input end of the operational amplifier and a source of the ninth transistor are both connected with a power supply end of the low-power consumption high-speed current control logic circuit; the operational amplifier is powered by a first power supply, the ninth transistor is powered by a second power supply, and the first power supply and the second power supply are different power supplies.
Usually, the operational amplifier needs a higher voltage value, for example, 3.3V, and when the operational amplifier and the transistor in the linear voltage stabilizer are powered by the same power supply in a traditional manner, the low voltage scenario cannot be satisfied; according to the embodiment of the application, the power supply of the operational amplifier and the power supply of the transistor in the linear voltage stabilizer are set to be different power supplies, so that the voltage value of the second power supply (for example, the voltage value of the second power supply is 1V) can be reduced under the condition that the single-side swing (for example, at least 750 mV) of the differential clock signal output is ensured, the power consumption of the differential clock signal driving circuit can be reduced, and the low-voltage scene of the differential clock signal driving circuit is facilitated.
In one possible implementation, the linear voltage regulator further includes a first capacitor and a second capacitor; the first capacitor is arranged between the drain electrode and the gate electrode of the ninth transistor, and the second capacitor is arranged between the source electrode of the ninth transistor and the common ground.
Drawings
FIG. 1 is a schematic diagram of a differential clock signal driving circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a driving circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a low power consumption high speed current control logic circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a differential clock signal driving circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a linear voltage regulator according to an embodiment of the present application;
fig. 6 is a schematic diagram of another structure of a differential clock signal driving circuit according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the technical solutions in the present specification, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.
In describing embodiments of the present application, words such as "for example" or "for example" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "such as" or "for example" in embodiments of the application should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "or" for example "is intended to present related concepts in a concrete fashion.
In the description of embodiments of the application, the term "plurality" means two or more. For example, a plurality of transducers refers to two or more transducers. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Referring to fig. 1, fig. 1 is a schematic diagram of a differential clock signal driving circuit 100 according to an embodiment of the application. As shown in fig. 1, the differential clock signal driving circuit 100 includes a driving circuit 10 and a low power consumption high speed current control logic (LP-HCSL) circuit 20. The driving circuit 10 is connected to the LP-HCSL circuit 20 via a plurality of outputs.
The driving circuit 10 includes a plurality of enable terminals, a plurality of pairs of differential signal transmission paths, and a plurality of output terminals, the number of the enable terminals may be the same as the number of pairs of the differential signal transmission paths, and the number of the output terminals may be twice the number of the enable terminals. For example, the driving circuit 10 includes two enable terminals, two pairs of differential signal transmission paths, and four output terminals; for example, the three enable terminals, three pairs of differential signal transmission paths and six output terminals are included, and the embodiment of the present application is not limited in particular. The driving circuit 10 is schematically shown in fig. 1 to include two enable terminals en1 and en2, two pairs of differential signal transmission paths 11 and 12, and four output terminals outp1, outp2, and the embodiment of the present application will be described in detail with reference to the structure of the driving circuit 10 by way of example, but is not particularly limited thereto. As shown in fig. 1, the differential signal transmission path 11 includes two signal transmission paths including a forward signal transmission path and a reverse signal transmission path, both of which are connected to the enable terminal en1, the forward signal transmission path in the differential signal transmission path 11 is connected to the output terminal outp1, and the reverse signal transmission path in the differential signal transmission path 11 is connected to the output terminal outn 1; also, the differential signal transmission path 12 includes two signal transmission paths, a forward signal transmission path and a reverse signal transmission path, both of which are connected to the enable terminal en2, the forward signal transmission path in the differential signal transmission path 12 is connected to the output terminal outp2, and the reverse signal transmission path in the differential signal transmission path 11 is connected to the output terminal out2. The driving circuit 10 further includes a forward signal input terminal clip and a reverse signal input terminal clin, and a forward signal transmission path in the differential signal transmission path 11 and a forward signal transmission path in the differential signal transmission path 12 are connected to the forward signal input terminal clip, and a reverse signal transmission path in the differential signal transmission path 11 and a reverse signal transmission path in the differential signal transmission path 12 are connected to the reverse signal input terminal clin.
The LP-HCSL circuit 20 includes a plurality of signal inputs, a voltage signal input Vreg, and differential signal outputs clop and clon. The signal inputs of the LP-HCSL circuit 20 are connected to the outputs of the driving circuit 10 in a one-to-one correspondence. The LP-HCSL circuit 20 includes multiple sets of transistors arranged in parallel, including two sets of transistors and three sets of transistors, and embodiments of the present application are not limited in detail. In addition, each of the plurality of sets of transistors may include two transistors or four transistors. It should be noted that, while the conventional HCSL circuit is generally powered by a current source, the LP-HCSL circuit 20 provided in the embodiment of the present application is powered by a voltage source.
In the embodiment of the present application, assuming that the output impedance of the differential clock signal is 100 ohms, the enable terminal en1 and the enable terminal en2 enable the differential signal transmission path 11 to be turned on and the differential signal transmission path 12 to be turned off based on the control of the enable signal, and the driving circuit 10 transmits the driving signal to the LP-HCSL circuit 20 through the output terminal outp1 and the output terminal outn 1; transistor n1 and transistor n2 in LP-HCSL circuit 20 (see fig. 3 for specific structure) are on, transistor n5 and transistor n6 are off, and transistors n1 and n2 provide differential clock signals with output impedance of 100 ohms to differential signal outputs clop and clon based on the voltage signal input at voltage signal input terminal Vreg. Assuming that the output impedance of the differential clock signal is 85 ohms, the enable terminal en1 and the enable terminal en2 are controlled based on the enable signal, so that the differential signal transmission path 11 and the differential signal transmission path 12 are both conductive, and the driving circuit 10 transmits a driving signal to the LP-HCSL circuit 20 through the output terminals outp1, outn1, outp2 and outn 2; transistors n1, n2, n5, and n6 in LP-HCSL circuit 20 are all on, and transistors n1, n2, n5, and n6 provide differential clock signals with an output impedance of 85 ohms to differential signal outputs clop and clon based on the voltage signal input at voltage signal input Vreg.
As can be seen from fig. 1, the differential clock signal driving circuit 100 provided in the embodiment of the present application is configured to provide a plurality of pairs of differential signal transmission paths, and a plurality of groups of transistors in the LP-HCSL circuit 20, so that the plurality of groups of transistors are controlled to be turned on or off by changing the on or off state of the differential signal transmission paths, and since the plurality of groups of transistors are arranged in parallel, the magnitude of the output impedance of the differential clock signal can be changed by changing the number of the transistors arranged in parallel, that is, by changing the size of the transistors, compared with the fixed impedance of the LP-HCSL output in the prior art, the embodiment of the present application can provide different magnitudes of output impedance, so that more scenes can be matched, that is, compared with the prior art, the flexibility of the LP-HCSL can be improved.
Based on the differential clock signal driving circuit 100 shown in fig. 1, in one possible implementation, the pairs of differential signal transmission paths included in the driving circuit 10 may have the same circuit structure. In each of the plurality of pairs of differential signal transmission paths, the forward signal transmission path comprises a plurality of cascaded first inverters, the plurality of cascaded first inverters are arranged between the same-direction signal input end and the output end of the forward signal transmission path, and the control end of one first inverter is connected with a first enabling end of the plurality of enabling ends; the reverse signal transmission path comprises a plurality of cascaded second inverters, the plurality of cascaded second inverters are arranged between the reverse signal input end and the output end of the reverse signal transmission path, and the control end of one second inverter is connected with the first enabling end; a plurality of cascaded third inverters are also arranged between the forward signal transmission path and the reverse signal transmission path. The structure of the driving circuit 10 is shown in fig. 2, and fig. 2 is a schematic diagram showing a specific structure of the driving circuit 10 shown in fig. 1. As shown in fig. 2, the differential signal transmission path 11 and the differential signal transmission path 12 have the same structure, and the differential signal transmission path 11 will be described as an example. The forward signal transmission path in the differential signal transmission path 11 includes two cascaded first inverters F1, the two first inverters F1 are connected in series between the differential signal input terminal clip and the output terminal outp1, the first inverter F1 connected with the differential signal input terminal clip is further provided with an enable signal input terminal, and the enable signal input terminal is connected with the enable terminal en 1; the reverse signal transmission path in the differential signal transmission path 11 includes two cascaded second inverters F2, the two second inverters F2 are connected in series between the differential signal input end clin and the output end outn1, the second inverter F2 connected to the differential signal input end clin is further provided with an enable signal input end, and the enable signal input end is connected to the enable end en 1; in addition, a third inverter F3 is connected in series between the output terminal of the first inverter F1 of the preceding stage and the output terminal of the second inverter F2 of the preceding stage; in addition, a third inverter F4 is connected in series between the output terminal of the first inverter F1 of the subsequent stage and the output terminal of the second inverter F2 of the subsequent stage. The on or off of the differential signal transmission path 11 is controlled by controlling the on or off of the inverter connected to the enable terminal en 1.
In one possible implementation of the embodiment of the present application, each set of transistors in the LP-HCSL circuit 20 may include four transistors, as shown in fig. 3, and fig. 3 is a schematic diagram of a configuration of the LP-HCSL circuit 20. As shown in fig. 3, the LP-HCSL circuit 20 includes a transistor n1, a transistor n2, a transistor n3, a transistor n4, a transistor n5, a transistor n6, a transistor n7, and a transistor n8, where the transistor n1, the transistor n2, the transistor n3, and the transistor n4 are a set of transistors to form a set of differential push-pull circuits, and the transistor n5, the transistor n6, the transistor n7, and the transistor n8 are a set of transistors to form a set of differential push-pull circuits. The drains of the transistors n1, n2, n5 and n6 are all connected with the voltage signal input terminal Vreg; the sources of the transistor n1 and the transistor n5 are connected with the differential signal output end clop; the sources of the transistor n2 and the transistor n6 are connected with the differential signal output end clon; the gate of the transistor n1 is connected with the output end outp1 of the driving circuit 10, and the gate of the transistor n5 is connected with the output end outp2 of the driving circuit 10; the gate of the transistor n2 is connected to the output terminal outn1 of the driving circuit 10; the gate of the transistor n6 is connected to the output terminal outn2 of the driving circuit 10; the drains of the transistor n3 and the transistor n7 are connected with the differential signal output end clop; the drains of the transistor n4 and the transistor n8 are connected with the differential signal output end clon; the gate of the transistor n4 is connected with the output end outp1 of the driving circuit 10, and the gate of the transistor n8 is connected with the output end outp2 of the driving circuit 10; the gate of the transistor n3 is connected to the output terminal outn1 of the driving circuit 10; the gate of the transistor n7 is connected to the output terminal outn2 of the driving circuit 10; the sources of transistors n3, n4, n7 and n8 are all connected to a common ground Gnd.
Referring to fig. 4, fig. 4 is a schematic diagram of a differential clock signal driving circuit 200 according to an embodiment of the application. The differential clock signal driving circuit 200 includes a driving circuit 10 and an LP-HCSL circuit 20, wherein the structures and connection relationships of the driving circuit 10 and the LP-HCSL circuit 20 are the same as those of the differential clock signal driving circuit 100 shown in fig. 1, and detailed descriptions thereof are omitted. As with the differential clock signal driving circuit 100 shown in fig. 1, the differential clock signal driving circuit 100 includes a decoder 30 and a linear regulator 40. The decoder 30 is connected to the enable terminal en1 and the enable terminal en2 of the driving circuit 10, and the linear regulator 40 is connected to the voltage signal input terminal Vreg of the LP-HCSL circuit 20. Wherein the decoder 30 generates the enable signals based on the control of the received control signals, which are provided to the enable terminal en1 and the enable terminal en2, respectively. For example, signal "01" is used to indicate that a differential clock signal with an output impedance of 100 ohms is generated; signal "10" is used to indicate that a differential clock signal with an output impedance of 85 ohms is generated; when the decoder 30 receives the signal "01", the generated signal "10" is supplied to the enable terminals en1 and en2, respectively, so that the differential signal transmission path 11 is turned on and the differential signal transmission path 12 is turned off; when the decoder 30 receives the signal "10", the generated signal "11" is supplied to the enable terminals en1 and en2, respectively, so that the differential signal transmission path 11 and the differential signal transmission path 12 are both turned on.
The linear regulator 40 is used to provide a regulated voltage to the transistors in the LP-HCSL circuit 20. The structure of the linear regulator 40 is shown in fig. 5. The linear regulator 40 includes an operational amplifier op1, a transistor N1, a capacitor C0, and a capacitor C1. The non-inverting input end of the operational amplifier op1 is used for inputting a reference signal Vref, the inverting input end of the operational amplifier op1 is connected with the source electrode of the transistor N1, and the output end of the operational amplifier op1 is connected with the gate electrode of the transistor N1; the power supply terminal of the operational amplifier op1 is connected to the first power supply VDD1, the drain of the transistor N1 is connected to the second power supply VDD2, and the first power supply VDD1 and the second power supply VDD2 are different power supplies. In addition, a capacitor C0 is disposed between the gate and the source of the transistor N1, and the capacitor C1 is disposed between the source of the transistor N1 and the common ground Gnd.
In the conventional technology, the linear voltage regulator 40 is powered by the same power supply, that is, the operational amplifier and the transistor N1 are both connected to the same power supply, and generally, the power supply of the operational amplifier needs a higher voltage value, for example, 3.3V, when the operational amplifier and the transistor in the linear voltage regulator are powered by the same power supply in the conventional manner, this results in that the differential clock signal driving circuit 100 has higher power consumption, and cannot meet the low voltage scenario; according to the embodiment of the application, the operational amplifier op1 and the transistor N1 in the linear voltage stabilizer 40 are powered by different power supplies, so that the voltage value of the second power supply VDD2 (for example, the voltage value of the second power supply VDD2 is 1V) can be reduced under the condition of ensuring the single-side swing (for example, at least 750 mV) of the differential clock signal output, the power consumption of the differential clock signal driving circuit 100 can be reduced, and the low-voltage scene of the differential clock signal driving circuit 100 is facilitated.
In the above embodiments, the differential clock signal driving circuits each include one driving circuit 10 and one LP-HCSL circuit 20, and in one possible implementation, the differential clock signal driving circuits may include a plurality of driving circuits 10 and a plurality of LP-HCSL circuits 20, the number of the plurality of driving circuits 10 and the plurality of LP-HCSL circuits 20 may be the same, and the plurality of driving circuits 10 and the plurality of LP-HCSL circuits 20 may be connected in a one-to-one correspondence. The differential clock signal driving circuit is described below with reference to fig. 6, taking three driving circuits 10 and three LP-HCSL circuits 20 as examples. Referring to fig. 6, fig. 6 is a schematic diagram of a differential clock signal driving circuit 300 according to an embodiment of the application. As shown in fig. 6, the enable terminals en1 and en2 of the three driving circuits 10 are connected to the decoder 30; each of the three driver circuits 10 is connected to the LP-HCSL circuit 20 via an output, outp1, outp2 and outp 2. When it is required to generate a differential clock signal with an output impedance of 100 ohms or 85 ohms, the decoder 30 may gate any one of the driving circuits 30; when it is desired to generate a differential clock signal having an output impedance of 33 ohms, the decoder 30 may gate all three driving circuits 10, and turn on a set of transistors in the corresponding LP-HCSL circuits 20 through the three driving circuits 10, respectively, to generate a differential clock signal having an output impedance of 33 ohms.
According to the embodiment of the application, more output impedance can be further provided by arranging the plurality of driving circuits and the plurality of low-power-consumption high-speed current control logic circuits, so that LP-HCSL can be matched with more scenes, and the flexibility of LP-HCSL is further improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The differential clock signal driving circuit is characterized by comprising a driving circuit and a low-power-consumption high-speed current control logic circuit, wherein the driving circuit is connected with the low-power-consumption high-speed current control logic circuit;
the driving circuit comprises a plurality of enabling ends and a plurality of pairs of differential signal transmission paths, the enabling ends are in one-to-one correspondence with the pairs of differential signal transmission paths, and at least one pair of differential signal transmission paths in the pairs of differential signal transmission paths outputs differential driving signals to the low-power-consumption high-speed current control logic circuit based on control of the corresponding enabling ends;
The low-power-consumption high-speed current control logic circuit comprises a plurality of groups of transistors which are arranged in parallel, and at least one group of transistors in the plurality of groups of transistors is conducted based on the control of the differential driving signal so as to generate a differential clock signal.
2. The differential clock signal driving circuit according to claim 1, wherein the driving circuit further comprises a forward signal input terminal and a reverse signal input terminal, any one of the pairs of differential signal transmission paths comprising a forward signal transmission path and a reverse signal transmission path;
The forward signal transmission path comprises a plurality of cascaded first inverters, wherein the plurality of cascaded first inverters are arranged between the forward signal input end and the output end of the forward signal transmission path, and the control end of one first inverter is connected with a first enabling end of the plurality of enabling ends.
3. The differential clock signal driving circuit according to claim 2, wherein the inverted signal transmission path includes a plurality of cascaded second inverters disposed between the inverted signal input terminal and an output terminal of the inverted signal transmission path, wherein a control terminal of one of the second inverters is connected to the first enable terminal.
4. A differential clock signal driving circuit as defined in claim 3, wherein a plurality of cascaded third inverters are further provided between said forward signal transmission path and said reverse signal transmission path.
5. The differential clock signal drive circuit of claim 1, wherein the plurality of sets of transistors comprises a first set of transistors and a second set of transistors;
The first set of transistors includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
the second set of transistors includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
The first transistor and the fifth transistor are arranged in parallel between a power end of the low-power-consumption high-speed current control logic circuit and a first differential signal output end of the differential clock signal driving circuit, the second transistor and the sixth transistor are arranged in parallel between the power end and a second differential signal output end of the differential clock signal driving circuit, the third transistor and the seventh transistor are arranged in parallel between the first differential signal output end and the common ground, and the fourth transistor and the eighth transistor are arranged in parallel between the second differential signal output end and the common ground.
6. The differential clock signal drive circuit according to any one of claims 1 to 5, wherein the differential clock signal drive circuit further comprises a decoder;
The input end of the decoder is connected with an external controller, and a plurality of output ends of the decoder are correspondingly connected with the plurality of enabling ends;
The decoder is used for receiving a control word from the external controller, converting the control word into a control signal and respectively providing the control signal to the plurality of enabling terminals.
7. The differential clock signal driving circuit according to claim 6, wherein the driving circuit includes a plurality of;
the driving circuits are arranged in parallel between the enabling end of the decoder and the low-power-consumption high-speed current control logic circuit.
8. The differential clock signal driving circuit according to claim 7, wherein the low power consumption high speed current control logic circuit includes a plurality of the low power consumption high speed current control logic circuits and a plurality of the driving circuits are respectively connected correspondingly.
9. The differential clock signal driving circuit according to any one of claims 1 to 5, further comprising a linear voltage regulator including an operational amplifier and a ninth transistor, a gate of the ninth transistor being connected to an output terminal of the operational amplifier, an inverting input terminal of the operational amplifier and a source of the ninth transistor being connected to a power supply terminal of the low power consumption high speed current control logic circuit; wherein,
The operational amplifier is powered by a first power supply, the ninth transistor is powered by a second power supply, and the first power supply and the second power supply are different power supplies.
10. The differential clock signal driving circuit according to claim 9, wherein the linear voltage regulator further comprises a first capacitor and a second capacitor;
The first capacitor is arranged between the drain electrode and the gate electrode of the ninth transistor, and the second capacitor is arranged between the source electrode of the ninth transistor and the common ground.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140061185A (en) * | 2012-11-13 | 2014-05-21 | 에스케이하이닉스 주식회사 | Differential delay circuit and oscillating circuit for the same |
CN204065892U (en) * | 2014-07-08 | 2014-12-31 | 新乡市新日电控设备有限公司 | A kind of modified low-pressure linear voltage stabilizer |
US9692394B1 (en) * | 2016-03-25 | 2017-06-27 | Integrated Device Technology, Inc. | Programmable low power high-speed current steering logic (LPHCSL) driver and method of use |
CN115333556A (en) * | 2022-08-10 | 2022-11-11 | 慷智集成电路(上海)有限公司 | High-speed receiving module based on MIPI protocol and vehicle-mounted video transmission chip |
CN118041308A (en) * | 2024-01-26 | 2024-05-14 | 珠海市杰理科技股份有限公司 | Crystal oscillator circuit and clock signal generation method |
-
2024
- 2024-06-11 CN CN202410741217.1A patent/CN118316438B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140061185A (en) * | 2012-11-13 | 2014-05-21 | 에스케이하이닉스 주식회사 | Differential delay circuit and oscillating circuit for the same |
CN204065892U (en) * | 2014-07-08 | 2014-12-31 | 新乡市新日电控设备有限公司 | A kind of modified low-pressure linear voltage stabilizer |
US9692394B1 (en) * | 2016-03-25 | 2017-06-27 | Integrated Device Technology, Inc. | Programmable low power high-speed current steering logic (LPHCSL) driver and method of use |
CN115333556A (en) * | 2022-08-10 | 2022-11-11 | 慷智集成电路(上海)有限公司 | High-speed receiving module based on MIPI protocol and vehicle-mounted video transmission chip |
CN118041308A (en) * | 2024-01-26 | 2024-05-14 | 珠海市杰理科技股份有限公司 | Crystal oscillator circuit and clock signal generation method |
Non-Patent Citations (1)
Title |
---|
佚名: "(干货分享)差分电路原理解析", Retrieved from the Internet <URL:https://zhuanlan.zhihu.com/p/420971335> * |
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