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CN118301055A - Message forwarding method and device, electronic equipment and storage medium - Google Patents

Message forwarding method and device, electronic equipment and storage medium Download PDF

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Publication number
CN118301055A
CN118301055A CN202410384478.2A CN202410384478A CN118301055A CN 118301055 A CN118301055 A CN 118301055A CN 202410384478 A CN202410384478 A CN 202410384478A CN 118301055 A CN118301055 A CN 118301055A
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CN
China
Prior art keywords
message
forwarding table
cpu
fpga
fast forwarding
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Application number
CN202410384478.2A
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Chinese (zh)
Inventor
李婷
沈佳诚
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Hangzhou DPTech Technologies Co Ltd
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Hangzhou DPTech Technologies Co Ltd
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Priority to CN202410384478.2A priority Critical patent/CN118301055A/en
Publication of CN118301055A publication Critical patent/CN118301055A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/54—Organization of routing tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/74—Address processing for routing
    • H04L45/745—Address table lookup; Address filtering
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/06—Protocols specially adapted for file transfer, e.g. file transfer protocol [FTP]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The application provides a message forwarding method, a device, an electronic device and a storage medium, which are applied to an FPGA in network equipment, wherein the network equipment further comprises a CPU, and the CPU is used for determining whether a first quick forwarding table item matched with a first message exists in an FPGA quick forwarding table in response to a received first message, and forwarding the first message according to the first quick forwarding table item if the first quick forwarding table item exists and the FPGA supports a service corresponding to a service mark in the first quick forwarding table item; otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message and forward according to the second fast forwarding table item under the condition that the second fast forwarding table item matched with the first message exists in the CPU fast forwarding table. By utilizing the fast forwarding function of the FPGA, the message forwarding speed of the network equipment is improved, and the service processing performance and economic benefit of the whole machine are improved.

Description

Message forwarding method and device, electronic equipment and storage medium
Technical Field
The present application relates to the field of network communications technologies, and in particular, to a method and apparatus for forwarding a message, an electronic device, and a storage medium.
Background
The traffic received by the network device is almost processed and forwarded by the CPU in the network device, when the network traffic is larger, and the network device processes some services, such as DPI (DEEP PACKET insertion) service, three-layer forwarding service and two-layer forwarding service, the network congestion, the slow data transmission rate or the increased response time of the network may be caused due to the insufficient processing capability of the CPU, so that the use experience of the user is greatly reduced.
At present, high-end network equipment or high-performance CPU is often used for replacing low-end network equipment or low-performance CPU to improve the processing capacity of the network equipment, but the cost of the whole machine is increased, and the economic benefit is low.
Disclosure of Invention
The application provides a message forwarding method, a message forwarding device, electronic equipment and a storage medium, which utilize the fast forwarding function of an FPGA to realize the improvement of the message forwarding rate of network equipment and the improvement of the service processing performance and economic benefit of the whole machine.
In a first aspect of the present application, a method for forwarding a message is provided, which is applied to an FPGA in a network device, where the network device further includes a CPU, and includes:
Responding to a received first message, and determining whether a first quick forwarding table item matched with the first message exists in an FPGA quick forwarding table;
If the first fast forwarding table entry exists and the FPGA supports the service corresponding to the service mark in the first fast forwarding table entry, forwarding the first message according to the first fast forwarding table entry;
Otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message under the condition that a second fast forwarding table item matched with the first message exists in a CPU fast forwarding table, and the processed first message is forwarded according to the second fast forwarding table item.
In a second aspect of the present application, a message forwarding apparatus is provided, which is applied to an FPGA in a network device, where the network device further includes a CPU, and includes:
the determining unit is used for responding to the received first message and determining whether a first fast forwarding table item matched with the first message exists in the FPGA fast forwarding table;
A forwarding unit, configured to forward, if the first fast forwarding table entry exists and the FPGA supports a service corresponding to a service flag in the first fast forwarding table entry, the first packet according to the first fast forwarding table entry;
Otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message under the condition that a second fast forwarding table item matched with the first message exists in a CPU fast forwarding table, and the processed first message is forwarded according to the second fast forwarding table item.
In a third aspect of the application, there is provided an electronic device comprising a processor and a memory storing machine executable instructions executable by the processor for executing the machine executable instructions to implement any of the methods provided in the first aspect.
In a fourth aspect of the application, there is provided a machine-readable storage medium having stored thereon machine-executable instructions which when executed by a processor implement any of the methods provided in the first aspect.
In a fifth aspect of the application, there is provided a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of any of the methods provided in the first aspect.
As can be seen from the above technical solution, the present application is applied to an FPGA in a network device, where the network device further includes a CPU, and by responding to a received first packet, determines whether a first fast forwarding table entry matching the first packet exists in an FPGA fast forwarding table, and if the first fast forwarding table entry exists, and the FPGA supports a service corresponding to a service flag in the first fast forwarding table entry, forwards the first packet according to the first fast forwarding table entry; otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message under the condition that a second fast forwarding table item matched with the first message exists in the CPU fast forwarding table, and the processed first message is forwarded according to the second fast forwarding table item. By utilizing the fast forwarding function of the FPGA, the message forwarding speed of the network equipment is improved, and the service processing performance and economic benefit of the whole machine are improved.
Drawings
Fig. 1 is a flow chart of a message forwarding method according to an embodiment of the present application;
fig. 2 is a flow chart of a packet forwarding method based on DPI service according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a message forwarding device according to an embodiment of the present application;
fig. 4 is a schematic hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments and that the modules or flows in the drawings are not necessarily required to practice the application and therefore should not be taken to limit the scope of the application.
First, some technical abbreviations related to the present application will be explained:
CPU: the central processing unit (Central Processing Unit) is used as an operation and control core of the computer system and is a final execution unit for information processing and program running.
In a network device, a CPU is the processor of the network device that is responsible for performing various computing and control tasks, including managing network connections, processing data packets, performing routing and forwarding algorithms, and the like. The CPU plays a vital role in the network device, which determines the processing power and performance of the network device.
DPI: deep packet Inspection (DEEP PACKET Inspection) is an application-layer-based traffic detection and control technique for deep parsing and Inspection of network packets. DPI technology can analyze the content, protocol, source and destination address information of the packet and identify, filter, classify and process according to predefined rules and policies. DPI technology is commonly used in the fields of network security, traffic management, network optimization, etc., and is an important component of network equipment.
And (3) FPGA: a Field-Programmable gate array (Field-Programmable GATE ARRAY) is a product developed further on the basis of Programmable devices such as PAL (Programmable array Logic ), GAL (general array Logic, GENERIC ARRAY Logic) and the like. The FPGA is used as a semi-custom circuit in the field of application-specific integrated circuits, not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device, has the advantages of flexibility, programmability and reconfigurability, and can dynamically adjust and reconfigure functions according to requirements.
Referring to fig. 1, a flow chart of a message forwarding method according to an embodiment of the present application is shown, where the method is applied to an FPGA in a network device, and the network device further includes a CPU.
The network device may be a router, a switch, a gateway, or any processing device that is additionally provided with a network function for constructing, managing, and maintaining on the basis of the original device function service, and the specific device type and the deployment form of the network device may be flexible in actual operation, and may be configured according to actual needs, which is not particularly limited by the embodiment of the present application.
The FPGA may be a component included in the network device itself, or may be a component in which the network device is additionally configured.
As shown in fig. 1, the message forwarding method may include the following steps:
Step 101: and responding to the received first message, and determining whether a first quick forwarding table item matched with the first message exists in the FPGA quick forwarding table.
The network device further includes a network card, where the network card receives a packet in the target network and transmits the packet to the FPGA.
Illustratively, the FPGA fast forwarding table may be stored in an internal memory of the FPGA, where the internal memory may be a distributed RAM, a block on chip RAM, or the like, which depends on the actual requirements and hardware resources of the FPGA, and the embodiment of the present application is not limited in particular.
In some embodiments, each fast forwarding table entry in the FPGA fast forwarding table stores at least a session Base address (Base), an Offset (Offset) of a session relative to the session Base address, and a service flag, and may further store information such as a control parameter, a number of messages, and a number of bytes of a message.
The address of the target session can be obtained by Base address addressing, that is, by adding the Offset to the session Base stored in the fast forwarding table entry, and in the subsequent step of forwarding the first packet, the address can be performed according to forwarding information included in the target session.
In some embodiments, each fast forwarding table entry in the FPGA fast forwarding table stores at least the outbound/inbound interface information and the service flag of the message, and may also store information such as control parameters, the number of messages, the number of bytes of the message, and so on.
In some embodiments, the network card of the network device receives the first message in the target network and transmits the first message to the FPGA, where the FPGA may extract key information in the first message, such as a source/destination IP address, a source/destination MAC address, a port number, and the like, of the first message, and determine the outbound/inbound interface information of the first message according to the key information.
The FPGA traverses the table items in the FPGA quick forwarding table according to the output/input interface information of the first message, and if the output/input interface information stored in a certain table item is found to be the same as the output/input interface information of the first message, the table item is the first quick forwarding table item matched with the first message in the FPGA quick forwarding table, that is, the first quick forwarding table item matched with the first message in the FPGA quick forwarding table can be determined. Otherwise, determining that a first fast forwarding table item matched with the first message does not exist in the FPGA fast forwarding table.
Step 102: if the first fast forwarding table entry exists and the FPGA supports the service corresponding to the service mark in the first fast forwarding table entry, forwarding the first message according to the first fast forwarding table entry;
Otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message under the condition that a second fast forwarding table item matched with the first message exists in a CPU fast forwarding table, and the processed first message is forwarded according to the second fast forwarding table item.
In some embodiments, if it is determined that a first fast forwarding table entry matching the first packet exists in the FPGA fast forwarding table, it is determined whether the FPGA supports a service corresponding to the service flag in the first fast forwarding table entry.
Specifically, an FPGA service list supported by the FPGA may be preconfigured in an internal memory, a configuration bitstream, or other specific storage area of the FPGA, where the FPGA service list includes various services supported by the FPGA and corresponding service flags.
The FPGA can analyze the first quick forwarding table entry to obtain the service mark in the first quick forwarding table entry, and match the service mark in the first quick forwarding table entry with the service mark in the FPGA service list.
If the service marks which are completely the same as the service marks in the first quick forwarding table item exist in the FPGA service list, determining that the FPGA supports the service corresponding to the service marks in the first quick forwarding table item, otherwise, determining that the FPGA does not support the service corresponding to the service marks in the first quick forwarding table item.
In some embodiments, if it is determined that a first fast forwarding table item matched with the first message exists in the FPGA fast forwarding table, and the FPGA supports a service corresponding to a service flag in the first fast forwarding table item, such as a three-layer forwarding service, a two-layer forwarding service, and the like, the FPGA may fast forward the first message according to the outbound interface information in the first fast forwarding table item.
In the embodiment of the application, the service marks stored in the FPGA quick forwarding table entry are utilized fully, so that the message forwarding rate is improved, the CPU processing pressure is reduced, and the service processing performance and stability of the network equipment are improved.
In some embodiments, if it is determined that the first fast forwarding table entry matching the first packet exists in the FPGA fast forwarding table, but the FPGA does not support a service corresponding to a service flag in the first fast forwarding table entry, such as a DPI service, an encryption/decryption service, an image processing service, an audio/video codec service, and the like, the FPGA may transmit the first packet to the CPU.
Specifically, the first fast forwarding table entry further includes a control parameter. The FPGA may transmit the first message to the CPU by:
The FPGA can analyze the first quick forwarding table item to obtain the control parameters, and the first message is transmitted to the CPU under the condition that the CPU meets the conditions defined by the control parameters.
Specifically, the control parameters include a quantity parameter. For example, the number parameter may be a maximum number of messages, where the maximum number of messages may be "80", and the FPGA determines whether the number of messages currently processed by the CPU is less than the maximum number of messages 80, and if so, transmits the first message to the CPU. Otherwise, the FPGA may buffer the first message in a storage unit or a queuing queue in the FPGA, and then transmit the first message to the CPU after waiting for the number of messages currently processed by the CPU to be less than the maximum number of messages 80.
The control parameters may further include a utilization parameter, a data processing amount parameter, and the like, which is not particularly limited in the embodiment of the present application, for example, the FPGA may determine whether the current utilization of the CPU is smaller than the utilization parameter, and if so, transmit the first packet to the CPU.
As to how the FPGA determines the number of messages currently processed by the CPU, embodiments of the present application are not particularly limited thereto. The FPGA monitors the read-write operation of the CPU on the memory, and determines the number of messages currently processed by the CPU by analyzing the memory access mode and the frequency. The CPU can also send a specific mark or indication signal to the FPGA when processing each message, so that the FPGA can determine the number of the messages currently processed by the CPU according to the mark or indication signal. The FPGA may send a request to the CPU, so that the CPU may send the number of messages currently processed to the FPGA in response to the request.
In the embodiment of the application, the first message can be transmitted to the CPU under the condition that the CPU meets the condition defined by the control parameters, so that the condition that the CPU bears too much pressure and packet loss, network instability and the like due to too many messages transmitted to the CPU by the FPGA is avoided, and the service processing stability of the network equipment is improved.
In some embodiments, after the FPGA transmits the first message to the CPU, the CPU is caused to determine whether a second fast forwarding table entry exists in the CPU fast forwarding table that matches the first message.
If it is determined that the second fast forwarding table item matched with the first message does not exist in the fast forwarding table of the CPU, the CPU processes the first message through a protocol stack, performs normal forwarding, creates the second fast forwarding table item matched with the first message in the fast forwarding table of the CPU, and brushes (or refers to as synchronizing) the second fast forwarding table item into the fast forwarding table of the FPGA.
If the second fast forwarding table item matched with the first message exists in the CPU fast forwarding table, the CPU is enabled to process the first message, and fast forwarding is conducted on the first message according to the second fast forwarding table item.
Specifically, the CPU may process the first packet by:
the CPU service list supported by the CPU itself can be preconfigured for the CPU, and the CPU service list comprises various services which can be directly processed by the CPU itself and corresponding service marks.
The CPU can analyze the second quick forwarding table entry to obtain the service mark in the second quick forwarding table entry, and match the service mark in the second quick forwarding table entry with the service mark in the CPU service list.
If the service mark which is completely the same as the service mark in the second quick forwarding table item exists in the CPU service list, determining that the CPU supports the service corresponding to the service mark in the second quick forwarding table item, in this case, the CPU directly processes the first message and carries out quick forwarding on the first message through the CPU according to the second quick forwarding table item.
Otherwise, determining that the CPU does not support the service corresponding to the service mark in the second fast forwarding table item, in this case, the CPU processes the first message through the protocol stack, and fast forwards the first message through the protocol stack according to the second fast forwarding table item.
In the embodiment of the application, the CPU can directly process and forward the supported service through the service mark stored in the fast forwarding table entry of the CPU, thereby reducing the resource consumption and improving the message forwarding rate and the service processing performance of the network equipment.
In some embodiments, the CPU may pre-configure the plurality of virtual central processing units VCPU (Virtual Central Processing Unit). Any VCPU is pre-allocated with a corresponding target storage space, where the corresponding target storage space may be a queue or buffer dedicated to any VCPU, and embodiments of the present application are not limited in this regard. The target storage space is used for storing the first message, that is, the target storage space is used for storing the message which is required to be processed by the corresponding VCPU.
The FPGA sends the first message to the CPU, and after determining that a second fast forwarding table item matched with the first message exists in the CPU fast forwarding table, the CPU sequentially stores the first message sent by the FPGA into a target storage space corresponding to each VCPU in a polling mode, so that each VCPU processes the first message in the corresponding target storage space and forwards the processed first message according to the second fast forwarding table item.
In one example, assume that the CPU is preconfigured with two VCPUs. The first message is sent to the CPU by the FPGA, and after the CPU determines that the fast forwarding table item matched with the first message exists in the fast forwarding table of the CPU, the first message is transmitted to the first queue initially pointed by the pointer of the scheduler, so that the VCPU corresponding to the first queue processes the first message, and fast forwards the first message according to the fast forwarding table item matched with the first message. At the same time, the pointer of the scheduler will point to the second queue.
After the FPGA sends the second message to the CPU, the CPU transmits the second message to the second queue pointed by the pointer of the scheduler after determining that the fast forwarding table entry matching the second message exists in the CPU fast forwarding table, so that the VCPU corresponding to the second queue processes the second message, and fast forwards the second message according to the fast forwarding table entry matching the second message. At the same time, the pointer of the scheduler will point to the first queue.
After the FPGA sends the third message to the CPU, the CPU transmits the third message to the first queue pointed by the pointer of the scheduler after determining that the fast forwarding table item matched with the third message exists in the CPU fast forwarding table, so that the VCPU corresponding to the first queue processes the third message, and fast forwards the third message according to the fast forwarding table item matched with the third message. At the same time, the pointer of the scheduler will point to the second queue. The above cycle is repeated, i.e. by means of polling.
In the embodiment of the application, the message sent by the FPGA is sequentially stored in the corresponding target storage space of each VCPU in a polling mode, so that each VCPU processes the message in the corresponding target storage space and forwards the processed message according to the second quick forwarding table entry, the purpose of uniformly distributing the message processing task among a plurality of VCPUs is realized, the aim of balancing loads is achieved, and the overall performance and the response capability of the system are improved.
In some embodiments, in the case that a second fast forwarding table item matched with the first packet exists in the CPU fast forwarding table, after the CPU processes the first packet, if the processed first packet meets a preset policy, the service flag in the second fast forwarding table item is set to be invalid, and the second fast forwarding table item with the service flag set to be invalid is brushed down into the FPGA fast forwarding table.
Specifically, the preset policy may be a security policy, a flow control policy, a load balancing policy, an optimization policy, a QoS (Quality of Service ) policy, or other custom policies, which depend on actual services and requirements, and the embodiment of the present application is not limited in particular.
Taking the DPI service as an example, after the CPU processes the first packet, the DPI depth of the processed first packet may be evaluated, and whether the DPI depth obtained by the evaluation is smaller than or equal to the preset DPI depth may be determined, if yes, the DPI service flag in the second fast forwarding table entry is set to be invalid, and the second fast forwarding table entry in which the DPI service flag is set to be invalid is brushed down to the FPGA fast forwarding table.
In the embodiment of the application, if the processed first message meets the preset strategy, the service mark in the second quick forwarding table item is set to be invalid, and the second quick forwarding table item with the service mark set to be invalid is downwards brushed into the FPGA quick forwarding table, so that the subsequent message can be directly and quickly forwarded by the FPGA without uploading a CPU, thereby realizing the improvement of the message forwarding rate, the reduction of the processing pressure of the CPU and the improvement of the service processing performance of network equipment.
Further, by fully utilizing the FPGA rapid forwarding function, the CPU cost is reduced, and the economic benefit of the whole machine is improved.
In some embodiments, if it is determined that the first fast forwarding table entry matching the first packet does not exist in the FPGA fast forwarding table, the FPGA may transmit the first packet to the CPU.
If the CPU determines that the second quick forwarding table item matched with the first message does not exist in the CPU quick forwarding table, the CPU processes the first message through a protocol stack, then performs ordinary forwarding, creates the second quick forwarding table item matched with the first message in the CPU quick forwarding table, and brushes the second quick forwarding table item down to the FPGA quick forwarding table.
If the CPU determines that the second quick forwarding table item matched with the first message exists in the CPU quick forwarding table, the CPU processes the first message and carries out quick forwarding on the first message according to the second quick forwarding table item. For specific implementation details, reference may be made to the foregoing embodiments, which are not described herein.
Referring to fig. 2, a flow chart of a packet forwarding method based on DPI service according to an embodiment of the present application is shown.
As shown in fig. 2, the following steps may be included:
Step 201: the network card receives the first message.
The network card of the network device receives the message in the target network and transmits the message to the FPGA.
Step 202: and determining whether a first fast forwarding table item matched with the first message exists in the FPGA fast forwarding table.
If the FPGA fast forwarding table does not have the first fast forwarding table entry matching the first message, then step 206 is executed: and transmitting the first message to the CPU.
If there is a first fast forwarding table entry matching the first message in the FPGA fast forwarding table, step 203 is executed: and judging whether the first message contains a load or not.
In some embodiments, the FPGA may determine whether the first packet includes a load by parsing a total_len field in a four-layer header of the first packet, and determine that the first packet includes a load if total_len is greater than 0, or determine that the first packet includes no load if not.
If it is determined that the first packet is a packet without load, step 205 is executed: and the FPGA carries out quick forwarding on the first message according to the first quick forwarding table item.
If it is determined that the first message is a message containing a load, step 204 is executed: judging whether the FPGA supports the service corresponding to the service mark in the first quick forwarding table item.
If the FPGA supports the service corresponding to the service flag in the first fast forwarding table, step 205 is executed: and the FPGA carries out quick forwarding on the first message according to the first quick forwarding table item.
If the FPGA does not support the service corresponding to the service flag in the first fast forwarding table, step 206 is executed: and transmitting the first message to the CPU.
In some embodiments, if the FPGA does not support the service corresponding to the service flag in the first fast forwarding table entry, the FPGA may parse the first fast forwarding table entry to obtain the control parameter in the first fast forwarding table entry, and transmit the first packet to the CPU if it is determined that the CPU meets the condition defined by the control parameter.
Specifically, the control parameter may be a DPI depth, for example, the value of the DPI depth is N, the FPGA determines whether the number of the messages currently processed by the CPU is smaller than the value N of the DPI depth, and if so, the first message is transmitted to the CPU. Otherwise, the FPGA may buffer the first packet in a storage unit or a queuing queue in the FPGA, wait for the number of packets currently processed by the CPU to be less than the value N of the DPI depth, and then transmit the first packet to the CPU.
At step 206: after transmitting the first message to the CPU, step 207 is executed: and determining whether a second quick forwarding table item matched with the first message exists in the CPU quick forwarding table.
If the second fast forwarding table entry matching the first message does not exist in the CPU fast forwarding table, step 208 is executed: and processing and forwarding the first message through a protocol stack, creating the second fast forwarding table item in a CPU fast forwarding table, and downflushing the second fast forwarding table item into an FPGA fast forwarding table.
The second fast forwarding table entry stores information such as the ingress/egress interface information, the DPI depth, the service flag, etc. of the first packet, and may also store information such as the number of packets, the number of bytes of the packet, etc.
If there is a second fast forwarding table entry matching the first packet in the CPU fast forwarding table, step 209 is executed: judging whether the CPU supports the service corresponding to the service mark in the first quick forwarding table item.
If the CPU does not support the service corresponding to the service flag in the first fast forwarding table, step 210 is executed: processing is performed through the protocol stack.
After processing the first message by the protocol stack, step 211 is executed: and according to the second fast forwarding table item, fast forwarding the processed first message through the protocol stack.
If the CPU supports the service corresponding to the service flag in the first fast forwarding table, step 212 is executed: the CPU directly processes DPI service.
In some embodiments, after the CPU directly performs DPI service processing on the first packet, the DPI depth of the first packet after performing DPI service processing may be estimated, and the DPI depth obtained by the estimation may be brushed down to the FPGA fast forwarding table.
After the CPU directly performs DPI service processing on the first packet, step 213 is executed: judging whether the first message processed by the DPI service meets a preset strategy or not.
In some embodiments, after the CPU performs the DPI service processing on the first packet, the DPI depth of the processed first packet may be estimated, and it may be determined whether the DPI depth obtained by the estimation is less than or equal to a preset DPI depth.
If the first packet after DPI service processing does not meet the preset policy, step 214 is executed: and according to the second fast forwarding table item, the first processed message is directly forwarded fast by the CPU.
If the first packet after DPI service processing meets the preset policy, step 215 is executed: and setting the DPI service mark in the second quick forwarding table item to be invalid, and brushing the DPI service mark to the FPGA quick forwarding table. After performing the completion step 215, step 214 is performed: and according to the second fast forwarding table item, the first message is directly forwarded fast through the CPU.
In the embodiment of the application, the service marks stored in the FPGA quick forwarding table entry are utilized fully, so that the message forwarding rate is improved, the CPU processing pressure is reduced, and the service processing performance and stability of the network equipment are improved.
Further, under the condition that the CPU meets the conditions defined by the control parameters, the first message is transmitted to the CPU, so that the situation that the CPU bears too much pressure and packet loss, network instability and the like due to too many messages transmitted to the CPU by the FPGA is avoided, and the service processing stability of the network equipment is improved.
Further, if the processed first message meets a preset strategy, the service mark in the second quick forwarding table item is set to be invalid, and the second quick forwarding table item with the service mark set to be invalid is downwards brushed into the FPGA quick forwarding table, so that the subsequent message can be directly and quickly forwarded by the FPGA without uploading a CPU, the message forwarding rate is improved, the processing pressure of the CPU is reduced, and the service processing performance of the network equipment is improved.
The foregoing describes the method provided by the present application. The device provided by the application is described below:
fig. 3 is a schematic structural diagram of a message forwarding device according to an embodiment of the present application.
As shown in fig. 3, the apparatus may include:
The determining unit 301 is configured to determine, in response to a received first packet, whether a first fast forwarding table entry matching the first packet exists in the FPGA fast forwarding table.
A forwarding unit 302, configured to forward, if the first fast forwarding table entry exists and the FPGA supports a service corresponding to a service flag in the first fast forwarding table entry, the first packet according to the first fast forwarding table entry;
Otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message and forward the first message according to a second fast forwarding table item matched with the first message when the second fast forwarding table item exists in the CPU fast forwarding table.
The implementation process of the functions and roles of each unit in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
The embodiment of the application also provides a hardware structure. Referring to fig. 4, fig. 4 is a block diagram of an electronic device according to an embodiment of the present application. As shown in fig. 4, the hardware structure may include: a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor; the processor is configured to execute machine-executable instructions to implement the methods disclosed in the above examples of the present application.
Based on the same application concept as the above method, the embodiment of the present application further provides a machine-readable storage medium, where a number of computer instructions are stored, where the computer instructions can implement the method disclosed in the above example of the present application when the computer instructions are executed by a processor.
By way of example, the machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device that can contain or store information, such as executable instructions, data, and the like. For example, a machine-readable storage medium may be: RAM (Radom Access Memory, random access memory), volatile memory, non-volatile memory, flash memory, a storage drive (e.g., hard drive), a solid state disk, any type of storage disk (e.g., optical disk, dvd, etc.), or a similar storage medium, or a combination thereof.
It is noted that relational terms such as target and object, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.

Claims (11)

1. The message forwarding method is characterized by being applied to an FPGA in network equipment, wherein the network equipment also comprises a CPU, and the method comprises the following steps:
Responding to a received first message, and determining whether a first quick forwarding table item matched with the first message exists in an FPGA quick forwarding table;
If the first fast forwarding table entry exists and the FPGA supports the service corresponding to the service mark in the first fast forwarding table entry, forwarding the first message according to the first fast forwarding table entry;
Otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message under the condition that a second fast forwarding table item matched with the first message exists in a CPU fast forwarding table, and the processed first message is forwarded according to the second fast forwarding table item.
2. The method of claim 1, wherein if the first fast forwarding table entry exists and the FPGA does not support the service corresponding to the service tag in the first fast forwarding table entry, the transmitting the first packet to the CPU includes:
And acquiring the control parameters in the first quick forwarding table entry, and transmitting the first message to the CPU under the condition that the CPU is determined to meet the conditions defined by the control parameters.
3. The method according to claim 2, wherein the control parameter includes a quantity parameter, and wherein the transmitting the first message to the CPU in a case where it is determined that the CPU satisfies a condition defined by the control parameter includes:
determining whether the number of messages currently processed by the CPU is smaller than the number parameter;
if yes, the first message is transmitted to the CPU.
4. The method according to claim 1, characterized in that the method further comprises:
And under the condition that the second quick forwarding table item does not exist in the CPU quick forwarding table, the CPU processes the first message and forwards the first message, the second quick forwarding table item is created in the CPU quick forwarding table, and the second quick forwarding table item is stored in the FPGA quick forwarding table.
5. The method according to claim 1, characterized in that the method further comprises:
determining whether the CPU supports the service corresponding to the service mark in the second quick forwarding table item;
if yes, the CPU processes the first message and forwards the processed first message according to the second fast forwarding table item;
If not, the CPU processes the first message through a protocol stack, and forwards the processed first message through the protocol stack according to the second fast forwarding table item.
6. The method of claim 1, wherein after the CPU processes the first message, the method further comprises:
and if the processed first message meets a preset strategy, setting the service mark in the second quick forwarding table item to be invalid, and storing the second quick forwarding table item with the service mark set to be invalid into the FPGA quick forwarding table.
7. The method of claim 1, wherein the CPU pre-configures a plurality of VCPUs, any VCPU is pre-allocated with a corresponding target storage space, the target storage space is used for storing the first message, the causing the CPU to process the first message, and forwarding the processed first message according to the second fast forwarding table entry includes:
And the CPU sequentially stores the first messages sent by the FPGA into the corresponding target storage spaces of the VCPUs in a polling mode, so that the VCPUs process the first messages in the corresponding target storage spaces and forward the processed first messages according to the second quick forwarding table items.
8. The message forwarding device is characterized by being applied to an FPGA in network equipment, wherein the network equipment also comprises a CPU, and the device comprises:
the determining unit is used for responding to the received first message and determining whether a first fast forwarding table item matched with the first message exists in the FPGA fast forwarding table;
A forwarding unit, configured to forward, if the first fast forwarding table entry exists and the FPGA supports a service corresponding to a service flag in the first fast forwarding table entry, the first packet according to the first fast forwarding table entry;
Otherwise, the first message is transmitted to the CPU, and the CPU is enabled to process the first message under the condition that a second fast forwarding table item matched with the first message exists in a CPU fast forwarding table, and the processed first message is forwarded according to the second fast forwarding table item.
9. An electronic device comprising a processor and a memory, the memory storing machine executable instructions executable by the processor for executing the machine executable instructions to implement the method of any of claims 1-7.
10. A machine-readable storage medium having stored thereon machine-executable instructions which, when executed by a processor, implement the method of any of claims 1-7.
11. A computer program product comprising computer programs/instructions which, when executed by a processor, implement the steps of the method of any of claims 1-7.
CN202410384478.2A 2024-03-29 2024-03-29 Message forwarding method and device, electronic equipment and storage medium Pending CN118301055A (en)

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