CN118300578B - Control system and method for accurate delay and pulse width adjustment of phased array ultrasonic emission - Google Patents
Control system and method for accurate delay and pulse width adjustment of phased array ultrasonic emission Download PDFInfo
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Abstract
The invention relates to the field of circuit design, in particular to a control system and a control method for accurate delay and pulse width adjustment of phased array ultrasonic emission. The phase-locked loop circuit comprises: for dividing the input clock signal CLK into multiple clock signals of the same frequency and different phases. The control circuit: for receiving the input clock signal CLK and the output clock Lock signal Lock, and then outputting pulse width, delay and enable signals through the register set. A coarse adjustment circuit: the device is used for receiving the clock signal, combining the pulse width, the time delay and the enabling signals output by the register group to output an independent rough adjustment output signal after processing. Fine tuning circuitry: the circuit is used for receiving the rough adjustment output signal, combining the pulse width, the time delay and the enabling signals output by the register group, performing channel selection and logic operation processing on the rough adjustment output signal, and generating a fine adjustment output signal. The invention realizes accurate subdivision delay and pulse width control, and the precision can reach the precision of phase interval.
Description
Technical Field
The invention relates to the field of circuit design, in particular to a control system and a control method for accurate delay and pulse width adjustment of phased array ultrasonic emission.
Background
In the field of phased array ultrasonic instruments, transducer excitation forms an intra-aperture acoustic beam deflection or focusing by means of different transmit delays for each ultrasonic transducer wafer, the accuracy of the delays directly reflecting the characteristics of the beam. In the ultrasonic nondestructive testing MHz frequency band, the delay precision of a phased array ultrasonic testing instrument is in ns level, which is typically a fraction to a tenth of the wavelength period time. In current digital circuit dominated beamforming circuits, a dedicated chip is typically employed, such as the LM96570 chip from TI. The other is to use CPLD or FPGA chip, the internal program sets frequency dividing circuit to count and output frequency dividing delay, but because the main frequency of FPGA or CPLD is limited, it is generally hundreds of MHz main frequency, such as 400MHz, the delay precision is 2.5ns, and it can not meet the accurate delay requirement of phased array transmitting circuit, especially the delay requirement of high frequency phased array. Meanwhile, in ultrasonic nondestructive detection or medical ultrasound, high-voltage pulse excitation is generally adopted for ultrasonic transduction wafer excitation, the single pulse width is set to be half of the wavelength period, in pulse coding excitation, excitation of multiple groups of pulse widths is simultaneously required, and pulse width control accuracy directly influences excitation efficiency.
In an ultrasonic phased array instrument, the delay precision and the pulse width precision of the transmitted pulse are strictly required, the beam forming circuit of the common transmitting end is realized in an FPGA or a CPLD, the external independent beam forming delay chip has the defects of large occupied space, high cost, inflexible configuration and the like, and the simple clock counting circuit in the FPGA or the CPLD is limited by the main frequency of the FPGA or the CPLD and cannot reach the corresponding ns or subns precision of GHz.
In view of this, the present invention provides a control system and method for accurate delay and pulse width adjustment of phased array ultrasound transmissions.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a control system and a method for phased array ultrasonic emission precise delay and pulse width adjustment, the invention adopts a control circuit and a coarse adjustment circuit, and the fine-tuning circuit respectively realizes the precise modulation of the pulse transmission timing signal and the fine adjustment of the transmission power, thereby achieving the purposes of high transmission pulse precision and high transmission efficiency.
In order to solve the technical problems, the following technical scheme is adopted:
The control system for phased array ultrasonic emission accurate time delay and pulse width adjustment comprises:
a phase-locked loop circuit: for dividing the input clock signal CLK into multiple clock signals of the same frequency and different phases.
The control circuit: for receiving an input clock signal CLK and an output clock Lock signal Lock of the phase locked loop circuit, and then outputting pulse width, delay and enable signals through a register set.
A coarse adjustment circuit: and the clock signals are used for receiving multiple paths of common-frequency and different phases of the phase-locked loop circuit, and the independent coarse adjustment output signals are output after being processed by combining the pulse width, the delay and the enabling signals output by the register group.
Fine tuning circuitry: and the circuit is used for receiving each path of the coarse adjustment output signals of the coarse adjustment circuit, combining pulse width, delay and enabling signals output by the register set, performing path selection and logic operation processing on each path of the coarse adjustment output signals, and generating a fine adjustment output signal.
On the basis of the technical scheme, the pulse width output by the register set comprises a coarse pulse width CorseWidth and a fine pulse width FINEWIDTH, the coarse pulse width CorseWidth is output to the coarse tuning circuit, and the fine pulse width FINEWIDTH is output to the fine tuning circuit.
The delays of the register set outputs include a coarse delay CorseDelay and a fine delay FINEDELAY, the coarse delay CorseDelay is output to the coarse tuning circuit, and the fine delay FINEDELAY is output to the fine tuning circuit.
The enable signals output by the register set include an enable signal TxEn and an enable signal OE, the enable signal TxEn is transmitted to the coarse tuning circuit, and the enable signal OE is output to the fine tuning circuit.
On the basis of the technical scheme, the register set comprises a control register CTRL, a Delay register Delay and a pulse width register width.
The control register CTRL is configured to transmit the enable signal TxEn to the coarse tuning circuit, and the control register CTRL is also configured to output the enable signal OE to the fine tuning circuit.
The Delay register Delay is used to output a coarse Delay CorseDelay to the coarse tuning circuit, and the Delay register Delay is also used to output a fine Delay FINEDELAY to the fine tuning circuit.
The pulse width register width is used to output a coarse pulse width CorseWidth to the coarse tuning circuit, and the pulse width register width is also used to output a fine delay FINEDELAY to the fine tuning circuit.
On the basis of the technical scheme, the control circuit comprises a communication interface for reading and writing the register group, wherein the communication interface comprises an internal communication bus, an external Uart communication interface, an I2C communication interface or an SPI communication interface.
On the basis of the technical scheme, the coarse adjustment circuit comprises a delay counter and a pulse width counter.
The delay counter is used for receiving multiple paths of clock signals with the same frequency and different phases of the phase-locked loop circuit, and is also used for receiving a coarse delay CorseDelay and an enabling signal TxEn which are output by the register set; and combines the clock signal, the coarse delay CorseDelay and the enable signal TxEn to output a delay trigger signal to the pulse width counter.
The pulse width counter is used for receiving multiple paths of clock signals with the same frequency and different phases of the phase-locked loop circuit, the pulse width counter is also used for receiving a coarse pulse width CorseWidth output by the register set, and the pulse width counter is also used for receiving a delay trigger signal of the delay counter; and combining the clock signal, the coarse pulse width CorseWidth and the delay trigger signal to output a coarse tuning output signal to the fine tuning circuit.
On the basis of the technical scheme, the fine-tuning circuit comprises a delay selection unit, a width selection unit and a logic operation unit, wherein the input end of the delay selection unit is connected with the coarse-tuning circuit and the control circuit, the output end of the delay selection unit is connected with the logic operation unit, the input end of the width selection unit is connected with the coarse-tuning circuit and the control circuit, and the output end of the width selection unit is connected with the logic operation unit.
On the basis of the technical scheme, the delay selection unit comprises an A-way selector, wherein the A-way selector is used for receiving a rough adjustment output signal of the rough adjustment circuit, and the A-way selector is also used for receiving a fine delay FINEDELAY output by the register set; and the coarse tuning output signal and the fine tuning delay FINEDELAY are combined and operated to output a delay selection signal SDA to the logic operation unit.
On the basis of the technical scheme, the width selection unit comprises an operation selector and a B-path selector, and the operation selector comprises an adder and a selector.
The operation selector is used for receiving the fine delay FINEDELAY and the fine pulse width FINEWIDTH output by the register set, performing addition operation through the adder and the selector, adding the fine delay FINEDELAY and the fine pulse width FINEWIDTH values, and finally outputting a B-path selection code to the B-path selector.
The B-path selector is used for receiving a coarse adjustment output signal of the coarse adjustment circuit, and is also used for receiving a B-path selection code output by the operation selector; and outputting a width selection signal SDB to the logic operation unit after combining the coarse adjustment output signal and the B-path selection code.
On the basis of the technical scheme, the logic operation unit comprises a logic operator L0, wherein the logic operator L0 is used for receiving an enable signal OE output by the register set, the logic operator L0 is also used for receiving a delay selection signal SDA output by the A-way selector, and the logic operator L0 is also used for receiving a width selection signal SDB output by the B-way selector; and the enable signal OE, the delay selection signal SDA and the width selection signal SDB are combined in an operation mode to output a fine adjustment output signal.
The invention provides another technical scheme: the control method for the accurate delay and pulse width adjustment of phased array ultrasonic emission comprises the following steps:
s1, dividing an input clock signal CLK into multiple clock signals with the same frequency and different phases.
S2, receiving an input clock signal CLK and an output clock locking signal Lock, and then outputting pulse width, delay and enabling signals through a register set.
S3, receiving the clock signals with multiple paths of same frequencies and different phases, and processing the clock signals by combining pulse width, delay and enabling signals output by the register set to output an independent coarse adjustment output signal.
S4, receiving each path of coarse adjustment output signals, and combining pulse width, delay and enabling signals output by the register set to perform path selection and logic operation processing on each path of coarse adjustment output signals so as to generate fine adjustment output signals.
Due to the adoption of the technical scheme, the method has the following beneficial effects:
The invention provides a control system and a method for precise delay and pulse width adjustment of phased array ultrasonic emission, which mainly utilize a CPLD or an FPGA chip internal or external phase-locked loop circuit to generate one clock signal into multiple paths of common-frequency clock signals with different phases, and generate a counting circuit in the CPLD or the FPGA chip through programming according to the multiple-phase clock signals, thereby realizing precise subdivision delay and pulse width control, and achieving the precision of phase intervals.
The invention carries out coarse adjustment on multiple paths of clocks with the same frequency and different phases, wherein a coarse adjustment signal circuit with different phases is generated by using a coarse adjustment circuit, and concretely, coarse adjustment pulse generation is realized by using a delay counter and a pulse width counter two-stage counter through the coarse adjustment circuit. And then, the fine-tuning circuit gating and logic operation are utilized to realize fine-tuning precision signal selection of different phases, and the logic operation is combined to output pulse width signals of reference clock phase interval precision, so that the pulse adjustment resolution reaches sub-ns precision, the problem that the main frequency of an FPGA or CPLD is limited by hundreds of MHz and the simple counting precision is in the ns precision level is effectively solved, the emission performance of a phased array ultrasonic instrument can be effectively improved, and different precision realization is carried out according to different requirements.
Drawings
The invention is further described below with reference to the accompanying drawings:
fig. 1 is a schematic structural diagram of a control system for precise delay and pulse width adjustment of phased array ultrasonic emission according to an embodiment of the invention.
Fig. 2 is a schematic diagram of a phase-locked output phase relationship of a phase-locked loop circuit according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a control circuit according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a coarse tuning circuit according to an embodiment of the invention.
Fig. 5 is a timing diagram of a coarse tuning circuit according to an embodiment of the invention.
Fig. 6 is a schematic diagram of a fine tuning circuit according to an embodiment of the invention.
Fig. 7 is a schematic diagram of an algorithm for fine delay and fine pulse width of a fine tuning circuit according to an embodiment of the invention.
Detailed Description
The present invention will be further described in detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Referring to fig. 1-7, a phased array ultrasound transmission accurate delay and pulse width modulation control system includes a phase locked loop circuit 101 (PLL), a control circuit 102, a coarse tuning circuit 103, and a fine tuning circuit 104.
Referring to fig. 1 and 2, in particular, the pll circuit in fig. 1 is a pll frequency divider circuit, and generates clock signals with different phases and the same frequency at a fixed phase interval as shown in fig. 2. Specifically, the phase-locked loop circuit 101: for dividing the input clock signal CLK into multiple clock signals of the same frequency and different phases.
The phase-locked loop circuit 101 is further configured to output a clock LOCK signal LOCK to the control circuit 102.
The phase-locked loop circuit 101 described above may be implemented by an external phase-locked loop circuit 101 or a dedicated clock generation chip. Such as a CPLD or an FPGA internal analog phase-locked loop or an external phase-locked loop chip, etc. The input clock is typically in the order of MHz, such as 125MHz.
Specifically, the input clock signal CLK is divided into multiple clock signals of the same frequency and different phases. After the phase-locked loop is locked, the clock LOCK signal is valid, indicating that the output clock has stabilized. As shown in fig. 2, after the phase LOCK is stable, the LOCK signal goes high, indicating valid.
The pll circuit 101 is further configured to output clock signals C0, C1, C2 … … Cn from multiple clock signals with the same frequency and different phases, where n is a positive integer. Referring to fig. 2, in this embodiment, n is equal to 15, and then C0-C15 corresponds to 0 ° phase, 22.5 ° phase, …, 337.5 ° phase, and the interval is 1/16 cycle, corresponding to 22.5 ° phase. However, the phase control may be set to 4, 8, 16 or the like for other cases, and thus is not fixed to 16, and may be set as needed.
Referring to fig. 1 and 3, the control circuit 102: for receiving the input clock signal CLK and the output clock Lock signal Lock of the phase locked loop circuit 101, and then outputting pulse width, delay and enable signals through a register set.
Specifically, the control circuit 102 first stores the original phase information of the external clock signal in the control register CTRL, then invokes the information in the control register CTRL as a control parameter, and performs Delay or pulse width modulation operation on the received external clock signal together with the internal Delay register Delay or pulse width register width, so as to output pulse width, delay and enable signals.
As a further explanation of the present embodiment, the pulse widths of the register set output include a coarse pulse width CorseWidth and a fine pulse width FINEWIDTH, the coarse pulse width CorseWidth is output to the coarse tuning circuit 103, and the fine pulse width FINEWIDTH is output to the fine tuning circuit.
The delays of the register set outputs include a coarse delay CorseDelay and a fine delay FINEDELAY, the coarse delay CorseDelay is output to the coarse tuning circuit 103, and the fine delay FINEDELAY is output to the fine tuning circuit.
The enable signals output by the register set include an enable signal TxEn and an enable signal OE, the enable signal TxEn is transmitted to the coarse tuning circuit 103, and the enable signal OE is output to the fine tuning circuit.
As a further illustration of this embodiment, the control circuit 102 may be configured as a set of registers that may be used for the code sequence output. Specifically, the register set includes a control register CTRL, a Delay register Delay, and a pulse width register width. The control circuit 102 may be configured to control the output enable signal OE and the transmit enable signal TxEn, or may be configured to set a Pulse Repetition Frequency (PRF), and may implement TxEn output of a fixed PRF according to a counter circuit, for example, a PRF of 2KHz, txEn may be configured to synchronize with a subsequent circuit for at least 1 CLK clock cycle.
The number of bits of the coarse delay and the coarse pulse width in the control circuit 102 may be set as needed, and may be set to 4, 8, 16, etc. paths of phase control of the phase-locked loop circuit 101, and the number of bits of the register may be set to 4, 8, 16, 32, etc., not fixed to 16 bits, and may be set and adjusted as needed.
The control register CTRL is configured to transmit the enable signal TxEn to the coarse tuning circuit 103, and the control register CTRL is also configured to output the enable signal OE to the fine tuning circuit.
The Delay register Delay is used to output a coarse Delay CorseDelay to the coarse tuning circuit 103, and the Delay register Delay is also used to output a fine Delay FINEDELAY to the fine tuning circuit.
The pulse width register width is used to output a coarse pulse width CorseWidth to the coarse tuning circuit 103, and the pulse width register width is also used to output a fine delay FINEDELAY to the fine tuning circuit.
Further improvements are made on the basis of the above technical solution, the control circuit 102 includes a communication interface for reading and writing the register set, where the communication interface includes an internal communication bus, or a conventional external Uart communication interface, an I2C communication interface, or an SPI communication interface.
Referring to fig. 1, 4 and 5, the coarse tuning circuit 103: for receiving the clock signals C0, C1, C2 … … Cn of the phase-locked loop circuit 101, n is equal to 15 in this embodiment. And processing the pulse width, delay and enabling signals output by the register group, and outputting independent rough adjustment output signals SO, S1 and S2 … … S15.
As a further illustration of this embodiment, the coarse tuning circuit 103 includes a delay counter and a pulse width counter. When the control circuit 102 stores information of the external clock signal to the control register CTRL, it also provides an enable signal TxEn to the coarse tuning circuit 103 and informs the coarse tuning circuit 103 that the data is ready to be read. The coarse tuning circuit 103 now loads the data obtained from the control register CTRL into its own delay counter. At the same time, the coarse tuning circuit 103 further acquires the information of the coarse pulse width CorseWidth and the information of the enable signal TxEn sent from the control circuit 102. Since the control circuit 102 updates data in real time, the information obtained from it is fast and does not lose any significant point in time. The delay timer continuously monitors the clock signal according to the set frequency and compares the clock signal to calculate the difference value between the two time points, namely the hysteresis. The delay timer is triggered to start the pulse width timer when it finds that the absolute value of a time difference reaches a threshold. The pulse width timer will restart a new timer for pulse width counting. The pulse width counter can complete the regulation and control of the pulse length by repeating the operation for a plurality of times.
Specifically, the delay counter is configured to receive multiple clock signals C0, C1, C2 … … Cn with the same frequency and different phases of the phase-locked loop circuit 101, where n is equal to 15 in this embodiment. The delay counter is further configured to receive a coarse delay CorseDelay and an enable signal TxEn output by the register set; and outputs a delay trigger signal to the pulse width counter after combining the clock signals C0, C1, C2 … … C15, the coarse delay CorseDelay and the enable signal TxEn.
The pulse width counter is configured to receive multiple clock signals C0, C1, C2 … … Cn with the same frequency and different phases of the phase-locked loop circuit 101, where n is equal to 15 in the present embodiment. The pulse width counter is further used for receiving a coarse pulse width CorseWidth output by the register set, and the pulse width counter is further used for receiving a delay trigger signal of the delay counter; and combines the clock signals C0, C1, C2 … … C15, the coarse pulse width CorseWidth, and the delayed trigger signal to output coarse output signals SO, S1, S2 … … S15 to the fine tuning circuit 104.
Fig. 4 and 5 illustrate that the 0-phase clock C0 is set according to the coarse delay CorseDelay and the coarse pulse width CorseWidth, and the enable signal TxEn is used as a trigger signal to output a coarse tuning output signal S0 with a certain pulse width under the corresponding delay condition. S0 'is the output of S0 delayed by one C0 clock period under the C0 clock, and so on S1', S2', …, S15'.
The above-mentioned fig. 4 and 5 are illustrated with reference to the 0-phase clock C0, and the other C1-C15 can be seen by analogy, wherein the coarse tuning output signals S1, S2 … … S15 are obtained by combining the clock signals C1, C2 … … C15, the coarse pulse width CorseWidth and the delay trigger signal, which are not described in detail herein.
Fine adjustment circuit 104: for receiving the coarse tuning output signals SO, S1, S2 … … Sn of each of the coarse tuning circuits 103, where n is equal to 15 in this embodiment. And combining pulse width, delay and enabling signals output by the register set, performing channel selection and logic operation processing on each coarse adjustment output signal, and generating a fine adjustment output signal F0.
As a further explanation of this embodiment, referring to fig. 6, the fine tuning circuit 104 includes a delay selection unit, a width selection unit, and a logic operation unit, wherein an input end of the delay selection unit is connected to the coarse tuning circuit 103 and the control circuit 102, an output end of the delay selection unit is connected to the logic operation unit, an input end of the width selection unit is connected to the coarse tuning circuit 103 and the control circuit 102, and an output end of the width selection unit is connected to the logic operation unit.
As a further illustration of the present embodiment, the delay selection unit includes an a-way selector for receiving the coarse tuning output signals SO, S1, S2 … … Sn of the coarse tuning circuit 103, where n is equal to 15 in the present embodiment. The A-way selector is also used for receiving the fine delay FINEDELAY output by the register set; and the coarse tuning output signals SO, S1, S2 … … S15 and the fine tuning FINEDELAY are combined and operated to output a time delay selection signal SDA to the logic operation unit.
Specifically, referring to table 1, it is a table of the correspondence of the a-way selector, which way is selected by the a-way selector according to the value of the fine delay FINEDELAY [3:0] is a one-to-one correspondence.
TABLE 1A way selector correspondence table
| FINEDELAY [3:0] value (decimal) | SDA selection |
| 0 | S0 |
| 1 | S1 |
| … | … |
| 15 | S15 |
As a further explanation of the present embodiment, the width selecting unit includes an operation selector including an adder and a selector, and a B-way selector.
The operation selector is used for receiving the fine delay FINEDELAY and the fine pulse width FINEWIDTH output by the register set, performing addition operation through the adder and the selector, adding the fine delay FINEDELAY and the fine pulse width FINEWIDTH values, and finally outputting a B-path selection code to the B-path selector.
The B-path selector is configured to receive coarse tuning output signals SO, S1, S2 … … Sn of the coarse tuning circuit 103, where n is equal to 15 in this embodiment. The B-path selector is also used for receiving the B-path selection code output by the operation selector; and outputs a width selection signal SDB to the logic operation unit after the coarse adjustment output signals SO, S1, S2 … … S15 and the B-path selection code are combined and operated.
Specifically, referring to table 2, the B-way selector corresponds to a table, the operation selector is composed of an adder and a selector, the adding operation adds the fine delay FINEDELAY and the fine pulse width FINEWIDTH values, and the operation selector correspondingly selects one of the ways S0-S15 and S0'-S15' and outputs the code.
TABLE 2B way selector correspondence table
| Dw= FINEDELAY value+ FINEWIDTH (decimal) | SDB selection |
| < 16, I.e. DW less than 16 | S (DW), such as: dw=0, then S0 is selected; dw=1, then S1 is selected; … dw=15, then S15 is selected. |
| >=16， | S (DW-16)', as follows: s (DW), such as: dw=16, then S0' is selected; dw=17, then S1' is selected; … dw=31, then S15' is selected. |
As a further explanation of the present embodiment, the logic operation unit includes a logic operator L0, the logic operator L0 is configured to receive an enable signal OE output by the register set, the logic operator L0 is further configured to receive a delay selection signal SDA output by the a-way selector, and the logic operator L0 is further configured to receive a width selection signal SDB output by the B-way selector; and the enable signal OE, the delay selection signal SDA and the width selection signal SDB are combined in an operation mode to output a fine adjustment output signal F0.
Specifically, the present embodiment performs the operation according to the above description, referring to fig. 7, assuming that the fine delay value is 3, the fine pulse width value is 15, and the sum of the fine pulse width value and the fine pulse width value is greater than 16 (one period), and performs the calculation according to table 1 and table 2, S3 and S2' are selected as the gating paths, and logic or operation is performed as shown in fig. 7, so as to obtain the final fine output signal F0.
The fine tuning circuit 104 is more complex than the coarse tuning circuit 103 and mainly comprises two unit parts, namely a delay selection unit and a width selection unit. Both units are used for path selection. Specifically, the selection of the paths is realized through different operation relations. This delay selection unit is accomplished by the a-way selector being directly connected to the delay counter and the pulse width counter. The other width selecting unit is composed of an operation selector and a B-path selector. The operation selector includes an adder and a selector. The function of the adder is to add the information in the width register to the information in the delay counter. The selector functions to send a pulse with a delay count value greater than the width register value to the output of the width selector, i.e., the input of the logic operator L0. The logic operator L0 is a hardware logic element. The function of the system is to comprehensively analyze a plurality of signals according to a certain rule and then output a signal meeting the requirement for other components. The logic operator L0 in fig. 6 is used to form a one-out-of-three line selector together with the output terminals of the delay selection unit and the width selection unit to output the final fine-tuning output signal.
The invention uses the FPGA or CPLD internal phase-locked loop (PLL), the phase lock outputs multiple paths of clock signals with the same frequency and different phases, combines with multiple paths of clock counting circuits and cooperates with a logic circuit to realize the delay and pulse width control of phase-locked subdivision precision. The invention aims to design a general ultrasonic phased array subdivision accurate time delay and pulse width control circuit 102 implementation method, which can realize the accurate time delay and pulse width control function in an FPGA or CPLD, and the accuracy reaches the subns level.
The invention adopts a control circuit 102, a coarse adjustment circuit 103 and a fine adjustment circuit 104 to respectively realize the precise modulation of pulse transmission timing signals and the fine adjustment of the transmission power, thereby achieving the purposes of high transmission pulse precision and high transmission efficiency. Meanwhile, the system of the invention also has good expandability and upgrading performance.
In summary, in the phased array ultrasonic emission accurate delay and pulse width adjustment control system of the invention, a phase-locked loop technology is used to quickly and accurately measure the pulse period and can give very accurate measurement results within one second. In addition, the control mode can also change the interval time and the length between the pulses in real time, so that the control is more flexible. Meanwhile, the function of automatically compensating errors can be realized, so that the most accurate and reliable high-quality pulse waveform can be sent out every time, and the measurement precision is further improved. In addition, it is worth mentioning that the control system has the characteristics of strong universality and easy expansion, so that the control system is very suitable for all types of ultrasonic detection instrument equipment. In a word, the technical scheme of the invention can not only improve the performance of the existing equipment, but also reduce the production cost and the maintenance cost.
The present invention proposes another embodiment: the control method for the accurate delay and pulse width adjustment of phased array ultrasonic emission comprises the following steps:
S1, dividing an input clock signal CLK into multiple clock signals with the same frequency and different phases. After the phase-locked loop is locked, the clock LOCK signal is valid, indicating that the output clock has stabilized. After the phase LOCK is stable, the clock LOCK signal goes high, indicating valid.
S2, receiving an input clock signal CLK and an output clock locking signal Lock, and then outputting pulse width, delay and enabling signals through a register set.
S3, receiving the clock signals with multiple paths of same frequencies and different phases, and processing the clock signals by combining pulse width, delay and enabling signals output by the register set to output an independent coarse adjustment output signal.
S4, receiving each path of coarse adjustment output signals, and combining pulse width, delay and enabling signals output by the register set to perform path selection and logic operation processing on each path of coarse adjustment output signals so as to generate fine adjustment output signals.
The above is only a specific embodiment of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions or modifications made on the basis of the present invention to solve the substantially same technical problems and achieve the substantially same technical effects are encompassed within the scope of the present invention.
Claims (6)
1. The control system for accurate delay and pulse width adjustment of phased array ultrasonic emission is characterized by comprising:
a phase-locked loop circuit: for dividing the input clock signal CLK into multiple clock signals of the same frequency and different phases;
the control circuit: the phase-locked loop circuit is used for receiving an input clock signal CLK and an output clock locking signal Lock of the phase-locked loop circuit, and outputting pulse width, delay and enable signals through a register set;
A coarse adjustment circuit: the clock signals are used for receiving multiple paths of same-frequency and different-phase clock signals of the phase-locked loop circuit, and the independent coarse adjustment output signals are output after being processed by combining the pulse width, the delay and the enabling signals output by the register set;
Fine tuning circuitry: the circuit is used for receiving each path of the coarse adjustment output signals of the coarse adjustment circuit, combining pulse width, delay and enabling signals output by the register set, performing path selection and logic operation processing on each path of the coarse adjustment output signals, and generating fine adjustment output signals;
The fine adjustment circuit comprises a delay selection unit, a width selection unit and a logic operation unit, wherein the input end of the delay selection unit is connected with the coarse adjustment circuit and the control circuit, the output end of the delay selection unit is connected with the logic operation unit, the input end of the width selection unit is connected with the coarse adjustment circuit and the control circuit, and the output end of the width selection unit is connected with the logic operation unit;
The delay selection unit comprises an a-way selector,
The A-way selector is used for receiving a coarse adjustment output signal of the coarse adjustment circuit, and also used for receiving a fine delay FINEDELAY output by the register set; and the coarse tuning output signal and the fine delay FINEDELAY are combined and operated to output a delay selection signal SDA to the logic operation unit;
The width selection unit includes an operation selector including an adder and a selector,
The operation selector is used for receiving the fine delay FINEDELAY and the fine pulse width FINEWIDTH output by the register set, performing addition operation through the adder and the selector, adding the fine delay FINEDELAY and the fine pulse width FINEWIDTH values, and finally outputting a B-path selection code to the B-path selector;
The B-path selector is used for receiving a coarse adjustment output signal of the coarse adjustment circuit, and is also used for receiving a B-path selection code output by the operation selector; the coarse adjustment output signal and the B path selection code are combined and operated to output a width selection signal SDB to the logic operation unit;
the logic operation unit includes a logic operator L0,
The logic operator L0 is configured to receive an enable signal OE output by the register set, and the logic operator L0 is further configured to receive a delay selection signal SDA output by the a-way selector, and the logic operator L0 is further configured to receive a width selection signal SDB output by the B-way selector; and the enable signal OE, the delay selection signal SDA and the width selection signal SDB are combined in an operation mode to output a fine adjustment output signal.
2. The phased array ultrasound transmit accurate delay and pulse width modulation control system of claim 1, wherein: the pulse width output by the register set comprises a coarse pulse width CorseWidth and a fine pulse width FINEWIDTH, the coarse pulse width CorseWidth is output to the coarse adjustment circuit, and the fine pulse width FINEWIDTH is output to the fine adjustment circuit;
The delay output by the register set comprises a coarse delay CorseDelay and a fine delay FINEDELAY, the coarse delay CorseDelay is output to the coarse tuning circuit, and the fine delay FINEDELAY is output to the fine tuning circuit;
the enable signals output by the register set include an enable signal TxEn and an enable signal OE, the enable signal TxEn is transmitted to the coarse tuning circuit, and the enable signal OE is output to the fine tuning circuit.
3. The phased array ultrasonic emission accurate delay and pulse width modulation control system of claim 2, wherein: the register set comprises a control register CTRL, a Delay register Delay and a pulse width register width,
The control register CTRL is configured to transmit the enable signal TxEn to the coarse tuning circuit, and the control register CTRL is further configured to output the enable signal OE to the fine tuning circuit;
The Delay register Delay is used for outputting a coarse Delay CorseDelay to the coarse tuning circuit, and the Delay register Delay is also used for outputting a fine Delay FINEDELAY to the fine tuning circuit;
The pulse width register width is used to output a coarse pulse width CorseWidth to the coarse tuning circuit, and the pulse width register width is also used to output a fine delay FINEDELAY to the fine tuning circuit.
4. A phased array ultrasound transmit accurate delay and pulse width modulation control system according to claim 3, wherein: the control circuit comprises a communication interface for reading and writing the register group, wherein the communication interface comprises an internal communication bus, an external Uart communication interface, an I2C communication interface or an SPI communication interface.
5. The phased array ultrasound transmit precision delay and pulse width modulation control system of any of claims 1-4, wherein: the coarse tuning circuit includes a delay counter and a pulse width counter,
The delay counter is used for receiving multiple paths of clock signals with the same frequency and different phases of the phase-locked loop circuit, and is also used for receiving a coarse delay CorseDelay and an enabling signal TxEn which are output by the register set; the clock signal, the coarse delay CorseDelay and the enabling signal TxEn are combined and processed to output a delay trigger signal to the pulse width counter;
The pulse width counter is used for receiving multiple paths of clock signals with the same frequency and different phases of the phase-locked loop circuit, the pulse width counter is also used for receiving a coarse pulse width CorseWidth output by the register set, and the pulse width counter is also used for receiving a delay trigger signal of the delay counter; and combining the clock signal, the coarse pulse width CorseWidth and the delay trigger signal to output a coarse tuning output signal to the fine tuning circuit.
6. A control method of a phased array ultrasound transmit accurate delay and pulse width modulation control system as claimed in any one of claims 1 to 4, comprising:
s1, dividing an input clock signal CLK into multiple clock signals with the same frequency and different phases;
s2, receiving an input clock signal CLK and an output clock locking signal Lock, and then outputting pulse width, delay and enabling signals through a register set;
s3, receiving multiple paths of clock signals with the same frequency and different phases, and processing the clock signals by combining pulse width, delay and enabling signals output by the register set to output an independent coarse adjustment output signal;
S4, receiving each path of coarse adjustment output signals, and combining pulse width, delay and enabling signals output by the register set to perform path selection and logic operation processing on each path of coarse adjustment output signals so as to generate fine adjustment output signals.
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