CN118280723A

CN118280723A - Capacitor assembly and method for manufacturing capacitor assembly

Info

Publication number: CN118280723A
Application number: CN202311818815.6A
Authority: CN
Inventors: 丁海硕; 李云京; 崔正燮; 朴洸杓; 朴知勳; 元俊九; 全贤求; 李珖默
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2022-12-29
Filing date: 2023-12-27
Publication date: 2024-07-02

Abstract

The present disclosure provides a capacitor assembly and a method of manufacturing the capacitor assembly. The capacitor assembly may include: a first connection conductive layer and a second connection conductive layer; a plurality of conductive nanowires respectively connected to the first connection conductive layer and the second connection conductive layer; a conductor disposed between the first and second connection conductive layers and having a plurality of through holes in which the plurality of conductive nanowires are disposed; and a dielectric film disposed such that at least a portion of the dielectric film is disposed between the plurality of conductive nanowires and the electrical conductor in the plurality of through holes, wherein at least one of the plurality of conductive nanowires may have an aspect ratio of 1000 or more, the aspect ratio being a ratio of a length to a width of the at least one conductive nanowire.

Description

Capacitor assembly and method for manufacturing capacitor assembly

The present application claims the benefit of priority from korean patent application No. 10-2022-0189358 filed in the korean intellectual property office on month 29 of 2022 and korean patent application No. 10-2023-0014832 filed in the korean intellectual property office on month 3 of 2023, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a capacitor assembly and a method of manufacturing a capacitor assembly.

Background

As technology continues to develop, the need for small-volume electronic components in the form of chips with high capacitance is increasing. Therefore, in recent years, capacitors used in IT products such as smart phones, personal digital assistants, digital video cameras, digital still cameras, network systems, computers, monitors, tablet computers, laptop computers, netbooks, televisions, video game machines, smartwatches, automobiles, and the like are also required to be miniaturized and have high capacitance. The properties that become more and more important in the performance of capacitor components may be equivalent series inductance (ESL), capacitance per unit volume, and thinner thickness relative to unit capacitance.

A multilayer ceramic capacitor (MLCC) may use a material having a perovskite structure with a high dielectric constant as a dielectric, and may have a structure in which a plurality of dielectric layers repeatedly stacked are connected in parallel and a distance between electrodes is close while a thickness of the dielectric layers is reduced, thereby effectively increasing capacitance. However, the MLCC may have a limit in reducing the ESL and/or reducing the thickness, and as the MLCC is miniaturized, it may become increasingly difficult to ensure a breakdown voltage (BDV).

Disclosure of Invention

An aspect of the present disclosure is to provide a capacitor assembly and a method of manufacturing the capacitor assembly, which may facilitate a reduction in ESL and/or thickness thereof, and may also improve capacitance improvement efficiency (which does not mean relative efficiency with respect to MLCCs) as compared to MLCCs.

According to an aspect of the disclosure, a capacitor assembly may include: a first connection conductive layer and a second connection conductive layer; a plurality of conductive nanowires respectively connected to the first connection conductive layer and the second connection conductive layer; a conductor disposed between the first and second connection conductive layers and having a plurality of through holes in which the plurality of conductive nanowires are disposed; and a dielectric film disposed such that at least a portion of the dielectric film is disposed between the plurality of conductive nanowires and the electrical conductor in the plurality of vias. The at least one conductive nanowire of the plurality of conductive nanowires may have an aspect ratio of 1000 or more, the aspect ratio being a ratio of a length to a width of the at least one conductive nanowire.

According to an aspect of the present disclosure, a method of manufacturing a capacitor assembly may include: forming a bundle of a plurality of conductive nanowires covered with alumina; forming a wafer by vertically cutting the bundles of the plurality of conductive nanowires; forming a first connection conductive layer and a second connection conductive layer on one surface and the other surface of the wafer such that the plurality of conductive nanowires are connected to each other; forming a space inside the wafer by removing the alumina from the wafer; forming a dielectric film on a surface of each of the plurality of conductive nanowires and surfaces of the first and second connection conductive layers by depositing a dielectric material on the wafer; and forming an electrical conductor filling the space by depositing an electrically conductive material on the wafer.

Drawings

The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

Fig. 1 is a diagram schematically illustrating a second connecting conductive layer, conductive nanowires, and dielectric film in a capacitor assembly according to an embodiment of the present disclosure;

fig. 2 is a diagram schematically illustrating a capacitor assembly according to an embodiment of the present disclosure;

FIG. 3 is a diagram schematically illustrating a cross section taken along line I-I' of FIG. 2;

fig. 4 to 7 are diagrams schematically showing an arrangement form of conductive nanowire bundles in a capacitor assembly according to an embodiment of the present disclosure;

Fig. 8 is a diagram schematically illustrating a cross-section of a capacitor assembly according to another embodiment of the present disclosure;

fig. 9A to 11B are diagrams for illustrating a degree of freedom of design of a capacitor assembly in a manufacturing method according to the present disclosure;

Fig. 12 to 22 are diagrams illustrating a process of manufacturing a capacitor assembly according to an embodiment of the present disclosure;

fig. 23 is a diagram illustrating an aspect ratio (T1/W1) of each conductive nanowire of a capacitor assembly and a distance (L1) between adjacent conductive nanowires of the capacitor assembly according to an embodiment of the present disclosure;

Fig. 24-26 are diagrams illustrating alumina that may be used in a process for manufacturing a capacitor assembly according to an embodiment of the present disclosure;

fig. 27 to 33 are diagrams showing modified embodiments of fig. 16 to 22;

Fig. 34 is a diagram illustrating a modified embodiment of the capacitor assembly of fig. 33; and

Fig. 35 is a diagram illustrating a semiconductor package including a capacitor assembly according to an embodiment of the present disclosure.

Detailed Description

Hereinafter, preferred embodiments of the present disclosure will be described with reference to the accompanying drawings. However, the embodiments of the present disclosure may be modified in many different forms, and the scope of the present disclosure is not limited to the embodiments described below. In addition, embodiments of the present invention are provided to more fully explain the present disclosure to those skilled in the art. The shapes and sizes of elements in the drawings may be exaggerated for clarity of description. In addition, components having the same functions within the scope of the same concept shown in the drawings of each embodiment are described using the same reference numerals. X, Y and Z shown in the drawings may represent the length direction, width direction, and thickness direction of the capacitor assembly, respectively. In addition, throughout the specification, when an element is referred to as being "comprising" or "comprises" another element, it can be taken to mean comprising the other element without excluding the other element, unless the context clearly dictates otherwise.

Referring to fig. 1 to 4, the capacitor assembly 1 according to the present embodiment includes a plurality of conductive nanowires 120 (as first electrode portions), first and second connection conductive layers 121 and 122, a dielectric film 110, a conductor 130 (as second electrode portions), first and second terminals 141 and 142, and a protective layer 150.

The first electrode portion includes a plurality of conductive nanowires 120. Each of the plurality of conductive nanowires 120 extends in a Z-direction and is disposed spaced apart from one another in an X-direction and/or a Y-direction perpendicular to the Z-direction. In addition, hereinafter, the first electrode part will be referred to as a plurality of conductive nanowires 120 and used.

The plurality of conductive nanowires 120 are physically and electrically connected to each other through a first connection conductive layer 121 and a second connection conductive layer 122 to be described later.

Each of the conductive nanowires 120 can be formed of a conductive material. As a non-limiting example, each conductive nanowire 120 may be formed of a metal including at least one of nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), and copper (Cu), or an alloy thereof. Alternatively, each conductive nanowire 120 may be formed of a conductive ceramic such as titanium nitride (TiN) and/or tungsten nitride (WN).

Each of the conductive nanowires 120 can have, for example, a crystalline alloy, an amorphous alloy, or an amorphous mixed phase structure including nano-sized grains. For example, the crystal structure of the conductive nanowire 120 may be controlled by controlling the conditions (cooling rate, formation rate) of forming the conductive nanowire 120, but the scope of the present disclosure is not limited thereto.

The plurality of conductive nanowires 120 may have the same or different materials. As an example, the plurality of conductive nanowires 120 may all be nickel (Ni) nanowires. As another example, a portion of the plurality of conductive nanowires 120 may be nickel (Ni) nanowires, and the remaining portion of the plurality of conductive nanowires 120 may be copper (Cu) nanowires. As another example, the plurality of conductive nanowires 120 may include metal nanowires, alloy nanowires, and conductive ceramic nanowires.

The plurality of conductive nanowires 120 may have a shape that is at least one of a cylindrical shape and a polygonal pillar shape. For example, the plurality of conductive nanowires 120 may all have a cylindrical shape. As another example, all of the plurality of conductive nanowires 120 can have a polygonal columnar shape. As another example, a portion of the plurality of conductive nanowires 120 may have a circular pillar shape, and other ones of the plurality of conductive nanowires 120 may have polygonal pillar shapes.

A portion of the plurality of conductive nanowires 120 may form a bundle, and the bundle of the plurality of conductive nanowires (which may be referred to as a bundle of conductive nanowires or a bundle of nanowires) 100 may be arranged to form a repeating pattern. For example, as shown in fig. 4 and 7, the bundles 100 and 100' "of the plurality of conductive nanowires may have a circular cross section as a whole. In addition, as shown in fig. 5 and 6, the bundles 100' and 100″ of the plurality of conductive nanowires may have a hexagonal cross section as a whole. In addition, as shown in fig. 4 to 7, the bundles 100, 100', 100", 100'" of the plurality of conductive nanowires may be disposed such that bundles having a circular cross section or a hexagonal cross section are repeatedly disposed to form a pattern.

Within any one of the bundles of conductive nanowires 100, 100', 100", 100'", one conductive nanowire 120 and another conductive nanowire 120 may have different widths, different materials, and/or different cross-sectional shapes. For example, as shown in fig. 6, a bundle 100 "of a plurality of conductive nanowires may include conductive nanowires 120a, 120b, and 120c having different conductive materials. In this case, the shapes of the conductive nanowires 120a, 120b, and 120c within the bundle may be identical to each other. As another example, as shown in fig. 7, the bundle 100 '"of the plurality of conductive nanowires may include conductive nanowires 1210 and 1220 having different widths, but a central portion of the bundle 100'" of the plurality of conductive nanowires may have a structure provided with the conductive nanowire 1210 having a large width, and an outer peripheral portion thereof may have a structure provided with the conductive nanowire 1220 having a small width.

The first connection conductive layer 121 is disposed at one end of the plurality of conductive nanowires 120 to connect the plurality of conductive nanowires 120 to each other. The second connection conductive layer 122 is disposed at the other end portions of the plurality of conductive nanowires 120 to connect the plurality of conductive nanowires 120 to each other. The connection conductive layers 121 and 122 may extend from the top and bottom of the plurality of conductive nanowires 120 in the X-Y plane to cover both ends of the plurality of conductive nanowires 120, respectively, and may have a plate-like shape as a whole. The connection conductive layers 121 and 122 connect the plurality of conductive nanowires 120 in parallel with each other.

The connection conductive layers 121 and 122 may be formed of a conductive material. As a non-limiting example, the connection conductive layers 121 and 122 may be formed of a metal including at least one of nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), and copper (Cu), or an alloy thereof. Alternatively, the connection conductive layers 121 and 122 may be formed of conductive ceramics such as titanium nitride (TiN), tungsten nitride (WN), or the like. The connection conductive layers 121 and 122 and the conductive nanowire 120 may be formed of the same material, and each of the connection conductive layers 121 and 122 and the conductive nanowire 120 may be formed of nickel (Ni), as an example.

The connection conductive layers 121 and 122 may be formed by, for example, a thin film process (such as vapor deposition), a plating process, or a lamination process of laminating conductive films, but the embodiment thereof is not limited thereto.

The electrical conductor 130 surrounds the plurality of conductive nanowires 120. The conductive body 130 forms the overall external appearance shape (for example, the overall hexahedral shape) of the capacitor assembly 1 according to the present embodiment, and serves as the second electrode part of the capacitor assembly 1. That is, a dielectric film 110 (to be described later) is disposed between each of the plurality of conductive nanowires 120 and the conductive body 130, and charges of different polarities are applied to each of the plurality of conductive nanowires 120 and the conductive body 130 to form a capacitance through the dielectric film 110.

The conductive body 130 fills a space between a plurality of conductive nanowires 120, the sides of which are covered with a dielectric film 110 (to be described later). Further, the conductive body 130 is formed on the upper surface of the first connection conductive layer 121 connecting one ends of the plurality of conductive nanowires 120. The conductive body 130 may not be disposed on the second connection conductive layer 122 connecting the other ends of the plurality of conductive nanowires 120, but the scope of the embodiment is not limited thereto.

The conductive body 130 may be formed of a conductive material. As non-limiting examples, the electrical conductor 130 may include a metal including at least one of nickel (Ni), cobalt (Co), titanium (Ti), tungsten (W), palladium (Pd), and copper (Cu), or an alloy thereof. Alternatively, the conductive body 130 may be formed of conductive ceramics such as titanium nitride (TiN), tungsten nitride (WN), or the like.

The conductive body 130 may be formed by, for example, a thin film process (such as vapor deposition), a plating process, or the like, but the embodiment thereof is not limited thereto. By way of non-limiting example, the electrical conductor 130 may be formed by Atomic Layer Deposition (ALD).

The dielectric film 110 is disposed between each of the plurality of conductive nanowires 120 and the conductive body 130 in a form of covering the outer circumferential surfaces of the plurality of conductive nanowires 120. That is, the dielectric film 110 serves as a spacer to prevent an electrical short between the plurality of conductive nanowires 120 and the conductive body 130. As described above, since both ends of the conductive nanowire 120 are in contact with and connected to the connection conductive layers 121 and 122, the dielectric film 110 is not disposed between both ends of the conductive nanowire 120 and the connection conductive layers 121 and 122. Further, the dielectric film 110 is disposed between each of the connection conductive layers 121 and 122 and the conductive body 130. In addition, unlike the second connection conductive layer 122, the first connection conductive layer 121 may have a structure in which the entire surface thereof is covered with the dielectric film 110.

Dielectric film 110 may comprise, for example, a high-k material having a specific dielectric constant of 3 or greater. As a non-limiting example, the dielectric film 110 may include an oxide of at least one selected from tantalum (Ta), titanium (Ti), lanthanum (La), zirconium (Zr), barium (Ba), silicon (Si), and hafnium (Hf). As a non-limiting example, the dielectric film 110 may be provided in a multi-layered structure. In this case, the dielectric film 110 may have a double-layer structure including an oxide film including the above-described oxide and a nitride film including a nitride such as silicon nitride (SiN) provided in this order, but the scope of the present embodiment is not limited thereto.

The dielectric film 110 may be formed by vapor deposition such as Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), etc., but the embodiment thereof is not limited thereto.

The protective layer 150 covers the conductive body 130 and the second connection conductive layer 122. The protective layer 150 forms the overall appearance of the capacitor assembly 1 according to the present embodiment. The protective layer 150 may serve to protect the capacitor assembly 1 from external impact, conductive foreign matter, and the like. The protective layer 150 may cover the outer surface of the first connection conductive layer 121 and the outer surface of the second connection conductive layer 122, and may surround the conductive body 130. The protective layer 150 may provide an upper outer surface and a lower outer surface of the capacitor assembly.

For example, the protective layer 150 may include a thermoplastic resin such as polystyrene, vinyl acetate, polyester, polyethylene, polypropylene, polyamide, rubber, or acrylic, a thermosetting resin such as phenol, epoxy, polyurethane, melamine, or alkyd, a photosensitive resin, or parylene, and the protective layer 150 may be formed of silicon (Si) and other materials other than silicon (Si).

The protective layer 150 may be formed by, for example, coating a liquid insulating resin, laminating an insulating film, or vapor deposition. In the case of the insulating Film, a Dry Film (DF) containing a photosensitive insulating resin, a laminated Film of a polyimide (ABF, ajinomoto Build-up Film) containing no photosensitive insulating resin, or the like can be used.

The first terminal 141 may be electrically connected to the first connection conductive layer 121, and a portion of the first terminal 141 may be exposed through the protective layer 150 to become an anode or a cathode. The second terminal 142 may be electrically connected to the conductive body 130, and a portion of the second terminal 142 may be exposed through the protective layer 150 to become a cathode or an anode having a polarity different from that of the first terminal 141.

The terminals 141 and 142 may be formed of a conductive material including at least one of copper (Cu), silver (Ag), nickel (Ni), and tin (Sn). The terminals 141 and 142 may be formed through at least one of a paste printing process, a plating process, or a thin film process such as vapor deposition, but the present disclosure is not limited thereto. The terminals 141 and 142 may be formed in a multi-layered structure, but the present disclosure is not limited thereto.

Referring to fig. 8, a capacitor assembly according to another embodiment of the present disclosure may further include a barrier metal film 125 and a barrier dielectric film 111, as compared to a capacitor assembly according to an embodiment of the present disclosure. Therefore, in describing a capacitor assembly according to another embodiment of the present disclosure, only the barrier metal film 125 and the barrier dielectric film 111 will be described, and the description in the embodiment of the present disclosure may be equally applied to the rest of the configuration.

The barrier metal film 125 may be formed to surround an outer circumferential surface of the dielectric film 110, and the dielectric film 110 surrounds side surfaces of the plurality of conductive nanowires 120. Further, the barrier dielectric film 111 may be formed to surround the outer circumferential surface of the barrier metal film 125, and the barrier metal film 125 surrounds the outer circumferential surface of the dielectric film 110. That is, the barrier metal film 125 and the barrier dielectric film 111 may be sequentially disposed between the dielectric film 110 and the conductor 130. The barrier metal film 125 and the barrier dielectric film 111 may block transfer of charges or ions from the dielectric film 110 to the conductive body 130.

Hereinafter, a method of manufacturing a capacitor according to an embodiment of the present disclosure will be described. The capacitor assembly 1 of the present disclosure may be manufactured in the following order.

Referring to fig. 12 and 13, first, a nanowire bundle including a plurality of nanowires in which a plurality of conductive nanowires 120 are covered with alumina 200 is prepared. The substrate of the nanowire bundle may be heat treated and the adhesive may be hardened to prepare the nanowire bundle.

In this embodiment, a plurality of nanowires may be connected in one body to form a nanowire bundle, and the nanowire bundle may be vertically cut and cut into a thin plate shape to prepare a wafer having a three-dimensional structure including a plurality of vertically erected metal conductive nanowires. Here, the alumina 200 is a material for adhesion.

As described above, when a three-dimensional structure composed of nanowire bundles is fixed by heat treatment and then cut into an arbitrary size and processed into a wafer form, a large area can be simultaneously processed, thereby improving productivity, which can be easily applied to the existing FAB (fabrication) process.

In this case, in the basic structure of the three-dimensional structure prepared in the form of a wafer, it is easy to replace a part of the structure with a desired component or to form an additional structure by a FAB process. In addition, in the FAB process of the wafer, the components included in the basic structure thereof may be replaced with another necessary component, or the basic structure may be easily reworked to suit a specific structure, and the wafer may also be cut to a necessary size by controlling the mask. For example, as shown in fig. 9A and 9B, each diameter of the wafers W11 and W12 may be controlled so as to adjust the size of a capacitor assembly manufactured using these wafers in the X direction or the Y direction. In addition, as shown in fig. 10A and 10B, the thickness of each of the wafers W21 and W22 may be controlled so as to adjust the height in the Z direction of the capacitor assembly manufactured using these wafers. In addition, as shown in fig. 11A and 11B, the flat wafers W31 and W32 of the same size may be cut into inner regions having different sizes.

After the wafer is prepared, a process of smoothing the surface of the wafer by polishing and wet etching may be performed before performing the subsequent process.

Next, as shown in fig. 14, a conductive material is applied to the upper and lower ends of the wafer to form a first connection conductive layer 121 physically connecting the upper ends of the plurality of conductive nanowires 120 on the upper surface of the wafer, and a second connection conductive layer 122 physically connecting the lower ends of the plurality of conductive nanowires 120 on the lower surface of the wafer.

In an embodiment, the plurality of conductive nanowires 120 serves as a first electrode portion.

Next, as shown in fig. 15, a mask manufactured in a desired shape is attached to the first connection conductive layer 121 for an ALD process inside the wafer, and an open channel 171 is formed by removing a portion of the surface of the wafer where the mask is not provided to connect the inside and the outside.

In this case, the shape of the mask may be used to control the uniformity of the unit size and the specific pattern.

As shown in fig. 16 and 17, alumina 200 used as a binder is removed from the wafer through the open channel 171 by a metal wet etching/oxide wet etching process, and only the conductive nanowires 120 are left so that a space 172 is provided inside the wafer.

Next, as shown in fig. 18 and 19, a dielectric material is deposited in the space 172 through a process such as Atomic Layer Deposition (ALD), and a dielectric film 110 may be formed at the outer circumferential surface of each conductive nanowire 120 and the upper surface of the first connection conductive layer 121.

In some cases, multiple layers of patterns surrounding conductive nanowires may be formed with different compositions by ALD control or repeated etching/deposition.

In addition, the thickness of the pattern can be finely controlled by the deposition technique of ALD, and thus, three-dimensional patterns of various shapes as basic shapes can be manufactured.

For example, after further forming the barrier metal film to cover the outer peripheral surface of the dielectric film, the process of forming the barrier dielectric film may be further performed by redepositing the dielectric material to cover the outer peripheral surface of the barrier metal film.

Next, as shown in fig. 20 and 21, a conductive material may be additionally deposited on the space 172 prepared by removing the upper surfaces of the alumina 200 and the dielectric film 110 to form the conductive body 130 connected in a form surrounding the plurality of conductive nanowires 120.

In this case, as a method of depositing the conductive material, ALD may be used, but the disclosure is not limited thereto.

Further, the conductive body 130 is kept insulated from the plurality of conductive nanowires 120 by the dielectric film 110.

Next, as shown in fig. 22, in order to form the first terminal 141 shown in fig. 2 on the upper portion of the wafer, a groove portion 173 is processed to expose the first connection conductive layer 121, and the first terminal 141 is formed in the groove portion 173 to be connected to the first connection conductive layer 121. In this case, the first terminal 141 is spaced apart from the second electrode part 130.

Next, a second terminal 142 shown in fig. 2 is formed on the upper surface 131 of the second electrode portion 130.

Next, a protective layer 150 covering the surfaces of the second electrode part 130 and the second connection conductive layer 122 may be formed such that a portion of the first terminal 141 and a portion of the second terminal 142 are exposed to the outside, so that the capacitor assembly 1 of fig. 2 may be manufactured.

Referring to fig. 23, a capacitor assembly according to an embodiment of the present disclosure may include: the first and second connection conductive layers 121 and 122 are spaced apart from each other; a plurality of conductive nanowires 120 connected to the first and second connection conductive layers 121 and 122, respectively, and spaced apart from each other; a conductive body 130 filled between the first and second connection conductive layers 121 and 122 and having a plurality of through holes in which the plurality of conductive nanowires 120 are disposed; and a dielectric film 110 disposed between the first connection conductive layer 121 and the second connection conductive layer 122 such that at least a portion of the dielectric film 110 is disposed between the plurality of conductive nanowires 120 and the conductive body 130 in the plurality of through holes. The plurality of through holes of the conductive body 130 may correspond to the plurality of through holes TH of fig. 24 to 26.

Referring to fig. 23, a width W1 of at least one or each of the plurality of conductive nanowires 120 may be greater than 20nm and less than 70nm. More specifically, the width W1 of at least one or each of the plurality of conductive nanowires 120 may be 40nm or more and 60nm or less. The length T1 of at least one or each of the plurality of conductive nanowires 120 may be greater than 40 μm and less than 140 μm. More specifically, the length T1 of at least one or each of the plurality of conductive nanowires 120 may be 80 μm or more and 130 μm or less. Accordingly, an aspect ratio (T1/W1) of at least one or each of the plurality of conductive nanowires 120 may be 1000 or more. More specifically, an aspect ratio (T1/W1) of at least one or each of the plurality of conductive nanowires 120 may be 2000 or more and 3000 or less. Each of the distance L1, the width W1, the length T1, and the aspect ratio (T1/W1) may be measured as an average value of at least one (or several) complete conductive nanowires 120 among a plurality of conductive nanowires 120 included in a cross section of a capacitor assembly formed by polishing the capacitor assembly in a horizontal direction. The cross section may be applied to analysis using at least one of a Transmission Electron Microscope (TEM), an Atomic Force Microscope (AFM), a Scanning Electron Microscope (SEM), an optical microscope, and a surface profiler (surface profiler), and L1, W1, and T1 may be measured by visually confirming an image obtained according to the above-described analysis or image processing (e.g., pixel recognition based on color or brightness of pixels, pixel value filtering for pixel recognition efficiency, distance integration between recognized pixels, etc.).

Referring to fig. 24 to 26, aluminum oxide (Al ₂O₃) may have a plurality of through holes TH formed through an anodic oxidation process, and a plurality of conductive nanowires 120 of fig. 12, 23 to 26 may be formed in the plurality of through holes TH. The alumina (Al ₂O₃) may correspond to the alumina 200 of fig. 12 to 15. Since the conductive body 130 of fig. 23 may be filled in at least a portion of a space where alumina (Al ₂O₃) is located after removing alumina (Al ₂O₃), the conductive body 130 may have a plurality of through holes corresponding to the plurality of through holes TH.

Since the alumina (Al ₂O₃) -based anodizing process may form the plurality of through holes TH having a high aspect ratio of 1000 or more (preferably 2000 or more), the anodizing process may be a process for realizing the plurality of conductive nanowires 120 having a high aspect ratio of 1000 or more (preferably 2000 or more).

Alternatively, according to an alumina (Al ₂O₃) -based anodizing process, alumina (Al ₂O₃) may stably support side surfaces of the plurality of conductive nanowires 120 while forming the plurality of conductive nanowires 120 having a high aspect ratio of 1000 or more (preferably 2000 or more). Accordingly, defective factors (such as collapse, pattern lifting, deflection, etc.) of the plurality of conductive nanowires 120 can be suppressed.

Thus, a capacitor assembly according to embodiments of the present disclosure prepared based on aluminum oxide (Al ₂O₃) and/or an anodic oxidation process may include a plurality of conductive nanowires 120 having a high aspect ratio of 1000 or more, preferably 2000 or more. Since the aspect ratio of the plurality of conductive nanowires 120 increases, the number of the plurality of conductive nanowires 120 that can be disposed in the unit horizontal region may increase. Since the capacity of the capacitor assembly may increase as the number of the plurality of conductive nanowires 120 increases, the larger the number of the plurality of conductive nanowires 120 that can be disposed in the unit horizontal region, the higher the capacitance, with the same overall size of the capacitor assembly.

For example, since the aspect ratio of the plurality of deep trenches of the capacitor assembly formed based on the plurality of deep trenches of a general silicon wafer is about several tens, the capacitance thereof may be lower than that of the capacitor assembly according to the embodiment of the present disclosure in the case where the overall size of the capacitor assembly is the same.

In addition, the aluminum oxide (Al ₂O₃) and/or anodization process that can be used to fabricate the capacitor assembly according to embodiments of the present disclosure may be less expensive than a process of forming a plurality of deep trenches of a common silicon wafer, so that the productivity of the capacitor assembly according to embodiments of the present disclosure may also be higher.

The length T1 of each of the plurality of conductive nanowires 120 can be determined according to the total thickness of the capacitor assembly. Since the total thickness of the capacitor assembly may be one of the standards required of the capacitor assembly, the length T1 of each of the plurality of conductive nanowires 120 may also vary according to the type of the capacitor assembly. For example, when the total thickness required for the capacitor assembly is 60 μm, the length T1 of each of the plurality of conductive nanowires 120 may be 50 μm or more and less than 60 μm.

According to the anodic oxidation process, as the length T1 of each of the plurality of conductive nanowires 120 decreases, the width W1 of each of the plurality of conductive nanowires 120 may also be narrower. Accordingly, the aspect ratio (T1/W1) of the plurality of conductive nanowires 120 may not be greatly affected by the total thickness of the capacitor assembly, and may be 1000 or more (preferably 2000 or more).

The aluminum oxide (Al ₂O₃) of fig. 24 may be formed on the lower aluminum (Al) layer. For example, aluminum oxide (Al ₂O₃) may be formed by anodic oxidation in a portion of the aluminum (Al) layer, and a plurality of through holes TH of aluminum oxide (Al ₂O₃) may be formed by self-organization when forming aluminum oxide (Al ₂O₃). For example, in the anodic oxidation process, an electrolyte solution such as oxalic acid may be used as an anode, and the anodic oxidation process may include a process of applying a voltage to the electrolyte solution. For example, a portion of the plurality of through holes TH of fig. 25 near the aluminum (Al) layer may have a diameter narrower than a width of each of the plurality of through holes TH, and the portion of the plurality of through holes TH of fig. 25 near the aluminum (Al) layer is removed by horizontal cutting or etching. Therefore, as in the case of the alumina 200 of fig. 12, the diameter variation of the plurality of through holes TH can be almost eliminated.

Referring to fig. 26, a horizontal cross section of at least a portion of the plurality of through holes may have a shape close to an ellipse or a shape close to a polygon, instead of a perfect circle. The diameter of the near-elliptical shape or the near-polygonal shape may be an average value of the lengths of the portions disposed within the ellipse or the polygon from a virtual line passing through the center of the ellipse or the polygon. The average value may be an average value of measurement values obtained by repeating measurement of the length while rotating the direction of the virtual line by a specific angle.

Referring to fig. 23, a distance L1 between the plurality of conductive nanowires 120 may be 80nm or more and 120nm or less, and the distance L1 between the plurality of conductive nanowires 120 may be greater than the width W1. The relationship between the distance L1 and the width W1 and the distance L1 may be achieved through an anodic oxidation process of aluminum oxide (Al ₂O₃), but the present disclosure is not limited thereto. As an example, the distance L1 between the plurality of conductive nanowires 120 may be a distance between centers of adjacent conductive nanowires, but the present disclosure is not limited thereto.

The open channel 171 of fig. 27 and 28 may have a structure in which conductive nanowires 120 of the plurality of conductive nanowires 120 of fig. 15 disposed in the open channel 171 of fig. 16 are etched. For example, the conductive nanowires disposed in the open channels 171 of fig. 16 may be selectively etched according to a wet etching method before etching the alumina 200, and then the alumina 200 may also be etched according to a wet etching method. A photoresist may be temporarily formed on the upper surfaces of a portion of the plurality of conductive nanowires 120 before etching the alumina 200, and the photoresist may be removed after etching the alumina 200.

The dielectric film 110 of fig. 29 and 30 may be formed by Atomic Layer Deposition (ALD), and may also be formed on the lower surface of the open channel 171. The thickness uniformity of the dielectric film 110 formed by Atomic Layer Deposition (ALD) may be higher than when formed by other processes. Dielectric film 110 may then be annealed, as designed. The dielectric film 110 and the conductive body 130 may be formed in an external stacked structure in consideration of the alumina 200.

When the alumina 200 is etched, the degree of freedom of design of the space between the first connection conductive layer 121 and the second connection conductive layer 122 may be further increased. For example, filling a portion of the space with alumina 200 may be advantageous because the barrier metal film 125 and the barrier dielectric film 111 shown in fig. 8 are further added, and may be advantageous to widen the controllable range of widths and/or distances of the plurality of conductive nanowires 120.

The dielectric film 110 may contact the upper, lower, and side surfaces of the plurality of conductive nanowires 120 and contact the inner side surfaces of the conductive body 130. Accordingly, since the capacitor assembly according to the embodiment of the present disclosure forms capacitance not only in the horizontal direction by the side surfaces of the plurality of conductive nanowires 120, but also in the vertical direction by the upper and lower surfaces of the plurality of conductive nanowires 120, the capacitance improvement efficiency of the capacitor assembly can be further improved.

The first connection conductive layer 121 may have an open channel 171 through which a portion of the conductive body 130 is exposed through the open channel 171, and the other portion 110b of the dielectric film 110 may be disposed between the portion 130b of the conductive body 130 exposed through the open channel 171 and the second connection conductive body 122. Thus, additional capacitance may also be formed on the underside of open channel 171.

The plurality of conductive nanowires 120 may be arranged around a portion 130b of the electrical conductor 130 exposed through the open channel 171. Accordingly, since the capacitance formed in the plurality of conductive nanowires 120 can be effectively aggregated through the open channel 171, the equivalent series inductance (ESL) of the capacitor assembly according to the embodiment of the present disclosure can be further reduced.

The conductive body 130 of fig. 31 and 32 may fill the alumina-filled space between the first connection conductive layer 121 and the second connection conductive layer 122, and the portion 130b of the conductive body 130 may also be formed in the open channel 171. The conductive body 130 can be used not only as an electrode for forming a capacitance but also to improve the overall durability of the capacitor assembly based on the strong strength of the conductive material, and can also be used to improve the overall moisture-proof reliability of the capacitor assembly based on the high density according to the process of forming the conductive body 130.

The portion 130b of the conductive body 130 disposed in the opening channel 171 may have a protruding portion 130c protruding further upward than the upper surface of the first connection conductive layer 121, and the protruding portion 130c may serve as a second terminal of the capacitor assembly (similar in function to 142 in fig. 23) capable of providing capacitance to the outside. The number of portions protruding upward from the conductive body 130 may be one or more. The protruding portion 130c may be surrounded by the upper portion 110c of the dielectric film 110, and the width of the protruding portion 130c may be wider than the width of the portion 130b of the conductive body 130. Referring to fig. 34, the protruding portion 130d may have a width narrower than that of the portion 130b of the conductive body 130.

The layer of fig. 31 and 32 covering the portion of the dielectric film 110 disposed on the outermost portion of the capacitor assembly may correspond to the protective layer 150 of fig. 23, and may be formed after the formation of the conductive body 130. For example, the protective layer 150 may be implemented with polyimide to reduce the impact of external physical factors on the capacitor assembly.

One or more groove portions 173 of fig. 33 and 34 may be formed on the first connection conductive layer 121, and may serve as an arrangement space of a first terminal (141 of fig. 23) of the capacitor assembly capable of providing capacitance to the outside. The groove portion 173 may be formed by wet etching using a photoresist, for example.

Thereafter, a process of passivating the upper surface of the capacitor assembly may be performed, and a process of forming the first terminal (141 in fig. 23) in the groove portion 173 may be performed, and a process of passivating the first terminal may be performed. Then, according to the design, a process of forming an upwardly protruding portion of the conductive body 130 and an Under Bump Metal (UBM) on the upper surface of the first terminal and a process of plating the protruding portion and the first terminal may be performed.

Referring to fig. 35, a semiconductor package according to an embodiment of the present disclosure may include a semiconductor chip 220, a redistribution structure 210, and a capacitor assembly 100a (such as the capacitor assembly described above).

The redistribution structure 210 may include redistribution lines 212 electrically connected to the semiconductor chips 220. The line widths and spacings of the redistribution lines 212 may be less than those of a typical printed circuit board. Thus, the redistribution structure 210 may also be smaller than a typical printed circuit board. For example, the redistribution structure 210 may further include a redistribution insulating layer 211, a redistribution via 213, and redistribution pads 214 and 215, which may correspond to an insulating layer, a via, and a pad of a printed circuit board, respectively. For example, the redistribution structure 210 may be implemented according to Wafer Level Packaging (WLP) or Panel Level Packaging (PLP).

The semiconductor chip 220 may include a logic semiconductor chip and/or a memory semiconductor chip. The logic semiconductor chip may be a microprocessor (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Field Programmable Gate Array (FPGA), an Application Processor (AP), a digital signal processor, a cryptographic processor, a controller, or an Application Specific Integrated Circuit (ASIC)). The memory semiconductor chip may be a volatile memory such as a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM) or a nonvolatile memory such as a flash memory.

For example, the semiconductor chip 220 may be molded by a molding unit 240 such as an Epoxy Molding Compound (EMC), and may have a chip pad 225 through which signals or power is input and output. The semiconductor chip 220 may be mounted on the redistribution structure 210 by the chip bumps 230. The redistribution structure 210 may be mounted on pads 254 on the printed circuit board 250 by substrate bumps 260.

The capacitor assembly 100a according to an embodiment of the present disclosure may be electrically connected to the semiconductor chip 220 and disposed on the redistribution structure 210. For example, the capacitor assembly 100a may be embedded in the redistribution structure 210 or mounted on a lower surface of the redistribution structure 210. For example, since the capacitor assembly 100a may overlap the semiconductor chip 220 in the Z direction, the capacitor assembly 100a may be used as a pad side capacitor (LSC).

The capacitor assembly 100a according to embodiments of the present disclosure may be more advantageously reduced in thickness compared to the MLCCs, and thus may be advantageously disposed on the redistribution structure 210. Accordingly, since an electrical distance between the capacitor assembly 100a and the semiconductor chip 220 may be shortened, the capacitor assembly 100a may be advantageous for improving signal integrity of a signal input/output to the semiconductor chip 220 or power integrity of power input/output to the semiconductor chip 220.

In addition, as the operating frequency of the semiconductor chip 220 increases or the current consumption increases, the capacitor assembly 100a is a decoupling capacitor, and a low ESL may be required to increase the efficiency of reducing high frequency noise of the semiconductor chip 220. The capacitor assembly 100a according to the embodiment of the present disclosure may have a structure advantageous in reducing equivalent series inductance (ESL) compared to the MLCC, so that high frequency noise of the semiconductor chip 220 may be effectively reduced. For example, the ESL of the MLCC may be about 100pH and the ESL of the capacitor assembly 100a may be less than 5pH.

As described above, according to embodiments of the present disclosure, a capacitor assembly and a method of manufacturing a capacitor assembly may be advantageous in reducing ESL or reducing thickness thereof as compared to an MLCC, and may also achieve capacitance-enhanced efficiency (which does not mean relative efficiency with respect to an MLCC).

In addition, according to the embodiments of the present disclosure, a capacitor assembly that can overcome the limitations of miniaturization and high capacitance of a conventional capacitor having a three-dimensional structure may be advantageous to have a higher degree of freedom in design or reduce process costs, and may be advantageous to have stronger strength or higher reliability against moisture, as compared to a conventional capacitor having a three-dimensional structure.

In this specification, the expression "embodiment" as used in this disclosure does not mean the same embodiment and is provided to emphasize and describe different unique features. However, the embodiment presented above does not exclude implementation in combination with features of another embodiment. For example, unless there is a contradiction or contradiction description with the content in another embodiment, even if the content described in one specific embodiment is not described in another embodiment, it is to be understood that the description relating to the other embodiment.

The terminology used in the present disclosure is for the purpose of describing one embodiment only and is not intended to be limiting of the present disclosure. In this case, the singular includes the plural referents unless the context clearly dictates otherwise.

Although exemplary embodiments have been shown and described above, it will be readily appreciated by those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A capacitor assembly, comprising:

a first connection conductive layer and a second connection conductive layer;

a plurality of conductive nanowires respectively connected to the first connection conductive layer and the second connection conductive layer;

A conductor disposed between the first and second connection conductive layers and having a plurality of through holes in which the plurality of conductive nanowires are disposed; and

A dielectric film disposed such that at least a portion of the dielectric film is disposed between the plurality of conductive nanowires and the electrical conductor in the plurality of vias,

Wherein at least one conductive nanowire of the plurality of conductive nanowires has an aspect ratio of 1000 or greater, the aspect ratio being a ratio of a length to a width of the at least one conductive nanowire.

2. The capacitor assembly of claim 1, wherein the aspect ratio is 2000 or greater and 3000 or less.

3. The capacitor assembly of claim 1, wherein the at least one of the plurality of conductive nanowires has a length greater than 40 μιη and less than 140 μιη, and

The width of the at least one conductive nanowire of the plurality of conductive nanowires is greater than 20nm and less than 70nm.

4. The capacitor assembly of claim 3, wherein the at least one of the plurality of conductive nanowires has a length of 80 μιη or more and 130 μιη or less, and

The width of the at least one conductive nanowire of the plurality of conductive nanowires is 40nm or more and 60nm or less.

5. The capacitor assembly of claim 1, wherein a distance between adjacent ones of the plurality of conductive nanowires is 80nm or more and 120nm or less.

6. The capacitor assembly of claim 1, wherein a distance between adjacent ones of the plurality of conductive nanowires is greater than a width of the at least one of the plurality of conductive nanowires.

7. The capacitor assembly of claim 1, wherein the dielectric film is in contact with upper, lower, and side surfaces of the plurality of conductive nanowires and with an inside surface of the electrical conductor.

8. The capacitor assembly of claim 1 wherein the first connecting conductive layer has an open channel through which a portion of the electrical conductor is exposed, and

Another portion of the dielectric film is disposed between a portion of the electrical conductor exposed through the open channel and the second connecting conductive layer.

9. The capacitor assembly of claim 1 wherein the first connecting conductive layer has an open channel through which a portion of the electrical conductor is exposed, and

The plurality of conductive nanowires are arranged around the portion of the electrical conductor exposed through the open channel.

10. The capacitor assembly of claim 1, further comprising:

A protective layer covering an outer surface of the first connection conductive layer;

A first terminal connected to the first connection conductive layer and exposed from the protective layer; and

And a second terminal connected to the conductor and exposed from the protective layer.

11. The capacitor assembly of claim 1, further comprising:

and a protective layer covering the outer surfaces of the first and second connection conductive layers and surrounding the conductor.

12. The capacitor assembly of claim 11 wherein the protective layer comprises silicon and other materials different from silicon, and

The protective layer provides upper and lower outer surfaces of the capacitor assembly.

13. The capacitor assembly of claim 11, wherein the protective layer comprises polyimide.

14. The capacitor assembly of claim 1, wherein the plurality of conductive nanowires comprises at least one of titanium nitride and tungsten nitride, and

The electrical conductor comprises at least one of titanium nitride and tungsten nitride.

15. The capacitor assembly of claim 1, wherein the dielectric film comprises an oxide film and a nitride film disposed on the oxide film.

16. The capacitor assembly of claim 16, wherein the nitride film comprises silicon nitride.

17. The capacitor assembly of claim 1, further comprising:

A barrier metal film surrounding an outer peripheral surface of the dielectric film; and

A barrier dielectric film disposed between the barrier metal film and the electrical conductor.

18. A method of manufacturing a capacitor assembly, comprising the operations of:

forming a bundle of a plurality of conductive nanowires covered with alumina;

Forming a wafer by vertically cutting the bundles of the plurality of conductive nanowires;

forming a first connection conductive layer and a second connection conductive layer on one surface and the other surface of the wafer such that the plurality of conductive nanowires are connected to each other;

Forming a space inside the wafer by removing the alumina from the wafer;

Forming a dielectric film on a surface of each of the plurality of conductive nanowires and surfaces of the first and second connection conductive layers by depositing a dielectric material on the wafer; and

An electrical conductor filling the space is formed by depositing an electrically conductive material on the wafer.

19. The method of manufacturing a capacitor assembly of claim 18 wherein said operation of forming said bundle of said plurality of conductive nanowires comprises an anodic oxidation process of said alumina,

20. The method of manufacturing a capacitor assembly of claim 18, wherein at least one of the electrical conductor and the dielectric film is formed by atomic layer deposition.

21. The method of manufacturing a capacitor assembly according to claim 19, wherein the aspect ratio of the at least one of the plurality of conductive nanowires is 2000 or more and 3000 or less,

The at least one conductive nanowire of the plurality of conductive nanowires has a length of 80 μm or more and 130 μm or less,

The width of the at least one conductive nanowire of the plurality of conductive nanowires is 40nm or more and 60nm or less,

The distance between adjacent conductive nanowires of the plurality of conductive nanowires is 80nm or more and 120nm or less.