CN118280408B

CN118280408B - Hybrid 14T-SRAM cell, SRAM circuit, chip with Schmidt structure

Info

Publication number: CN118280408B
Application number: CN202410706157.XA
Authority: CN
Inventors: 卢文娟; 王闯; 彭春雨; 胡薇; 戴成虎; 赵强; 吴秀龙; 陈军宁
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2024-06-03
Filing date: 2024-06-03
Publication date: 2024-08-23
Anticipated expiration: 2044-06-03
Also published as: CN118280408A

Abstract

The invention belongs to the field of static random access memories, and particularly relates to a hybrid 14T-SRAM unit with a Schmidt structure, and a corresponding SRAM circuit and a memory chip thereof. The 14T-SRAM cell is composed of 4P-type TFET transistors, 8N-type TFET transistors, and 2 NMOS transistors. The invention forms a Schmitt inverter through 8 TFET transistors, and two inverters form a latch structure in a storage unit. Since the latch structure adopts a schmitt inverter design, the retention and read noise margin of the cell can be improved. In the scheme, a mode of breaking the latch structure is adopted, so that the writing speed and the writing noise margin of the unit are improved; and NTFET with drain voltage not lower than source voltage is used as a transmission control tube, so that forward bias current of TFET is eliminated, and static power consumption of the circuit is reduced. In addition, the invention multiplexes part of transistors in the unit and the array to improve the integration level of the circuit.

Description

Hybrid 14T-SRAM cell, SRAM circuit, chip with Schmidt structure

Technical Field

The invention belongs to the field of static random access memories, and particularly relates to a hybrid 14T-SRAM unit with a Schmidt structure, an SRAM circuit adopting the hybrid 14T-SRAM unit as a basic unit and a corresponding memory chip thereof.

Background

With the continuous development of electronic and internet technologies, the market has increasingly demanded high-performance Static Random Access Memories (SRAMs), which are mainly implemented by improving the integration level of circuits, and with the increase of the integration level of circuits, the power consumption problem of chips has also become serious, and the power consumption problem has become a primary challenge for researchers at present. In order to keep the product running, the market demand for low power chips with low operating voltage is becoming stronger. In a processor, an internet of things device and a mobile device, the SRAM occupies most of the chip area and generates the operation power consumption with the highest duty ratio; wherein, the static power consumption of the SRAM consumes more than 50% of the total power consumption. It becomes critical to reduce the static power consumption of SRAM. At present, research on reducing static power consumption of an SRAM under a subthreshold voltage is mostly focused on optimizing a peripheral logic circuit of the SRAM or introducing a read-write auxiliary circuit. However, the sub-threshold swing of conventional MOSFET devices is physically limited in low voltage applications, which greatly affects the switching characteristics of the MOSFET devices and causes the leakage current of the circuit to increase exponentially with voltage reduction, which is affected by boltzmann distribution. In summary, the above-mentioned inherent disadvantages of MOSFET devices greatly prevent their application in ultra-low power chips.

Compared with MOSFET devices, the Tunneling Field Effect Transistor (TFET) is used as a non-Boltzmann distributed device, has higher switching ratio and lower subthreshold swing, so that the TFET device has wide application prospect in the field of low voltage and low power consumption and has huge potential in replacing the MOSFET devices. But the application of TFET devices in SRAM still faces several challenges: 1. the TEFT devices have non-uniform source and drain doping and unidirectional conductivity, which results in that forward bias currents which are not controlled by the gate voltage can occur during operation, which greatly increases the static power consumption of the existing TFET SRAM and damages the voltage stability of the storage node. 2. The TFET device has smaller on current than the MOSFET device, so that the TFET device has weaker read-write capability and lower read-write noise margin. 3. Due to the delayed output saturation characteristics of TFETs, the VTC curve of TFET-based inverters approximates a straight line with a gentle slope, which results in a much smaller SNM (static margin noise, static Noise Margin) for a memory cell made up of TFET-inverter pairs than for a memory cell made up of MOSFET-inverter pairs.

Disclosure of Invention

In order to solve the problems of low noise margin, high static power consumption and low writing speed of the conventional TFET type SRAM circuit, the invention provides a hybrid 14T-SRAM unit with a Schmidt structure, and a corresponding SRAM circuit and a storage chip thereof.

The technical scheme provided by the invention is as follows:

A hybrid 14T-SRAM cell with a Schmitt structure is composed of 4 PTFET transistors P1, P2, P3, P4,8 NTFET transistors N1, N4, N5, N6, N7, N8, N9, N10, and two NMOS transistors N2, N3. The circuit connection relationship is as follows:

The sources of P1 and P2 are connected with the drain electrode of N4 by VDD; the drain electrode of the P1 is connected with the source electrode of the P3; the drain electrode of P2 is connected with the source electrode of P4; the grid electrode of P1 and the grid electrode of N2 are connected with a write bit line BL; the gates of P2 and N3 are connected with a write bit line BLB; the drains of P3, N2 and N5 are connected with the gates of P4, N6 and N8 and serve as a storage node Q; the grid electrodes of P3, N5, N7 and N9 are connected with the drain electrodes of P4, N3 and N6 and serve as a storage node QB; the sources of N4 and N5 are connected with the drain electrode of N7; the sources of N6 and N9 are connected with the drains of N8 and N10; the drain electrode of the N1 is connected with the source electrodes of the N2 and the N3; the sources of N1, N7, N8 and N10 are connected with GND; the grid electrode of N1 is connected with a write word line WL; the grid electrode of N10 is connected with a read word line RWL; the drain of N9 is connected to the read bit line RBL.

In the hybrid 14T-SRAM cell provided by the invention, P3, N4, N5 and N7 form one Schmitt inverter, P4, N6, N8 and N9 form another Schmitt inverter, and the two inverters form a latch structure in the memory cell. P1, P2 are write assist transistors. P3 and P4 are pull-up transistors, and N5, N6, N7 and N8 are pull-down transistors. N4 and N9 are feedback transistors. N1, N2, N3 constitute a unit transfer tube.

As a further improvement of the present invention, the operation logic for implementing data retention of a hybrid 14T-SRAM cell with a schmitt structure is as follows:

The write word line WL, the write bit lines BL, BLB, and the read word line RWL are all set to low level, and the read bit line RBL is set to high level; at this time, N1, N2, N3, N10 are turned off, P1, P2 are turned on, and the latch structure is in a latch state, thereby realizing data retention.

As a further improvement of the present invention, the operation logic for implementing data writing of the hybrid 14T-SRAM cell with schmitt structure is as follows:

First, the read word line RWL is set to a low level, the read bit line RBL is set to a high level, and the write word line WL is set to a high level. Then, the level states of the write bit lines BL and BLB are adjusted according to the written data, and the level states of the storage nodes Q and QB are rewritten through the write bit lines BL and BLB.

As a further improvement of the present invention, in the data writing operation logic, when data "1" needs to be written, BL is set to low level and BLB is set to high level. When the data "0" needs to be written, BL is set to high level and BLB is set to low level.

As a further improvement of the present invention, after the data writing operation is completed, the write word line WL is set to a low level, the write bit lines BL, BLB are set to a low level, P1, P2 are turned on, and the latch structure resumes the latch state.

As a further improvement of the present invention, the operation logic for implementing data reading of a hybrid 14T-SRAM cell with a schmitt structure is as follows:

First, the write word line WL and the write bit lines BL, BLB are both set to low level, and the read bit line RBL is connected to a capacitor having an initial potential VDD. Then, the read word line RWL is set to a high level, and at this time, if the level of the read bit line RBL is lowered, the read result is data "0". If the read bit line RBL remains high, the read result is a data "1".

The invention also comprises an SRAM circuit which comprises a memory array and a peripheral circuit which is matched with the memory array to realize the functions of data reading, writing and maintaining. The memory array is formed by arranging the mixed 14T-SRAM cells with the Schmidt structure according to the array mode. In the memory array, the write assist transistors P1 and P2 are shared by all memory cells in the same column, and the cell transfer transistor N1 is shared by all memory cells in the same column.

As a further improvement of the present invention, in the memory array, each memory cell of each row is connected to the same write word line WL and read word line RWL; the individual memory cells of each column are connected to the same set of write bit lines BL and BLB, and read bit line RBL.

The invention also includes a memory chip packaged by the SRAM circuit.

The technical scheme provided by the invention has the following beneficial effects:

The invention designs a 14T-SRAM unit by using 12 TFET transistors and 2 CMOS transistors, and the circuit fully utilizes the advantages of better switching characteristic and lower subthreshold swing of the TFET transistors under low voltage, adopts a mode of breaking a latch structure, and improves the write noise margin of the unit. The scheme adopts the Schmitt structure to form the latch structure of the SRAM, so that the noise margin of the circuit can be improved.

The 14T-SRAM scheme part designed by the invention adopts an N-type TFET transistor N1 with drain voltage not lower than source voltage all the time as a transmission control tube, and can eliminate forward bias current of a TFET device by matching with other two NMOS-type unit transmission tubes N2 and N3; the circuit uses multiple TFETs to reduce the static power consumption of the circuit.

The 14T-SRAM cell of the present invention also shares a portion of the transistors in the Schmitt structure with the read channel and multiplexes the cell transfer transistors in the same row and the write assist transistors in the same column in the memory array. Through the two means, the number of transistors in the array can be effectively reduced, and the integration level of the memory chip designed based on the 14T-SRAM unit is further improved.

Drawings

Fig. 1 is a circuit diagram of a hybrid 14T-SRAM cell with a schmitt structure provided in embodiment 1 of the present invention.

Fig. 2 is a circuit diagram of a schmitt trigger-based inverter and its output curve with a conventional inverter when the input terminal is changed from "0" to "1".

Fig. 3 is a circuit diagram of a memory array in an SRAM circuit provided in embodiment 2 of the present invention, in which the red frame portion is a portion of transistors commonly used in rows or columns.

Fig. 4 is a circuit diagram of an existing 6T TFET SRAM used in a simulation test.

Fig. 5 is a circuit diagram of an existing read-write separation type 8T TFET SRAM used in a simulation test.

Fig. 6 is a signal flow diagram of a data storage function test performed by the inventive arrangements in a simulation test.

Fig. 7 is a graph showing voltage changes of each storage node when data of one of the storage cells in the storage array according to the embodiment of the present invention is rewritten in a simulation test.

Fig. 8 is a graph showing the transmission characteristics of the remaining noise margin with voltage for three schemes under different operating voltages in a simulation test.

FIG. 9 is a graph showing the transmission characteristics of the read noise margin versus voltage for three schemes under different operating voltages in a simulation test.

FIG. 10 is a graph showing the transfer characteristics of the write noise margin versus voltage for three schemes under different operating voltages in a simulation test.

FIG. 11 is a graph of static power consumption versus power consumption for three schemes under different operating voltages in a simulation test.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Example 1

The embodiment provides a hybrid 14T-SRAM cell with a Schmidt structure, which is composed of 4P-type TFET transistors P1, P2, P3, P4, 8N-type TFET transistors N1, N4, N5, N6, N7, N8, N9, N10, and two NMOS transistors N2, N3. The circuit unit is a basic unit for realizing data reading, writing and holding in the SRAM, and the TFET transistor is mainly used as a basic element, so that the advantages of better switching characteristic and lower subthreshold swing of the TFET transistor under low voltage can be fully utilized, and the write noise margin of the unit is improved in a mode of breaking a latch structure on the basis. As shown in fig. 1, the circuit connection relationship of the hybrid 14T-SRAM cell of the present embodiment is as follows:

The sources of P1 and P2 are connected with the drain electrode of N4 by VDD; the drain electrode of the P1 is connected with the source electrode of the P3; the drain electrode of P2 is connected with the source electrode of P4; the grid electrode of P1 and the grid electrode of N2 are connected with a write bit line BL; the gates of P2 and N3 are connected to write bit line BLB. The drains of P3, N2, N5 are connected to the gates of P4, N6, N8 and serve as storage node Q. The gates of P3, N5, N7, N9 are connected to the drains of P4, N3, N6 and serve as the storage node QB. The sources of N4 and N5 are connected with the drain electrode of N7; the sources of N6 and N9 are connected with the drains of N8 and N10; the drain electrode of N1 is connected with the source electrodes of N2 and N3. The sources of N1, N7, N8 and N10 are connected with GND; the grid electrode of N1 is connected with a write word line WL; the grid electrode of N10 is connected with a read word line RWL; the drain of N9 is connected to the read bit line RBL.

In the hybrid 14T-SRAM cell shown in FIG. 1, P3, N4, N5, N7 constitute one Schmitt inverter, P4, N6, N8, N9 constitute another Schmitt inverter, and both inverters constitute a latch structure in the memory cell. The present embodiment uses a schmitt structure to form the latch structure of the SRAM, and a typical schmitt structure is shown in part (a) of fig. 2. As can be seen in connection with the signal flow diagram of part (b) of fig. 2, for a conventional inverter, when the input voltage transitions from "0" to "1", the output voltage (Vout) starts to transition from "1" to "0" once the input voltage (Vin) approaches the threshold voltage Vth of the pull-down transistor. However, for a schmitt inverter, when Vout is "1" at the beginning, the feedback transistor N3 is turned on, causing the voltage at the node Vx to rise. When vin=vx+vth, the output voltage will start to switch from "1" to "0". Thus, the minimum voltage required for the schmitt inverter to switch the output from high to low increases, and the switching time is reduced.

Therefore, after the schmitt structure is adopted to form the latch structure, the characteristic of the inverter can be improved, so that the SRAM unit has higher noise margin.

In the circuit, P1, P2 are write assist transistors. Both are turned on during the data retention and data read phases and turned on or off during the data write phase by the bit line voltage control of the write bit lines BL and BLB. P1 and P2 break the latch structure of two inverters, and can improve the writing capability of the SRAM unit. P3 and P4 are pull-up transistors, and N5, N6, N7 and N8 are pull-down transistors. The pull-up transistor is used for pulling up the stored data to a high level; the pull-down transistor is used for pulling down the stored data to a low level; n4, N9 are feedback transistors used to improve the VTC of TFET-based inverters. N1, N2, N3 constitute a cell transfer tube, N1, N2, N3 form an effective discharge path at the time of writing operation, thereby improving cell writing stability. In particular, the unit transmission tubes N2 and N3 in the embodiment adopt NMOS tubes, which can eliminate the problem of forward bias leakage current caused by the existence of forward bias voltage in the TFET tubes.

In order to make the scheme of the hybrid 14T-SRAM cell with the schmitt structure provided in this embodiment clearer, the following details are given on the operation logic and the working principle of the hybrid 14T-SRAM cell according to three types of operations of data retention, data reading and data writing:

1. Data retention

In this embodiment, the operation logic for implementing data retention of the hybrid 14T-SRAM cell with a Schmitt structure is as follows:

In the data hold state, the write word line WL, the write bit lines BL, BLB, and the read word line RWL are all set to low level, and the read bit line RBL is set to high level; at this time, N1, N2, N3, N10 are turned off, P1, P2 are turned on, and the latch structure is in a latch state, so that stability of the SRAM cell in a retention state is ensured, i.e., data retention is realized.

In the circuit design scheme of the embodiment, as the source electrode of the N1 is always grounded, the drain electrode potential of the N1 is always higher than the source electrode potential, so that forward bias current which is not controlled by a grid electrode of a TFET tube is avoided, and the static power consumption of the 14T-SRAM unit is reduced.

2. Data writing

The operation logic for realizing data writing of the hybrid 14T-SRAM unit with the Schmitt structure provided by the embodiment is as follows:

First, the read word line RWL is set to low level, the read bit line RBL is set to high level, the write word line WL is set to high level, at this time N10 is turned off, and N1 is kept on. Then, the level states of the write bit lines BL and BLB are adjusted according to the written data, and the level states of the storage nodes Q and QB are rewritten through the write bit lines BL and BLB. Specifically, in the operation logic for data writing, when data "1" needs to be written, the write bit line BL is set to a low level and the write bit line BLB is set to a high level. When the data "0" needs to be written, the write bit line BL is set to a high level and the write bit line BLB is set to a low level.

The following describes in detail the complete process of implementing data writing in the scheme of this embodiment, with reference to two different cases of original storage data and written data of the storage node respectively:

2.1 write "0" operation

Assume that the data originally stored in the hybrid 14T-SRAM cell is "1", i.e., the level states of the two storage nodes are: when data "0" needs to be written in the hybrid 14T-SRAM cell, the write word line WL is set to high level, the write bit line BL is set to high level, and the write bit line BLB is set to low level. At this time, N3 is turned off, P1 is turned off, N1 is turned on, N2 is turned on, and P2 is turned on; the storage node Q is discharged to ground through N2, N1, falls to a low state, and inverts the level of the storage node QB through a latch structure. The power supply VDD charges the storage node QB through P2 and P4, so that the voltage of the storage node QB is rapidly increased to a high level, and after the process, the level states of the two storage nodes are inverted to be: q= "0", qb= "1". I.e., the write "0" operation is completed.

2.2 Write "1" operation

Assume that the data originally stored in the hybrid 14T-SRAM cell is "0", i.e., the level states of the two storage nodes are: when data "1" needs to be written in the hybrid 14T-SRAM cell, the write word line WL is set to high level, the write bit line BL is set to low level, and the write bit line BLB is set to high level. At this time, N2 is turned off, P2 is turned off, N1 is turned on, N3 is turned on, and P1 is turned on; the storage node QB discharges to the ground through N3 and N1, is reduced to a low level state, and enables the level of the storage node Q to be inverted through a latch structure; the power supply VDD charges the storage node Q through P1 and P3, and rapidly increases the voltage of the storage node Q to a high level. After this process, the level states of the two storage nodes are flipped as: q= "1", qb= "0". I.e. the write "1" operation is completed.

After the data writing operation is completed, the write word line WL should be set to the low level again, and the write bit lines BL and BLB should be set to the low level, and at this time, P1 and P2 are turned on, and the latch structure is restored to the latch state again.

When the hybrid 14T-SRAM unit of the embodiment executes data writing, the N1 always keeps the drain voltage not lower than the source voltage, so that the forward bias current of the TFET tube can be effectively avoided. Meanwhile, in the embodiment, a write interrupt mode is adopted, and a latch structure formed by two inverters is interrupted by using P1 and P2, so that the write-in capability of the unit can be improved.

(III) data reading

In the hybrid 14T-SRAM cell provided in the present embodiment, the data reading process is completed by means of the read word line RWL and the read bit line RBL independently. Specifically, the operation logic for implementing data reading of the hybrid 14T-SRAM cell with the schmitt structure in this embodiment is as follows:

First, the write word line WL and the write bit lines BL, BLB are both set to low level, and at this time, P1 and P2 are turned on. The read bit line RBL is connected with a capacitor with the initial potential of VDD, namely, the read bit line keeps high level in the initial state.

Then, the read word line RWL is set to a high level, and at this time, N10 is turned on. In this case, if the data originally stored in the cell is "0", i.e., "q=0, qb=1", the transistor N9 having the gate connected to the storage node QB is also turned on. At this time, N9 and N10 form a discharge path, and the read bit line RBL is discharged through N9 and N10, thereby lowering the level of the read bit line RBL. If the data originally stored in the cell is "1", i.e. "q=1, qb=0", the transistor N9 with the gate connected to the storage node QB is in an off state. At this time, N9 and N10 cannot form a discharge path, and the read bit line RBL cannot be discharged through N9 and N10, so that the read bit line RBL remains at a high level.

In summary, if the level of the read bit line RBL is lowered, the read result is data "0". If the read bit line RBL remains high, the read result is a data "1".

When the circuit scheme is actually applied, a plurality of mixed 14T-SRAM units form a storage array of an SRAM, read bit lines RBL of the mixed 14T-SRAM units in the same column in the storage array are usually connected to one input port of a sense amplifier SA, and the other input port of the sense amplifier is connected with a reference level Vref which is usually smaller than VDD. At this time, the sense amplifier SA quantizes the corresponding stored data according to the magnitude relation between the bit line voltage V _RBL of the read bit line RBL and the reference level Vref.

Specifically, if the data originally stored in the cell is "0", i.e. "q=0, qb=1", the bit line voltage of RBL will drop, and thus V _RBL < Vref, the output of SA is low, i.e. "0" is read from the storage node. Conversely, if the data originally stored in the cell is "1", i.e. "q=1, qb=0", the bit line voltage of RBL will remain high, which results in V _RBL > Vref, and the output of SA is high, i.e. "1" for reading the data of the storage node.

In combination with the above, it can be seen that the transistor N9 is part of the schmitt structure in the latch structure on the one hand, and also forms a read channel together with the transistor N10 on the other hand. Therefore, the circuit design scheme provided by the embodiment can share the schmitt structure and the read channel, so that the number of transistors in the unit circuit is reduced.

Example 2

Based on the scheme of embodiment 1, this embodiment further provides an SRAM circuit, which includes a memory array, and a peripheral circuit that cooperates with the memory array to implement data reading, writing, and holding functions. As shown in fig. 3, the memory array is formed by arranging hybrid 14T-SRAM cells having a schmitt structure as in example 1 in an array manner. In particular, in the memory array of the SRAM circuit of the present embodiment, all memory cells in the same column share the write assist transistors P1 and P2, and all memory cells in the same column share the cell transfer transistor N1.

Further, in the memory array of the SRAM circuit of the present embodiment, the respective memory cells of each row are connected to the same write word line WL and read word line RWL; the individual memory cells of each column are connected to the same set of write bit lines BL and BLB, and read bit line RBL. The level state of the storage nodes in each memory cell can be "flipped" by means of the write word lines WL and the write bit lines BL and BLB to enable writing of the stored data. The level state of the storage node in each storage unit can be "identified" by means of the write word line RWL and the write bit line RBL, so that the reading of the stored data is realized.

In practical applications, the SRAM circuit in this embodiment is mainly manufactured and sold in the form of a memory chip product, so this embodiment also provides a memory chip, which belongs to the SRAM and is packaged by the SRAM circuit described above.

Simulation test

In order to test the data storage function of the hybrid 14T-SRAM unit with the Schmidt structure and the corresponding SRAM circuit, the superiority of the related circuit in the performance of noise tolerance, function and the like is verified. In the experimental process, a technician takes the scheme of the invention as an experimental group, tests the data storage function of the scheme, selects the classical 6T TFET SRAM and the read-write separated 8T TFET SRAM as shown in fig. 4 and 5 as a comparison group, compares the noise margin and the power consumption of the scheme of the invention with those of the two existing schemes under different states, and the experimental process is specifically as follows;

1. memory function test

In this experiment, the skilled artisan devised an SRAM circuit comprising a2 x 2 memory array based on the 14T-SRAM cell of example 1 of the present invention. In the experiment, 14T-SRAM units in a storage array are selected to respectively perform data read-write function test, and the working states of the circuits are switched according to the sequence of data holding, writing 1, reading 1, writing 0, reading 0 and data holding in the test process, so that the obtained signal flow diagram is shown in figure 6.

Next, the initial storage data of 4 storage units in the 2×2 storage array is set to "1", that is, the level states of the storage nodes are "Q1, Q2, Q3, q4=1, QB1, QB2, QB3, qb4=0", and then, the storage unit No. 1 is selected to perform the operation of writing "0", the level states of the storage nodes corresponding thereto are adjusted to "q1=0, qb1=1", and the change of the signals of the storage nodes Q1, Q2, Q3, Q4, QB1, QB2, QB3, QB4 corresponding to the operation procedure is shown in fig. 7. The figure can be seen: the operation in the experiment can successfully write a "0" in memory cell number 1, and the data stored in the other 3 memory cells is unchanged.

As can be seen from fig. 6 and 7, the hybrid 14T-SRAM cell of the present invention has a complete data storage function, and is capable of performing data retention, data writing and data reading, and thus can be used as a basic unit of an SRAM memory chip.

2. Performance comparison

2.1 Noise margin

(2.1.1) Maintaining noise margin

In the experiment, the scheme (14T) and the two control group schemes (6T and 8T) are respectively taken as test objects, when the three are tested to carry out data retention under different working voltages of 0.5V, 0.6V, 0.7V, 0.8V and 0.9V, the obtained data of the retention noise margin (marked as HSNM) are used for drawing a transmission characteristic curve (VTC) of the retention noise margin with voltage according to the experimental data, and the transmission characteristic curve (VTC) is shown in figure 8.

From a review of the data in fig. 8, it can be found that: the 14T scheme of the present invention has a greater holding noise margin than the conventional 6T and 8T schemes. Analysis of the solution of the present invention has the above-mentioned advantages mainly because the schmitt structure can improve the hold-on noise margin of the circuit.

(2.1.2) Read noise margin

In the experiment, the scheme of the invention and the two comparison group schemes are respectively used as test objects, when the three schemes perform data reading operation under different working voltages of 0.5V, 0.6V, 0.7V, 0.8V and 0.9V, the obtained data of the read noise margin (denoted as RSNM) are tested, and the transmission characteristic curve of the read noise margin with voltage as shown in figure 9 is drawn by combining experimental data.

From an examination of the data in fig. 9, it can be seen that: the 14T scheme of the present invention has a greater read noise margin than conventional 6T and 8T schemes. Analysis of the higher read noise margin of the inventive scheme is also caused by the schmitt structure.

(2.1.3) Write noise margin

In the experiment, the scheme of the invention and the two comparison group scheme are respectively used as test objects, when the three are tested to carry out data writing operation under different working voltages of 0.5V, 0.6V, 0.7V, 0.8V and 0.9V, the obtained data of the writing noise margin (which is recorded as WSNM) is obtained, and the transmission characteristic curve of the writing noise margin with voltage is drawn by combining experimental data as shown in figure 10.

From a review of the data in fig. 10, it can be found that: the 14T scheme of the present invention has a larger write noise margin than the conventional 6T and 8T schemes. Analysis of the present solution produces significant advantages in write noise margin because: the 14T scheme breaks the latch structure of the two inverters during the write phase, which can improve the write capability of the memory cell, thereby making the write noise margin of the circuit higher.

2.2 Static Power consumption

In the data holding state, the experiment takes the scheme of the invention and the two-comparison group scheme as test objects, tests static power consumption of the three under different working voltages of 0.5V, 0.6V, 0.7V, 0.8V and 0.9V, and draws a power consumption comparison chart shown in figure 11 according to experimental data.

From an examination of the experimental data in fig. 11, it can be found that: the static power consumption of the 14T scheme of the present invention is significantly lower compared to the 6T and 8T schemes of the control group, and the static power consumption of the 6T and 8T schemes is close.

The static power consumption is the overall power consumption of the SRAM circuit in the data holding state, and the reason for analyzing the obvious difference of the three static power consumption is as follows: the 6T and 8T use the unidirectional-conduction source external NTFET as a transmission transistor, which causes forward bias current in the two circuits, thereby improving the static power consumption of the SRAM unit. The drain voltage of the transmission tube N1 used by 14T is not lower than the source voltage all the time, so that forward bias current is eliminated, and the problem of forward bias current existing when the unidirectional-conduction source external NTFET tubes are used as the transmission transistors by 6T and 8T in a holding state is solved.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims

1. A hybrid 14T-SRAM cell with a schmitt structure, characterized in that it consists of 4 PTFET transistors P1, P2, P3, P4,8 NTFET transistors N1, N4, N5, N6, N7, N8, N9, N10, and two NMOS transistors N2, N3; the circuit connection relationship is as follows:

2. The hybrid 14T-SRAM cell with a schmitt structure of claim 1, wherein: in the hybrid 14T-SRAM cell, P3, N4, N5, N7 form one Schmitt inverter, P4, N6, N8, N9 form another Schmitt inverter, and the two inverters form a latch structure in the memory cell; p1 and P2 are write assist transistors; p3 and P4 are pull-up transistors, and N5, N6, N7 and N8 are pull-down transistors; n4 and N9 are feedback transistors; n1, N2, N3 constitute a unit transfer tube.

3. The hybrid 14T-SRAM cell with a schmitt structure of claim 2, wherein the operating logic to implement data retention is as follows:

4. The hybrid 14T-SRAM cell with a schmitt structure of claim 1, wherein the operating logic to implement the data writing is as follows:

first, the read word line RWL is set to a low level, and the read bit line RBL is set to a high level; the write word line WL is set to high; then, the level states of the write bit lines BL and BLB are adjusted according to the written data, and the level states of the storage nodes Q and QB are rewritten through the write bit lines BL and BLB.

5. The hybrid 14T-SRAM cell with a schmitt structure of claim 4, wherein: in the operation logic of data writing, when data '1' needs to be written, BL is set to be low level, and BLB is set to be high level; when the data "0" needs to be written, BL is set to high level and BLB is set to low level.

6. The hybrid 14T-SRAM cell of claim 5, wherein after the data writing operation is completed, the write word line WL is set to low, the write bit lines BL, BLB are set to low, P1, P2 are turned on, and the latch structure resumes the latched state.

7. The hybrid 14T-SRAM cell with a schmitt structure of claim 1, wherein the operating logic to implement the data read is as follows:

Firstly, setting a write word line WL and write bit lines BL and BLB to be low level, and connecting a read bit line RBL with a capacitor with an initial potential of VDD; then, the read word line RWL is set to a high level; at this time, if the level of the read bit line RBL is lowered, the read result is data "0"; if the read bit line RBL remains high, the read result is a data "1".

8. An SRAM circuit comprises a memory array and a peripheral circuit which is matched with the memory array to realize the functions of data reading, writing and maintaining; the memory array is formed by arranging the mixed 14T-SRAM cells with the Schmidt structures according to any one of claims 1-7 in an array mode; in the memory array, all memory cells in the same column share write assist transistors P1 and P2, and all memory cells in the same column share cell transfer transistor N1.

9. The SRAM circuit of claim 8, wherein: in the memory array, each memory cell of each row is connected to the same write word line WL and read word line RWL; the individual memory cells of each column are connected to the same set of write bit lines BL and BLB, and read bit line RBL.

10. A memory chip, characterized in that: packaged with an SRAM circuit as claimed in claim 8 or 9.