CN118278329B - Method, electronic device and medium for optimizing trigger size in gate-level netlist - Google Patents
Method, electronic device and medium for optimizing trigger size in gate-level netlist Download PDFInfo
- Publication number
- CN118278329B CN118278329B CN202410704296.9A CN202410704296A CN118278329B CN 118278329 B CN118278329 B CN 118278329B CN 202410704296 A CN202410704296 A CN 202410704296A CN 118278329 B CN118278329 B CN 118278329B
- Authority
- CN
- China
- Prior art keywords
- gate
- level netlist
- buffer
- size
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 230000008569 process Effects 0.000 claims abstract description 25
- 238000005457 optimization Methods 0.000 claims abstract description 18
- 238000013507 mapping Methods 0.000 claims abstract description 6
- 239000000872 buffer Substances 0.000 claims description 47
- 230000007704 transition Effects 0.000 claims description 13
- 230000006870 function Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000003786 synthesis reaction Methods 0.000 description 12
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to the technical field of chips, in particular to a method, electronic equipment and medium for optimizing the size of a trigger in a gate-level netlist, wherein the method comprises the following steps: step S1, compiling and mapping a chip design code, and generating a mapped gate-level netlist based on a standard cell library of a preset process; s2, obtaining standard units { F 1,F2,…,Fn,…,FN } corresponding to all triggers from the mapped gate-level netlist; step S3, replacing (F n,Bn) the combined structure of each F n in the mapped gate-level netlist to generate a replaced gate-level netlist; and S4, performing logic optimization on the replaced gate-level netlist, and adjusting the B n based on the load size corresponding to the F n to generate a gate-level netlist after logic optimization. The invention reduces the chip area and the chip power consumption and improves the chip performance.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method, an electronic device, and a medium for optimizing a size of a trigger in a gate level netlist.
Background
In chip design, there are a large number of Flip-flops (Flip-Flop), one Flip-Flop is usually connected to a combinational logic circuit, and one Flip-Flop is connected after the combinational logic circuit is connected. The trigger is also connected with a clock signal for clock synchronization. In generating the gate level netlist, the synthesis tool typically generates trigger standard cells of corresponding sizes in the gate level netlist based on the load size of the combinational circuit to which each trigger is connected, for implementing the data storage function and the function of driving the load to which the trigger is connected. However, the flip-flop is good at storing data, but not driving a load, and the flip-flop itself contains more transistors and requires a larger area. In the prior art, the size of the flip-flops in the synthesized netlist is usually increased directly according to the load of the flip-flop connection, so that the size of the flip-flops is increased. The larger the standard cell size of the trigger, the larger the area required to be occupied, the larger the corresponding power consumption, and the worse the chip performance. In the layout and wiring stage, the larger the standard cell size of the flip-flop is, the larger a Buffer (Buffer) for driving the flip-flop is generated for connecting clock signals is, so that the larger the occupied area of the generated clock tree is, the larger the power consumption is, and the worse the chip performance is. Therefore, how to optimize the flip-flops in the gate-level netlist, reduce the chip area and the chip power consumption, and improve the chip performance becomes a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a method, electronic equipment and medium for optimizing the size of a trigger in a gate-level netlist, which reduces the chip area and the chip power consumption and improves the chip performance.
According to a first aspect of the present invention, there is provided a method of optimizing the size of a flip-flop in a gate level netlist, comprising:
Step S1, compiling and mapping a chip design code, and generating a mapped gate-level netlist based on a standard cell library of a preset process;
s2, obtaining standard units { F 1,F2,…,Fn,…,FN},Fn corresponding to all the triggers from the mapped gate-level netlist, wherein the standard units { F 1,F2,…,Fn,…,FN},Fn are standard units corresponding to the nth trigger, the value range of N is 1 to N, and N is the total number of the triggers in chip design;
Step S3, replacing (F n,Bn) a combined structure of each F n in the mapped gate-level netlist to generate a replaced gate-level netlist, wherein F n is a replacement trigger corresponding to F n and is used for realizing a storage function corresponding to F n, B n is a replacement buffer corresponding to F n and is used for realizing a driving function corresponding to F n, all F n are set as a minimum-sized trigger in a standard cell library of a preset process, all B n are initially set as a buffer of a preset size, and B n is set to be only capable of adjusting size attributes;
And S4, performing logic optimization on the replaced gate-level netlist, and adjusting the B n based on the load size corresponding to the F n to generate a gate-level netlist after logic optimization.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the method, the electronic equipment and the medium for optimizing the size of the trigger in the gate-level netlist can achieve quite technical progress and practicality, and have wide industrial utilization value, and the method and the medium have at least the following beneficial effects:
According to the invention, all the triggers in the gate-level netlist are replaced by the structure of combining the minimum-size triggers with the buffer, so that the area required by the triggers is greatly reduced on the premise of meeting the storage and driving requirements of the triggers, the power consumption of the triggers is reduced, the chip area and the chip power consumption are further reduced, and the chip performance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for optimizing the size of a trigger in a gate level netlist according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a method for optimizing the size of a trigger in a gate-level netlist, which is shown in fig. 1 and comprises the following steps:
s1, compiling and mapping a chip design code, and generating a mapped gate-level netlist based on a standard cell library of a preset process.
The chip design code may be Verilog code. Step S1 may be implemented by a logic synthesis tool. Different chip designs may use standard cell libraries for different processes. Standard cells with different sizes corresponding to different components are included in a standard cell library of a preset process.
And S2, acquiring standard units { F 1,F2,…,Fn,…,FN},Fn corresponding to all the triggers from the mapped gate-level netlist, wherein the standard units { F 1,F2,…,Fn,…,FN},Fn are standard units corresponding to the nth trigger, the value range of N is 1 to N, and N is the total number of the triggers in chip design.
It should be noted that, in general, the flip-flop includes ten or more transistors, and the more transistors, the larger the area, and the larger the increase in the entire area of the chip as the size increases. The size of the logic synthesis tool to select standard cells for a trigger is typically determined based on the load size of the subsequent connections of the trigger. However, the flip-flop is mainly used for realizing a memory function, and has weak driving capability, and if the driving capability is improved by increasing the size of the flip-flop, the chip area can be greatly increased, and the chip power consumption can be reduced. The buffer has stronger driving capability relative to the flip-flop, and the buffer only comprises a plurality of transistors, and the Area is smaller relative to the flip-flop, so that the flip-flop mapped by the logic synthesis tool is replaced by the structure of combining the flip-flop with the minimum size and the buffer, thereby reducing the chip Area (Area), reducing the chip Power consumption (Power), and improving the chip Performance (Performance), namely integrally improving the PPA of the chip.
Step S3, replacing (F n,Bn) the combined structure of each F n in the mapped gate-level netlist to generate a replaced gate-level netlist, where F n is a replacement trigger corresponding to F n, for implementing a storage function corresponding to F n, B n is a replacement buffer corresponding to F n, for implementing a driving function corresponding to F n, all F n are set as minimum-sized triggers in a standard cell library of a preset process, all B n are initially set as buffers of a preset Size, and B n is set as a Size-adjustable Only attribute (Size Only).
It should be noted that the minimum size of flip-flop F n is sufficient to implement the required storage function for each F n. The buffer has stronger driving capability than the flip-flop and has a smaller area than the flip-flop. Therefore, the combined structure of F n and F n,Bn can greatly reduce the area required by the trigger and reduce the power consumption of the trigger on the basis of ensuring the storage function and the driving capability corresponding to F n. Thereby reducing the chip area and the chip power consumption and improving the chip performance. In addition, since the load corresponding to each F n may be different, the final replacement B n may also be different, so all B n are initially set to the buffer with the preset size, and the size attribute is set to B n only to be adjustable, and then B n is further adjusted by the logic synthesis tool.
It should be noted that if only the size attribute is able to be adjusted without setting B n, then in the subsequent logic optimization process, the logic synthesis tool may optimize B n and return to adjust the size of f n. After setting the size attribute for B n, the correct optimization direction can be set for the subsequent logic optimization, and the optimization tool does not optimize B n, but matches the driving force required by the load corresponding to F n by adjusting the size of B n.
As an embodiment, the buffer with a preset size is a minimum size buffer in a standard cell library of a preset process. It will be appreciated that other sizes of buffers may be selected as B n, depending on the particular chip design requirements.
And S4, performing logic optimization on the replaced gate-level netlist, and adjusting the B n based on the load size corresponding to the F n to generate a gate-level netlist after logic optimization.
It should be noted that, in the process of performing logic optimization on the replaced gate-level netlist, the logic synthesis tool may adjust B n based on the load size corresponding to F n, may only adjust the size of B n, and may replace B n with a buffer tree. The buffer tree generated on the chip Data Path (Data Path) can be optimized by setting the size attribute B n, so that the area and the power consumption on the chip Data Path are reduced, the chip performance is improved, and the PPA of the chip is integrally improved. As an embodiment, the step S1 includes:
and S11, acquiring a chip design code, compiling the chip design code, and generating a gate-level circuit structure.
The chip design codes are input into a logic synthesis tool, the logic synthesis tool compiles the chip design codes first, and the chip design codes are converted into a circuit structure composed of gate-level components, wherein the gate-level components are not standard units.
And step S12, mapping the components in the gate-level circuit structure to a standard cell library of a preset process, and generating a mapped gate-level netlist.
Different chip designs may be provided with standard cell libraries of different preset technologies, each standard cell is also provided with different sizes, and the logic synthesis tool maps each component in the gate level circuit structure into a standard cell of a corresponding size according to a specific circuit structure. At this stage, the flip-flops are mapped into flip-flop standard cells of different sizes, and the larger the size mapped by the flip-flops, the larger the occupied area and the larger the corresponding power consumption.
As an embodiment, in the step S4, the adjusting B n based on the load size corresponding to F n includes:
step S41, judging whether the current B n meets the maximum fan-out number (Max Fanout), the maximum Capacitance (Max Capacitance) and the maximum Transition time (Max Transition) all match the load driving requirements corresponding to F n, if yes, finishing the adjustment of B n, otherwise, executing step S42.
The maximum transition time may also be referred to as a maximum transition time, and a specific value is that there is a transition from 0 to 1 in a signal, and the corresponding ramp-up time is the maximum transition time.
Step S42, judging whether a buffer which is not traversed exists in a standard cell library of a preset process, if so, executing step S43, otherwise, executing step S44.
Step S43, updating B n to a standard cell library of a preset process, selecting an unremoved buffer, and returning to the step S41.
Step S44, constructing a buffer tree based on a standard cell library of a preset process, and updating B n into the buffer tree, wherein the buffer tree meets the load driving requirement corresponding to F n and the maximum fan-out number, the maximum capacitance and the maximum transition time are all matched.
It should be noted that in step S41-step S44, it is first determined whether a buffer exists to meet the requirement by adjusting the size, if not, a buffer tree is constructed, and the logic synthesis tool sets parameters such as the specific size and the number of stages of the buffer included in the buffer tree according to the specific requirement of the chip design, so that the buffer tree finally meets the maximum fan-out number, the maximum capacitance and the maximum transition time all match the load driving requirement corresponding to F n. The logic synthesis tool may specifically determine or adjust B n by repairing design rule violations (Design Rule Violation, abbreviated as DRV) so that the final B n meets the load driving requirements corresponding to F n for the maximum fan-out number, the maximum capacitance, and the maximum transition time.
After F n is substituted for the combined structure of (F n,Bn), the self-static power consumption and dynamic power consumption corresponding to F n are greatly reduced compared with the non-minimum-sized flip-flops. In addition, in the subsequent physical layout and wiring stage, the area of the constructed clock tree is further reduced due to the reduction of the size of the trigger, so that the area of a chip is further reduced, the power consumption of the chip is reduced, and the performance of the chip is improved. As an embodiment, the step S4 includes:
In the step S5, in the physical layout and routing stage, one end of the clock driving buffer unit M n,Mn corresponding to each f n generated in the gate-level netlist after logic optimization is connected to a clock signal, and the other end of the clock driving buffer unit M n,Mn is connected to f n,Mn, and includes g (n) cascaded clock driving buffers, where g (n) is the number of cascaded clock driving buffers corresponding to f n.
And S6, generating a Clock Tree (Clock Tree) corresponding to the chip design based on all M n.
It should be noted that the size of the clock driving buffer unit corresponding to the flip-flop is proportional to the size of the buffer, since all flip-flops have been replaced with the flip-flop of the smallest size. The load of the clock tree is all the triggers, and the duty ratio in the whole chip is very large. After the size of the trigger is reduced, the load of the clock tree is also greatly reduced, so that the overall size of the clock tree generated in the physical layout and wiring stage is reduced, thereby reducing static power consumption and dynamic power consumption and reducing the area. In addition, the number of stages of the generated clock tree is reduced, so that the delay of clock signals is reduced, and the performance of the chip is improved.
In the physical layout stage, B n may be further optimized, and as an embodiment, the step S4 further includes:
And S7, in the physical layout and wiring stage, physical layout and wiring optimization is carried out on the B n, and the optimized B n meets the load driving requirement corresponding to F n, wherein the maximum fan-out number, the maximum capacitance and the maximum transition time are all matched.
The physical layout and wiring optimization is further carried out on the B n, so that the chip area and the power consumption can be further reduced, and the chip performance is improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, all the triggers in the gate-level netlist are replaced by the structure of combining the minimum-size triggers with the buffer, so that the area required by the triggers is greatly reduced on the premise of meeting the storage and driving requirements of the triggers, the power consumption of the triggers is reduced, the chip area and the chip power consumption are further reduced, and the chip performance is improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (7)
1. A method for optimizing trigger size in a gate-level netlist, comprising:
Step S1, compiling and mapping a chip design code, and generating a mapped gate-level netlist based on a standard cell library of a preset process;
s2, obtaining standard units { F 1,F2,…,Fn,…,FN},Fn corresponding to all the triggers from the mapped gate-level netlist, wherein the standard units { F 1,F2,…,Fn,…,FN},Fn are standard units corresponding to the nth trigger, the value range of N is 1 to N, and N is the total number of the triggers in chip design;
Step S3, replacing (F n,Bn) a combined structure of each F n in the mapped gate-level netlist to generate a replaced gate-level netlist, wherein F n is a replacement trigger corresponding to F n and is used for realizing a storage function corresponding to F n, B n is a replacement buffer corresponding to F n and is used for realizing a driving function corresponding to F n, all F n are set as a minimum-sized trigger in a standard cell library of a preset process, all B n are initially set as a buffer of a preset size, and B n is set to be only capable of adjusting size attributes;
S4, performing logic optimization on the replaced gate-level netlist, and adjusting the B n based on the load size corresponding to the F n to generate a gate-level netlist after logic optimization;
In the step S4, adjusting B n based on the load size corresponding to F n includes:
Step S41, judging whether the current B n meets the maximum fan-out number, the maximum capacitance and the maximum transition time which are matched with the load driving requirements corresponding to F n, if so, finishing the adjustment of B n, otherwise, executing step S42;
Step S42, judging whether a buffer which is not traversed exists in a standard cell library of a preset process, if so, executing step S43, otherwise, executing step S44;
Step S43, updating the B n into a standard cell library of a preset process, selecting an unremoved buffer, and returning to the step S41;
Step S44, constructing a buffer tree based on a standard cell library of a preset process, and updating B n into the buffer tree, wherein the buffer tree meets the load driving requirement corresponding to F n and the maximum fan-out number, the maximum capacitance and the maximum transition time are all matched.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The step S1 includes:
S11, acquiring a chip design code, compiling the chip design code, and generating a gate-level circuit structure;
And step S12, mapping the components in the gate-level circuit structure to a standard cell library of a preset process, and generating a mapped gate-level netlist.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The step S4 includes:
Step S5, in the physical layout and wiring stage, one end of a clock driving buffer unit M n,Mn corresponding to each f n generated in the gate-level netlist after logic optimization is connected with a clock signal, the other end of the clock driving buffer unit M n,Mn is connected with f n,Mn and comprises g (n) cascaded clock driving buffers, and g (n) is the number of cascaded clock driving buffers corresponding to f n;
And S6, generating a clock tree corresponding to the chip design based on all M n.
4. The method of claim 3, wherein the step of,
The step S4 further includes:
And S7, in the physical layout and wiring stage, physical layout and wiring optimization is carried out on the B n, and the optimized B n meets the load driving requirement corresponding to F n, wherein the maximum fan-out number, the maximum capacitance and the maximum transition time are all matched.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The buffer with the preset size is the smallest size buffer in a standard cell library of the preset process.
6. An electronic device, comprising:
at least one processor;
And a memory communicatively coupled to the at least one processor;
Wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-5.
7. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410704296.9A CN118278329B (en) | 2024-06-03 | 2024-06-03 | Method, electronic device and medium for optimizing trigger size in gate-level netlist |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410704296.9A CN118278329B (en) | 2024-06-03 | 2024-06-03 | Method, electronic device and medium for optimizing trigger size in gate-level netlist |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118278329A CN118278329A (en) | 2024-07-02 |
| CN118278329B true CN118278329B (en) | 2024-08-02 |
Family
ID=91649716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410704296.9A Active CN118278329B (en) | 2024-06-03 | 2024-06-03 | Method, electronic device and medium for optimizing trigger size in gate-level netlist |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118278329B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102217323A (en) * | 2008-11-06 | 2011-10-12 | 艾科星科技公司 | Systems and methods for setting timers via an interactive trigger |
| CN102279899A (en) * | 2011-04-01 | 2011-12-14 | 中国科学院微电子研究所 | Method for optimizing simplified standard cell library |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8471597B2 (en) * | 2008-05-27 | 2013-06-25 | Qualcomm Incorporated | Power saving circuit using a clock buffer and multiple flip-flops |
| CN102831273B (en) * | 2012-08-30 | 2015-02-04 | 锐迪科科技有限公司 | Design method of digital integrated circuit comprising double-edge trigger |
| CN104852739B (en) * | 2015-05-12 | 2018-01-05 | 西安交通大学 | A kind of precision restructural delay line analog-digital converter circuit for digital power |
| CN114492265B (en) * | 2022-04-02 | 2022-06-28 | 奇捷科技(深圳)有限公司 | Method, equipment and storage medium for determining chip testable design |
| CN114936536A (en) * | 2022-05-17 | 2022-08-23 | 比科奇微电子(杭州)有限公司 | Trigger merging method, device, equipment, medium and program product applied to chip design |
-
2024
- 2024-06-03 CN CN202410704296.9A patent/CN118278329B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102217323A (en) * | 2008-11-06 | 2011-10-12 | 艾科星科技公司 | Systems and methods for setting timers via an interactive trigger |
| CN102279899A (en) * | 2011-04-01 | 2011-12-14 | 中国科学院微电子研究所 | Method for optimizing simplified standard cell library |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118278329A (en) | 2024-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8365115B2 (en) | System and method for performance modeling of integrated circuits | |
| CN101187957B (en) | System and method for designing multiple latch unit layout of integrated circuit public clock domain clock aware placement | |
| KR100249251B1 (en) | Logic circuit optimization apparatus and its method | |
| CN102160054B (en) | System and method for designing integrated circuits that employ adaptive voltage scaling optimization | |
| JP2001256271A (en) | Method and device for analyzing unwanted radiation | |
| US8302041B1 (en) | Implementation flow for electronic circuit designs using choice networks | |
| US8291364B2 (en) | Automated digital circuit design tool that reduces or eliminates adverse timing constraints do to an inherent clock signal skew, and applications thereof | |
| US7689964B2 (en) | System and method for routing connections | |
| US11030383B2 (en) | Integrated device and method of forming the same | |
| US20080216043A1 (en) | Structure for Optimizing the Signal Time Behavior of an Electronic Circuit Design | |
| US6609241B2 (en) | Method of designing clock wiring | |
| US11003821B1 (en) | Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits | |
| JP2001357090A (en) | Method and device for synthesizing logic | |
| US20080104552A1 (en) | Power consumption optimizing method for semiconductor integrated circuit and semiconductor designing apparatus | |
| CN118278329B (en) | Method, electronic device and medium for optimizing trigger size in gate-level netlist | |
| US20050251776A1 (en) | Integrated circuit design system | |
| US12079558B2 (en) | On-the-fly multi-bit flip flop generation | |
| JP2009042905A (en) | Noise analyzing method for integrated circuit device, noise analyzing system for integrated circuit device, integrated circuit device, electronic equipment, noise analysis program for integrated circuit device, and information storage medium | |
| US20150269304A1 (en) | System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce total power within a circuit design | |
| US20220171912A1 (en) | Poly-bit cells | |
| US7360193B1 (en) | Method for circuit block placement and circuit block arrangement based on switching activity | |
| CN117933156B (en) | Gate-level netlist-based burr power consumption optimization method, electronic equipment and medium | |
| CN114662446A (en) | Wiring optimization method for reducing dynamic power consumption | |
| JP4855283B2 (en) | Semiconductor integrated circuit design equipment | |
| JP2008123458A (en) | Method for designing semiconductor integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |