CN118263328B - Lateral double diffused field effect transistor, manufacturing method, chip and circuit - Google Patents

Abstract

The invention provides a transverse double-diffusion field effect transistor, a manufacturing method, a chip and a circuit, and relates to the technical field of semiconductors. The transistor includes: the initial substrate, the first well region, the body region, the drift region, the source electrode, the drain electrode and the grid electrode, and the lateral double-diffusion field effect transistor further comprises: the oxidation medium region is formed in the drift region and is covered by polysilicon extending out of the grid electrode, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together; wherein the oxidation medium region is manufactured by a shallow trench isolation process; the oxidation isolation region is in a strip-shaped structure, is formed at the junction of the body region and the drift region, and extends downwards to the first well region from the middle region at the junction of the body region and the drift region. The transistor provided by the invention can avoid breakdown inside the device, improve the breakdown voltage of the transverse double-diffusion field effect transistor and enhance the reliability of the transistor in high-voltage application.

Description

Lateral double diffused field effect transistor, manufacturing method, chip and circuit

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a lateral double diffused field effect transistor, a lateral double diffused field effect transistor, a chip and a circuit.

Background Art

Lateral Double-Diffused MOSFET (LDMOS) is a lateral power device with electrodes located on the device surface. It is easy to achieve monolithic integration with low-voltage signal circuits and other devices through internal connections. It also has the advantages of high voltage resistance, high gain, good linearity, high efficiency, and good broadband matching performance. It has been widely used in power integrated circuits, especially low-power and high-frequency circuits.

In the prior art, in order to increase the breakdown voltage, a field plate is usually made by growing a layer of oxide on the substrate surface using a thermal oxidation process to reduce the surface electric field. However, this can only prevent surface breakdown, and breakdown will still occur deep from the substrate surface, so the breakdown voltage of the device is high.

Summary of the invention

In view of the technical problems in the prior art that devices are prone to breakdown and have high breakdown voltage, the present invention provides a lateral double diffused field effect transistor, a method for manufacturing a lateral double diffused field effect transistor, a chip and a circuit. The use of the lateral double diffused field effect transistor can avoid breakdown inside the device, improve the breakdown voltage of the lateral double diffused field effect transistor, and enhance the reliability of the transistor in high voltage applications.

To achieve the above-mentioned purpose, the first aspect of the present invention provides a lateral double diffused field effect transistor, comprising: an initial substrate, a first well region, a body region, a drift region, a source, a drain, and a gate, wherein the lateral double diffused field effect transistor also comprises: an oxidation medium region, formed in the drift region and covered by polysilicon extending from the gate, the oxidation medium region and the polysilicon covering the oxidation medium region together serve as a field plate; wherein the oxidation medium region is made by a shallow trench isolation process; an oxidation isolation region, wherein the oxidation isolation region is a strip-shaped configuration, formed at the junction of the body region and the drift region, and extending downward from the middle area at the junction of the body region and the drift region to the first well region.

Furthermore, the oxide isolation region extends to a middle area of the first well region.

Furthermore, the body region has ion doping of the first conductivity type; the lateral double diffused field effect transistor also includes: a second well region formed on a side of the initial substrate away from the body region, the second well region has ion doping of the first conductivity type.

Furthermore, the lateral double diffused field effect transistor also includes: a first guard ring, formed in the body region and close to the source, with heavy ion doping of the first conductivity type; a second guard ring, formed in the first well region close to the drift region side, with heavy ion doping of the second conductivity type; wherein the second conductivity type is different from the first conductivity type ion doping type; a third guard ring, formed in the second well region, with heavy ion doping of the first conductivity type.

Furthermore, the lateral double diffused field effect transistor further includes: a first shallow trench isolation formed between the drain and the second guard ring.

Furthermore, the lateral double diffused field effect transistor further includes: a second shallow trench isolation formed between the second guard ring and the third guard ring; and a polysilicon protection structure formed on a surface of the second shallow trench isolation.

Furthermore, the lateral double diffused field effect transistor further includes: an oxidation isolation structure formed on a side of the initial substrate close to the first well region and extending downward from the bottom of the second shallow trench isolation to below the first well region.

Furthermore, the oxidation isolation structure includes a plurality of strip-shaped oxidation isolation strips spaced apart from each other.

The second aspect of the present invention provides a method for manufacturing a lateral double diffused field effect transistor, which comprises: forming an initial substrate, and forming an oxidation isolation region in the initial substrate, wherein the oxidation isolation region is a strip-shaped configuration, formed at the junction of a defined body region and a defined drift region, and extending downward from the middle area at the junction of the defined body region and the defined drift region to the defined first well region; forming a first well region, a body region and a drift region by an ion implantation process; forming an oxidation medium region in the drift region by a shallow trench isolation process; forming a gate by a thermal oxidation process and a vapor deposition process; wherein the polysilicon of the gate extends toward the drift region to cover the oxidation medium region, and the oxidation medium region and the polysilicon covering the oxidation medium region together serve as a field plate; and forming a source and a drain by an ion implantation process.

Furthermore, the forming of the initial substrate and the forming of the oxidation isolation region in the initial substrate include: providing an original substrate and forming an oxidation isolation region groove in the original substrate through an etching process; filling the oxidation isolation region groove using a chemical vapor deposition process to form the oxidation isolation region; bonding a layer of external substrate on the surface of the original substrate, and using the original substrate and the external substrate as the initial substrate.

Furthermore, the body region is doped with ions of a first conductivity type; the method further comprises: using an ion implantation process to form a second well region doped with ions of the first conductivity type on a side of the initial substrate away from the body region.

Furthermore, the method also includes: using an ion implantation process to form a first guard ring heavily doped with ions of the first conductivity type in the body region and close to the source; using an ion implantation process to form a second guard ring heavily doped with ions of the second conductivity type in the first well region close to the drift region; wherein the second conductivity type is different from the first conductivity type in ion doping type; and using an ion implantation process to form a third guard ring heavily doped with ions of the first conductivity type in the second well region.

Furthermore, the method further includes: forming a first shallow trench isolation between the drain and the second guard ring.

Furthermore, the method further includes: forming a second shallow trench isolation between the second protection ring and the third protection ring while forming the first shallow trench isolation; and forming a polysilicon protection structure on a surface of the second shallow trench isolation.

Furthermore, the method also includes: forming an oxidation isolation structure while forming the oxidation isolation region; wherein the oxidation isolation structure is formed on a side of the initial substrate close to the first well region and extends downward from the bottom of the second shallow trench isolation to below the first well region.

A third aspect of the present invention provides a chip, which includes the lateral double diffused field effect transistor described above.

A fourth aspect of the present invention provides a circuit comprising the lateral double diffused field effect transistor described above.

Through the technical solution provided by the present invention, the present invention has at least the following technical effects:

The lateral double diffused field effect transistor of the present invention comprises: an initial substrate, a first well region, a body region, a drift region, a source, a drain, and a gate. An oxidized medium region is formed in the drift region by a shallow trench isolation process, and the oxidized medium region is covered by polysilicon extending from the gate. The oxidized medium region and the polysilicon covering the oxidized medium region serve together as a field plate. The oxidized medium region is formed in the substrate, and can disperse the electric field between the surface and the middle region of the transistor to prevent the breakdown of the surface and the middle region of the device. An oxidized isolation region is formed at the junction of the body region and the drift region, and the oxidized isolation region is a strip-shaped configuration, extending downward from the middle region at the junction of the body region and the drift region to the first well region. It can avoid the movement of electron-hole pairs at the junction of the body region and the drift region inside the device, alleviate the sharp rise of current, and avoid breakdown. Through the lateral double diffused field effect transistor provided by the present invention, it is possible to avoid breakdown inside the device, improve the breakdown voltage of the lateral double diffused field effect transistor, and enhance the reliability of the transistor in high voltage applications.

Other features and advantages of the present invention will be described in detail in the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

FIG1 is a schematic structural diagram of an original substrate formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

2 is a schematic structural diagram of the trenches of the oxidation isolation region and the trenches of the oxidation isolation structure formed in the method for manufacturing a lateral double diffused field effect transistor provided by an embodiment of the present invention;

3 is a schematic structural diagram of an oxide isolation region and an oxide isolation structure formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

4 is a schematic structural diagram of an initial substrate formed in a method for manufacturing a lateral double diffused field effect transistor provided by an embodiment of the present invention;

5 is a schematic structural diagram of a first well region, a second well region, a body region and a drift region formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

6 is a schematic structural diagram of an oxidized dielectric region, a first shallow trench isolation, and a second shallow trench isolation formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

7 is a schematic structural diagram of a gate, a field plate and a polysilicon protection structure formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

8 is a schematic structural diagram of a lateral double diffused field effect transistor formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

9 is a schematic structural diagram of a lateral double diffused field effect transistor formed in a method for manufacturing a lateral double diffused field effect transistor provided in an embodiment of the present invention;

FIG. 10 is a flow chart of a method for manufacturing a lateral double diffused field effect transistor according to an embodiment of the present invention.

Description of Reference Numerals

1-original substrate; 2-oxidation isolation region; 3-oxidation isolation structure; 4-first well region; 5-drift region; 6-body region; 7-second well region; 8-oxidation dielectric region; 9-first shallow trench isolation; 10-second shallow trench isolation; 11-gate; 12-polysilicon protection structure; 13-first protection ring; 14-third protection ring; 15-source; 16-drain; 17-second protection ring.

DETAILED DESCRIPTION

The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

In the present invention, unless otherwise specified, directional words such as "up, down, top, bottom" are usually used with reference to the directions shown in the drawings or are used to describe the relative positional relationships of components in the vertical, perpendicular or gravity direction.

The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

Please refer to Figure 8. The first aspect of an embodiment of the present invention provides a lateral double diffused field effect transistor, which includes: an initial substrate, a first well region 4, a body region 6, a drift region 5, a source 15, a drain 16, and a gate 11. The lateral double diffused field effect transistor also includes: an oxidation medium region 8, which is formed in the drift region 5 and is covered by polysilicon extending from the gate 11, and the oxidation medium region 8 and the polysilicon covering the oxidation medium region 8 together serve as a field plate; wherein the oxidation medium region 8 is made by a shallow trench isolation process; an oxidation isolation region 2, which is a strip-shaped configuration, formed at the junction of the body region 6 and the drift region 5, and extends downward from the middle area at the junction of the body region 6 and the drift region 5 to the first well region 4.

Specifically, in the embodiment of the present invention, the lateral double diffused field effect transistor includes: an initial substrate, a body region 6 and a drift region 5 are adjacently formed in the first well region 4, a source 15 is formed in the body region 6, a drain 16 is formed in the drift region 5, and a gate 11 is formed on the surface of the body region 6. The oxidizing medium region 8 is formed in the drift region 5 by shallow trench isolation technology, and the polysilicon extending from the gate 11 covers the surface of the oxidizing medium region 8, and the oxidizing medium region 8 and the polysilicon covering it form a field plate structure. The oxidizing medium region 8 is formed in the initial substrate, which can reduce the electric field on the surface of the transistor and prevent the breakdown of the device surface.

An oxidation isolation region 2 is formed at the junction of the body region 6 and the drift region 5. The oxidation isolation region 2 extends downward from the middle area at the junction of the body region 6 and the drift region 5 to the first well region 4, and the oxidation isolation region 2 is a strip configuration. Since the body region 6 and the drift region 5 are doped with different types, when the voltage applied to the device reaches a certain level, the electrons and holes in the body region 6 and the drift region 5 obtain sufficient energy under the action of the electric field, collide with the atoms in the semiconductor, and generate more electron-hole pairs. These electron-hole pairs continue to move under the action of the electric field, further collide with the atoms, form a chain reaction, and cause a sharp rise in current and breakdown. The oxidation isolation region 2 can prevent the movement of electron-hole pairs at the junction of the body region 6 and the drift region 5 inside the initial substrate, alleviate the sharp rise in current, and avoid breakdown. In addition, the breakdown voltage of the oxidation isolation region 2 is high, and its breakdown electric field strength is 10MV/cm, which will not cause avalanche breakdown.

The lateral double diffused field effect transistor provided by the present invention can avoid breakdown inside the device, improve the breakdown voltage of the lateral double diffused field effect transistor, and enhance the reliability of the transistor in high voltage applications.

Furthermore, the lateral width of the oxide isolation region 2 is between 0.5 and 1.5 microns. If the lateral width is too large, the lateral width of the transistor will be increased, which will in turn increase the area of the transistor, increase the power consumption of the device, and increase the heat generation, reduce the switching speed, and affect the integration of the device; if the lateral width is too thin, the breakdown voltage will be reduced.

Furthermore, the oxide isolation region 2 extends to the middle region of the first well region 4. Since the first well region 4 needs an external voltage, the oxide isolation region 2 extending to the middle region of the first well region 4 will not isolate the first well region 4. The first well region 4 on the left can be connected to an external voltage together with the first well region 4 on the right through the second guard ring 17. Therefore, the first well region 4 on the left does not need to be connected to an external voltage separately, which simplifies the manufacturing steps of the transistor, reduces the manufacturing cost, and improves the manufacturing efficiency.

Furthermore, the body region 6 has ion doping of the first conductivity type; the lateral double diffused field effect transistor also includes: a second well region 7 formed on a side of the initial substrate away from the body region 6, and the second well region 7 has ion doping of the first conductivity type.

Specifically, in the embodiment of the present invention, a second well region 7 is formed on a side of the initial substrate away from the body region 6, and the second well region 7 is doped with ions of the first conductivity type like the body region 6. The second well region 7 can improve the voltage resistance of the device, and when the transistor is affected by an external voltage, the second well region 7 can effectively prevent the voltage from further increasing, thereby protecting the transistor from damage.

Furthermore, the lateral double diffused field effect transistor also includes: a first guard ring 13, formed in the body region 6 and close to the source 15, with heavy ion doping of the first conductivity type; a second guard ring 17, formed in the first well region 4 on the side close to the drift region 5, with heavy ion doping of the second conductivity type; wherein the second conductivity type is different from the first conductivity type ion doping type; a third guard ring 14, formed in the second well region 7, with heavy ion doping of the first conductivity type.

Specifically, in the embodiment of the present invention, a guard ring is also formed in the lateral double diffused field effect transistor, and the first guard ring 13 is formed in the body region 6 and is arranged close to the source 15, and has a first conductive type ion heavy doping. The first guard ring 13 can provide voltage protection for the lateral double diffused field effect transistor. At the same time, it can also absorb carriers that flow from the drift region 5 into the body region 6 when the field effect transistor is turned on, reduce the aggregation of carriers in the body region 6, avoid the conduction of the parasitic triode in the lateral double diffused field effect transistor, and improve the breakdown voltage of the lateral double diffused field effect transistor.

A second guard ring 17 is formed on the side of the first well region 4 close to the drift region 5, and the second guard ring 17 is heavily doped with the second conductive type ions. A third guard ring 14 heavily doped with the first conductive type ions is formed in the second well region 7. The second guard ring 17 and the third guard ring 14 can be connected to an external voltage to perform voltage protection on the lateral double diffused field effect transistor.

Furthermore, the lateral double diffused field effect transistor further comprises: a first shallow trench isolation 9 formed between the drain 16 and the second guard ring 17. The first shallow trench isolation 9 is used for isolation.

Furthermore, the lateral double diffused field effect transistor further includes: a second shallow trench isolation 10 formed between the second guard ring 17 and the third guard ring 14 ; and a polysilicon protection structure 12 formed on the surface of the second shallow trench isolation 10 .

Specifically, in the embodiment of the present invention, the second guard ring 17 is heavily doped with the second conductivity type, and the third guard ring 14 is heavily doped with the first conductivity type. When the voltage applied to the second guard ring 17 and the third guard ring 14 is too high, the second guard ring 17 and the third guard ring 14 will be broken down. In order to avoid breakdown, a second shallow trench isolation 10 is formed between the second guard ring 17 and the third guard ring 14 to isolate the second guard ring 17 and the third guard ring 14, and a polysilicon protection structure 12 is formed on the surface of the second shallow trench isolation 10. The second shallow trench isolation 10 and the polysilicon protection structure 12 can disperse the surface electric field of the transistor at that location to prevent breakdown between the second guard ring 17 and the third guard ring 14. The transistor can withstand higher voltages without dielectric breakdown, which enhances the reliability of the transistor in high voltage applications.

The lateral double diffused field effect transistor provided by the present invention can prevent breakdown between the second guard ring 17 and the third guard ring 14, thereby increasing the breakdown voltage of the device and enhancing the reliability of the transistor in high voltage applications.

Furthermore, the lateral double diffused field effect transistor further includes: an oxidation isolation structure 3 formed on a side of the initial substrate close to the first well region 4 and extending downward from the bottom of the second shallow trench isolation 10 to below the first well region 4 .

Specifically, in the embodiment of the present invention, the first well region 4 and the initial substrate have different conductivity types and can form a PN junction. When the voltage applied to the first well region 4 and the initial substrate reaches a certain level, the electrons and holes in the first well region 4 and the initial substrate obtain sufficient energy under the action of the electric field, collide with atoms in the semiconductor, and generate more electron-hole pairs. These electron-hole pairs continue to move under the action of the electric field, further collide with atoms, form a chain reaction, and cause the current to rise sharply and breakdown to occur. Although the second shallow trench isolation 10 and the polysilicon protection structure 12 can reduce the electric field on the surface of the initial substrate and prevent surface breakdown, breakdown still occurs inside the initial substrate. In order to avoid breakdown between the inside of the initial substrate and the first well region 4, an oxidation isolation structure 3 is formed between the first well region 4 and the second well region 7, and the initial substrate is close to the drift region 5. The oxidation isolation structure 3 does not contact the second shallow trench isolation 10, and the oxidation isolation structure 3 extends downward from the bottom of the second shallow trench isolation 10 to below the first well region 4. The oxidation isolation structure 3 can prevent the movement of electron-hole pairs between the first well region 4 and the initial substrate and the second well region 7, relieve the sharp rise of current, avoid breakdown, increase the breakdown voltage, reduce the distance between the drain 16 and the guard ring 14, and reduce the size of the device. The width of the oxidation isolation structure 3 is between 1-2 microns. If the lateral width is too large, the lateral width of the transistor will be increased, and then the area of the transistor will be increased, the power consumption of the device will be increased, and the heat will increase, the switching speed will be reduced, and the integration of the device will be affected; if the lateral width is too thin, the breakdown voltage will be reduced.

Furthermore, the oxide isolation structure 3 is disposed in close proximity to the first well region 4 in the initial substrate, which can further enhance the anti-breakthrough capability of the transistor, increase the breakdown voltage, reduce the lateral width of the transistor, and reduce the area of the transistor.

The lateral double diffused field effect transistor provided by the present invention can avoid breakdown of the first well region and the substrate inside the device, improve the breakdown voltage of the lateral double diffused field effect transistor, and enhance the reliability of the transistor in high voltage applications.

Furthermore, the oxidation isolation structure 3 includes a plurality of strip-shaped oxidation isolation strips spaced apart from each other.

As shown in Fig. 9, specifically, in the embodiment of the present invention, the oxidation isolation structure 3 includes a plurality of strip-shaped oxidation isolation strips spaced apart from each other. Such a configuration can improve the barrier effect of the oxidation isolation structure 3 and improve the breakdown voltage of the device.

Please refer to Figure 10. The second aspect of the present invention provides a method for manufacturing a lateral double diffused field effect transistor, which comprises: S101: forming an initial substrate, and forming an oxidation isolation region 2 in the initial substrate, wherein the oxidation isolation region 2 is a strip-shaped configuration, formed at the junction of the defined body region 6 and the defined drift region 5, and extending downward from the middle area at the junction of the defined body region 6 and the defined drift region 5 to the defined first well region 4; S102: forming the first well region 4, the body region 6 and the drift region 5 by an ion implantation process; S103: forming an oxidation medium region 8 in the drift region 5 by a shallow trench isolation process; S104: forming a gate 11 by a thermal oxidation process and a vapor deposition process; wherein the polysilicon of the gate 11 extends toward the drift region 5 to cover the oxidation medium region 8, and the oxidation medium region 8 and the polysilicon covering the oxidation medium region 8 together serve as a field plate; S105: forming a source 15 and a drain 16 by an ion implantation process.

First, step S101 is performed: an initial substrate is formed, and an oxide isolation region 2 is formed in the initial substrate. The oxide isolation region 2 is a strip-shaped configuration, formed at the junction of the defined body region 6 and the defined drift region 5, and extending downward from the middle area at the junction of the defined body region 6 and the defined drift region 5 to the defined first well region 4.

Furthermore, the forming of the initial substrate and the forming of the oxidation isolation region 2 in the initial substrate include: providing an original substrate 1, and forming an oxidation isolation region 2 groove in the original substrate 1 through an etching process; filling the oxidation isolation region 2 groove by a chemical vapor deposition process to form the oxidation isolation region 2; bonding a layer of external substrate on the surface of the original substrate 1, and using the original substrate 1 and the external substrate as the initial substrate.

Furthermore, the method also includes: forming an oxidation isolation structure 3 while forming the oxidation isolation region 2; wherein the oxidation isolation structure 3 is formed on the side of the initial substrate close to the first well region 4, and extends downward from the bottom of the second shallow trench isolation 10 to below the first well region 4.

Specifically, in the embodiment of the present invention, the lateral double diffused field effect transistor provided can be an N-type lateral double diffused field effect transistor or a P-type lateral double diffused field effect transistor. When the lateral double diffused field effect transistor is an N-type lateral double diffused field effect transistor, the first doping type is P-type and the second doping type is N-type; when the lateral double diffused field effect transistor is a P-type lateral double diffused field effect transistor, the first doping type is N-type and the second doping type is P-type. The present invention does not limit this. The following text embodiment only takes the N-type lateral double diffused field effect transistor as an example for explanation.

First, a P-type original substrate 1 as shown in FIG. 1 is provided, and a thin oxide layer is grown on the surface of the original substrate 1. Then, a layer of photoresist is coated on the surface of the oxide layer, and the photoresist is exposed and developed to form an etching window. The original substrate 1 is dry-etched through the etching window to form the grooves of the oxidation isolation region 2 and the oxidation isolation structure 3 as shown in FIG. 2. The photoresist is removed, and a silicon dioxide medium is chemically vapor deposited, and silicon dioxide is filled in the grooves of the oxidation isolation region 2 and the oxidation isolation structure 3 to form the oxidation isolation region 2 and the oxidation isolation structure 3 as shown in FIG. 3. The oxidation isolation region 2 is a strip-shaped configuration, formed at the junction of the delimited body region 6 and the delimited drift region 5, and extends downward from the middle area at the junction of the delimited body region 6 and the delimited drift region 5 to the delimited first well region 4. The oxidation isolation structure 3 is formed on the side of the initial substrate close to the first well region 4, and extends downward from the bottom of the second shallow trench isolation 10 to below the first well region 4. Please refer to FIG. 4, chemical mechanical polishing removes silicon dioxide on the surface of the original substrate 1. Then, a P-type external substrate is bonded to the surface of the original substrate 1, and then the external substrate is thinned, and the original substrate 1 and the external substrate are used as initial substrates.

Furthermore, the oxide isolation region 2 extends into the bottom of the designated first well region 4, so that the oxide isolation region 2 can be manufactured simultaneously with the oxide isolation structure 3, using a consistent depth, simplifying the steps of etching the grooves of the oxide isolation region 2 and the oxide isolation structure 3, and only one etching is required to form the oxide isolation region 2 and the oxide isolation structure 3 grooves.

Then, step S102 is performed: a first well region 4 , a body region 6 and a drift region 5 are formed by an ion implantation process.

Furthermore, the body region 6 is doped with ions of the first conductivity type; the method further comprises: forming a second well region 7 doped with ions of the first conductivity type on a side of the initial substrate away from the body region 6 by an ion implantation process.

As shown in FIG5 , specifically, in an embodiment of the present invention, a thin silicon dioxide layer is thermally oxidized on the surface of the initial substrate to form a sacrificial oxide layer, and then a photoresist layer is formed on the sacrificial oxide layer, and the photoresist layer is exposed and developed to form an injection window, and the initial substrate is injected with N-type high-energy ions through the injection window to form an N-type first well region 4. Then, a photoresist layer is formed again, and the photoresist layer is exposed and developed to form an injection window, and the first well region 4 is injected with N-type high-energy ions through the injection window to form a drift region 5. Next, a photoresist layer is formed again, and the photoresist layer is exposed and developed to form an injection window, and the first well region 4 is injected with P-type high-energy ions through the injection window to form a body region 6. Next, a photoresist layer is formed again, and the photoresist layer is exposed and developed to form an injection window, and the side of the initial substrate away from the body region 6 is injected with P-type high-energy ions through the injection window to form a second well region 7. High-temperature annealing is performed to remove the sacrificial oxide layer on the surface of the initial substrate.

Then, step S103 is performed: forming an oxidizing medium region 8 in the drift region 5 by using a shallow trench isolation process.

Furthermore, the method further includes: forming a first shallow trench isolation 9 between the drain 16 and the second guard ring 17 .

Furthermore, the method further includes: forming a second shallow trench isolation 10 between the second protection ring 17 and the third protection ring 14 while forming the first shallow trench isolation 9 ; and forming a polysilicon protection structure 12 on the surface of the second shallow trench isolation 10 .

Specifically, in the embodiment of the present invention, a thick layer of silicon dioxide is oxidized again on the surface of the initial substrate, silicon nitride is vapor-deposited, photolithography is performed, silicon nitride and silicon dioxide are dry-etched, the initial substrate is dry-etched, a groove of the oxidized dielectric region 8 is formed in the drift region 5, a groove of the first shallow trench isolation 9 is formed between the delimited drain 16 and the delimited second guard ring 17, and a groove of the second shallow trench isolation 10 is formed between the delimited second guard ring 17 and the delimited third guard ring 14. High-density plasma chemical vapor deposition of silicon dioxide dielectric, high-temperature annealing, chemical mechanical polishing to remove the silicon dioxide dielectric on the surface, wet removal of silicon nitride and thick silicon dioxide, to form the oxidized dielectric region 8, the first shallow trench isolation 9 and the second shallow trench isolation 10 as shown in FIG.

Then, step S104 is performed: a gate 11 is formed by a thermal oxidation process and a vapor deposition process; wherein the polysilicon of the gate 11 extends toward the drift region 5 to cover the oxidizing medium region 8, and the oxidizing medium region 8 and the polysilicon covering the oxidizing medium region 8 together serve as a field plate.

As shown in FIG7 , specifically, in the embodiment of the present invention, thermal oxidation is performed on the surface of the initial substrate to form a thin oxide layer, and the oxide layer on the body region 6 is used as a gate oxide. A layer of N-type heavily doped polysilicon is deposited by low-pressure chemical vapor phase, a photoresist is formed on the polysilicon, the photoresist is etched to form an etching window, and the polysilicon is etched through the etching window to retain the polysilicon on a portion of the oxidation medium region 8, the polysilicon on the surface of the body region 6 adjacent to the drift region 5, and the polysilicon on the surface of the second shallow trench isolation 10. The polysilicon on the surface of the body region 6 adjacent to the drift region 5 and the gate oxide below constitute the gate 11, and the oxidation medium region 8 and the polysilicon thereon constitute the field plate. Since the oxidation medium region 8 is formed in the initial substrate, it can disperse the electric field between the surface and the middle region of the transistor, and prevent the breakdown of the surface and the middle region of the device. The second shallow trench isolation 10 and the polysilicon protection structure 12 can disperse the surface electric field of the transistor at this location, and prevent the breakdown between the second protection ring 17 and the third protection ring 14. The transistor can withstand higher voltages without dielectric breakdown, enhancing the reliability of the transistor in high-voltage applications.

Finally, step S105 is performed: forming the source 15 and the drain 16 by using an ion implantation process.

Furthermore, the method also includes: using an ion implantation process to form a first guard ring 13 heavily doped with ions of the first conductivity type in the body region 6 and close to the source 15; using an ion implantation process to form a second guard ring 17 heavily doped with ions of the second conductivity type on the side of the first well region 4 close to the drift region 5; wherein the second conductivity type is different from the first conductivity type in ion doping type; and using an ion implantation process to form a third guard ring 14 heavily doped with ions of the first conductivity type in the second well region 7.

Specifically, in the embodiment of the present invention, please refer to FIG8 , a thin silicon dioxide layer is thermally oxidized on the surface of the initial substrate to form a sacrificial oxide layer, and then a photoresist layer is formed on the sacrificial oxide layer, and the photoresist layer is exposed and developed to form an injection window, and the initial substrate is injected with N-type heavily doped ions through the injection window, and a source 15 is formed in the body region 6, and a drain 16 is formed in the drift region 5, and a second guard ring 17 is formed on the side of the first well region 4 close to the drift region 5. The photoresist is removed, and then the photoresist layer is re-formed, and the photoresist layer is exposed and developed to form an injection window, and P-type heavily doped ions are injected into the body region 6 and the second well region 7 through the injection window, and a first guard ring 13 heavily doped with the first conductive type ions is formed on the side of the body region 6 close to the source 15, and a third guard ring 14 heavily doped with the first conductive type ions is formed in the second well region 7, and voltage protection is provided to the lateral double diffused field effect transistor. High temperature annealing is performed to remove the sacrificial oxide layer on the surface of the initial substrate. The implantation dose of the N-type heavily doped ions is greater than that of the P-type heavily doped ions, and the implantation energy of the N-type heavily doped ions is less than that of the P-type heavily doped ions.

A third aspect of the present invention provides a chip, which includes the lateral double diffused field effect transistor described above.

A fourth aspect of the present invention provides a circuit comprising the lateral double diffused field effect transistor described above.

The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims (17)

1. A lateral double diffused field effect transistor, comprising: an initial substrate, a first well region, a body region, a drift region, a source, a drain, and a gate, wherein the lateral double diffused field effect transistor further comprises: An oxidized dielectric region is formed in the drift region and is covered by polysilicon extending from the gate, the oxidized dielectric region and the polysilicon covering the oxidized dielectric region together serve as a field plate; wherein the oxidized dielectric region is made by a shallow trench isolation process; The oxidized isolation region is in a strip-shaped configuration, is formed at the junction of the body region and the drift region, and extends downward from a middle area at the junction of the body region and the drift region to the first well region. 2 . The lateral double diffused field effect transistor according to claim 1 , wherein the oxide isolation region extends to a middle area of the first well region. 3. The lateral double diffused field effect transistor according to claim 1, wherein the body region has ion doping of the first conductivity type; The lateral double diffused field effect transistor further comprises: The second well region is formed on a side of the initial substrate away from the body region, and the second well region is doped with ions of the first conductivity type. 4. The lateral double diffused field effect transistor according to claim 3, characterized in that the lateral double diffused field effect transistor further comprises: A first guard ring, formed in the body region and close to the source, and heavily doped with ions of a first conductivity type; A second guard ring is formed on a side of the first well region close to the drift region and is heavily doped with ions of a second conductivity type; wherein the ion doping type of the second conductivity type is different from that of the first conductivity type; The third guard ring is formed in the second well region and is heavily doped with ions of the first conductivity type. 5. The lateral double diffused field effect transistor according to claim 4, characterized in that the lateral double diffused field effect transistor further comprises: A first shallow trench isolation is formed between the drain and the second guard ring. 6. The lateral double diffused field effect transistor according to claim 4, characterized in that the lateral double diffused field effect transistor further comprises: A second shallow trench isolation is formed between the second guard ring and the third guard ring; A polysilicon protection structure is formed on the second shallow trench isolation surface. 7. The lateral double diffused field effect transistor according to claim 6, characterized in that the lateral double diffused field effect transistor further comprises: The oxidation isolation structure is formed on a side of the initial substrate close to the first well region and extends downward from the bottom of the second shallow trench isolation to below the first well region. 8 . The lateral double diffused field effect transistor according to claim 7 , wherein the oxide isolation structure comprises a plurality of strip-shaped oxide isolation strips spaced apart from each other. 9. A method for manufacturing a lateral double diffused field effect transistor, characterized in that the method for manufacturing a lateral double diffused field effect transistor comprises: forming an initial substrate, and forming an oxidized isolation region in the initial substrate, wherein the oxidized isolation region is in a stripe configuration, is formed at the junction of the defined body region and the defined drift region, and extends downward from the middle region of the junction of the defined body region and the defined drift region to the defined first well region; forming a first well region, a body region and a drift region by using an ion implantation process; forming an oxidizing medium region in the drift region by using a shallow trench isolation process; A gate is formed by using a thermal oxidation process and a vapor deposition process; wherein the polysilicon of the gate extends toward the drift region to cover the oxidation medium region, and the oxidation medium region and the polysilicon covering the oxidation medium region together serve as a field plate; The source and drain are formed by ion implantation. 10. The method for manufacturing a lateral double diffused field effect transistor according to claim 9, wherein the forming of an initial substrate and forming an oxidized isolation region in the initial substrate comprises: Providing an original substrate, and forming an oxidation isolation region trench on the original substrate by an etching process; Filling the oxidation isolation region trenches by chemical vapor deposition process to form the oxidation isolation region; A layer of external substrate is bonded on the surface of the original substrate, and the original substrate and the external substrate are used as the initial substrate. 11. The method for manufacturing a lateral double diffused field effect transistor according to claim 9, wherein the body region has ion doping of a first conductivity type; The method further comprises: By using an ion implantation process, a second well region doped with ions of the first conductivity type is formed on a side of the initial substrate away from the body region. 12. The method for manufacturing a lateral double diffused field effect transistor according to claim 11, characterized in that the method further comprises: Using an ion implantation process, forming a first guard ring heavily doped with ions of a first conductivity type in the body region and close to the source; Using an ion implantation process, a second guard ring heavily doped with ions of a second conductivity type is formed on a side of the first well region close to the drift region; wherein the ion doping type of the second conductivity type is different from that of the first conductivity type; By using an ion implantation process, a third guard ring heavily doped with ions of the first conductivity type is formed in the second well region. 13. The method for manufacturing a lateral double diffused field effect transistor according to claim 12, characterized in that the method further comprises: A first shallow trench isolation is formed between the drain and the second guard ring. 14. The method for manufacturing a lateral double diffused field effect transistor according to claim 13, characterized in that the method further comprises: While forming the first shallow trench isolation, forming a second shallow trench isolation between the second guard ring and the third guard ring; A polysilicon protection structure is formed on the surface of the second shallow trench isolation. 15. The method for manufacturing a lateral double diffused field effect transistor according to claim 14, characterized in that the method further comprises: An oxidation isolation structure is formed while forming the oxidation isolation region; wherein the oxidation isolation structure is formed on a side of the initial substrate close to the first well region and extends downward from the bottom of the second shallow trench isolation to below the first well region. 16. A chip, characterized in that the chip comprises the lateral double diffused field effect transistor according to any one of claims 1 to 8. 17. A circuit, characterized in that the circuit comprises the lateral double diffused field effect transistor according to any one of claims 1 to 8.