CN118263328B - Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit - Google Patents
Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit Download PDFInfo
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- CN118263328B CN118263328B CN202410669086.0A CN202410669086A CN118263328B CN 118263328 B CN118263328 B CN 118263328B CN 202410669086 A CN202410669086 A CN 202410669086A CN 118263328 B CN118263328 B CN 118263328B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
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- 230000003647 oxidation Effects 0.000 claims abstract description 110
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 210000000746 body region Anatomy 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 67
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 150000002500 ions Chemical class 0.000 claims description 49
- 238000005468 ion implantation Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005019 vapor deposition process Methods 0.000 claims description 4
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- 230000015556 catabolic process Effects 0.000 abstract description 41
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- 229920002120 photoresistant polymer Polymers 0.000 description 18
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- 238000002513 implantation Methods 0.000 description 8
- 230000001965 increasing effect Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides a transverse double-diffusion field effect transistor, a manufacturing method, a chip and a circuit, and relates to the technical field of semiconductors. The transistor includes: the initial substrate, the first well region, the body region, the drift region, the source electrode, the drain electrode and the grid electrode, and the lateral double-diffusion field effect transistor further comprises: the oxidation medium region is formed in the drift region and is covered by polysilicon extending out of the grid electrode, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together; wherein the oxidation medium region is manufactured by a shallow trench isolation process; the oxidation isolation region is in a strip-shaped structure, is formed at the junction of the body region and the drift region, and extends downwards to the first well region from the middle region at the junction of the body region and the drift region. The transistor provided by the invention can avoid breakdown inside the device, improve the breakdown voltage of the transverse double-diffusion field effect transistor and enhance the reliability of the transistor in high-voltage application.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a lateral double-diffused field effect transistor, a chip, and a circuit.
Background
The Lateral Double-diffused field effect transistor (LDMOS) is used as a Lateral power device, electrodes of the Lateral Double-Diffused MOSFET are all positioned on the surface of the device, monolithic integration with a low-voltage signal circuit and other devices is easy to realize through internal connection, and the Lateral Double-diffused field effect transistor has the advantages of high voltage resistance, large gain, good linearity, high efficiency, good broadband matching performance and the like, and is widely applied to power integrated circuits, in particular to low-power consumption and high-frequency circuits.
In the prior art, in order to increase the breakdown voltage, a layer of oxide is grown on the surface of the substrate by using a thermal oxidation process to manufacture a field plate so as to reduce the surface electric field. But this only prevents breakdown of the surface from occurring, which still occurs deep from the substrate surface, so the breakdown voltage of the device is high.
Disclosure of Invention
Aiming at the technical problems that breakdown is easy to occur in a device and breakdown voltage is high in the prior art, the invention provides a transverse double-diffusion field effect transistor, a transverse double-diffusion field effect transistor manufacturing method, a chip and a circuit.
To achieve the above object, a first aspect of the present invention provides a lateral double diffusion field effect transistor, comprising: an initial substrate, a first well region, a body region, a drift region, a source, a drain, a gate, the lateral double-diffused field effect transistor further comprising: the oxidation medium region is formed in the drift region and is covered by polysilicon extending out of the grid electrode, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together; wherein the oxidation medium region is manufactured by a shallow trench isolation process; the oxidation isolation region is in a strip-shaped configuration, is formed at the junction of the body region and the drift region, and extends downwards from the middle region at the junction of the body region and the drift region to the first well region.
Further, the oxide isolation region extends to a middle region of the first well region.
Further, the body region has ion doping of the first conductivity type; the lateral double-diffusion field effect transistor further includes: and the second well region is formed on one side of the initial substrate far away from the body region and is provided with ion doping of the first conductivity type.
Further, the lateral double-diffusion field effect transistor further includes: the first protection ring is formed in the body region and is close to the source electrode, and is heavily doped with ions of a first conductivity type; the second protection ring is formed on one side of the first well region, close to the drift region, and is provided with ion heavy doping of a second conductivity type; wherein the second conductivity type is different from the ion doping species of the first conductivity type; and the third protection ring is formed in the second well region and is provided with ion heavy doping of the first conductivity type.
Further, the lateral double-diffusion field effect transistor further includes: and the first shallow groove isolation is formed between the drain electrode and the second protection ring.
Further, the lateral double-diffusion field effect transistor further includes: a second shallow trench isolation formed between the second guard ring and the third guard ring; and the polysilicon protection structure is formed on the second shallow slot isolation surface.
Further, the lateral double-diffusion field effect transistor further includes: and the oxidation isolation structure is formed on one side of the initial substrate close to the first well region and extends downwards from the bottom of the second shallow trench isolation to the lower part of the first well region.
Further, the oxidation isolation structure comprises a plurality of strip-shaped oxidation isolation strips which are mutually spaced.
A second aspect of the present invention provides a method of manufacturing a lateral double-diffused field effect transistor, the method comprising: forming an initial substrate, and forming an oxidation isolation region in the initial substrate, wherein the oxidation isolation region is in a strip-shaped configuration, is formed at the junction of the demarcation body region and the demarcation drift region, and extends downwards from the middle region at the junction of the demarcation body region and the demarcation drift region to the demarcation first well region; forming a first well region, a body region and a drift region by utilizing an ion implantation process; forming an oxidation medium region in the drift region by using a shallow trench isolation process; forming a grid electrode by utilizing a thermal oxidation process and a vapor deposition process; the polysilicon of the grid extends to the drift region to cover the oxidation medium region, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together; the source and drain electrodes are formed using an ion implantation process.
Further, the forming an initial substrate and forming an oxidation isolation region in the initial substrate includes: providing an original substrate, and forming an oxidation isolation region groove on the original substrate through an etching process; filling the oxidation isolation region groove by using a chemical vapor deposition process to form the oxidation isolation region; and bonding an external substrate on the surface of the original substrate, and taking the original substrate and the external substrate as the initial substrate.
Further, the body region has ion doping of the first conductivity type; the method further comprises the steps of: and forming a second well region doped with ions of the first conductivity type on one side of the initial substrate away from the body region by utilizing an ion implantation process.
Further, the method further comprises: forming a first protection ring heavily doped with ions of a first conductivity type at the body region and proximate to the source electrode by using an ion implantation process; forming a second protection ring with ion heavy doping of a second conductivity type on one side of the first well region, which is close to the drift region, by utilizing an ion implantation process; wherein the second conductivity type is different from the ion doping species of the first conductivity type; and forming a third protection ring which is heavily doped with ions of the first conductivity type in the second well region by utilizing an ion implantation process.
Further, the method further comprises: a first shallow trench isolation is formed between the drain and the second guard ring.
Further, the method further comprises: forming a second shallow trench isolation between the second guard ring and the third guard ring while forming the first shallow trench isolation; and forming a polysilicon protection structure on the second shallow slot isolation surface.
Further, the method further comprises: forming an oxidation isolation structure at the same time of forming the oxidation isolation region; the oxidation isolation structure is formed on one side of the initial substrate close to the first well region, and extends downwards from the bottom of the second shallow trench isolation to the position below the first well region.
A third aspect of the invention provides a chip comprising a lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a lateral double diffused field effect transistor as described above.
Through the technical scheme provided by the invention, the invention has at least the following technical effects:
The lateral double-diffusion field effect transistor of the present invention includes: the device comprises an initial substrate, a first well region, a body region, a drift region, a source electrode, a drain electrode and a grid electrode. An oxidation medium region is formed in the drift region through a shallow trench isolation process, the oxidation medium region is covered by polysilicon extending from the grid electrode, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together. The oxidation dielectric region is formed in the substrate, and can disperse the electric fields of the surface of the transistor and the middle region, so that breakdown of the surface of the device and the middle region is prevented. An oxidation isolation region is formed at the junction of the body region and the drift region, the oxidation isolation region is in a strip-shaped configuration, and the oxidation isolation region extends downwards to the first well region from the middle region at the junction of the body region and the drift region. The electron-hole pair movement at the junction of the body region and the drift region in the device can be avoided, the abrupt current rise is relieved, and breakdown is avoided. The lateral double-diffusion field effect transistor provided by the invention can avoid breakdown inside the device, improve the breakdown voltage of the lateral double-diffusion field effect transistor and enhance the reliability of the transistor in high-voltage application.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
fig. 1 is a schematic structural diagram of an original substrate formed in a method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
Fig. 2 is a schematic structural diagram of a trench in an oxide isolation region and a trench in an oxide isolation structure formed in a method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an oxide isolation region and an oxide isolation structure formed in a method for fabricating a lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an initial substrate formed in a method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
Fig. 5 is a schematic structural diagram of a first well region, a second well region, a body region and a drift region formed in a method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an oxidized dielectric region, a first shallow trench isolation and a second shallow trench isolation formed in a method for fabricating a lateral double-diffused field effect transistor according to an embodiment of the present invention;
Fig. 7 is a schematic structural diagram of a gate, a field plate and a polysilicon protection structure formed in the method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a lateral double-diffused field effect transistor formed in the method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a lateral double-diffused field effect transistor formed in the method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention;
fig. 10 is a flowchart of a method for manufacturing a lateral double-diffused field effect transistor according to an embodiment of the present invention.
Description of the reference numerals
1-An original substrate; a 2-oxide isolation region; 3-oxidizing the isolation structure; 4-a first well region; a 5-drift region; 6-body region; 7-a second well region; 8-an oxidation medium zone; 9-first shallow trench isolation; 10-second shallow trench isolation; 11-gate; 12-a polysilicon protection structure; 13-a first protection ring; 14-a third guard ring; 15-source electrode; 16-drain electrode; 17-a second guard ring.
Detailed Description
The following describes the detailed implementation of the embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
In the present invention, unless otherwise indicated, terms of orientation such as "upper, lower, top, bottom" are used generally with respect to the orientation shown in the drawings or with respect to the positional relationship of the various components with respect to one another in the vertical, vertical or gravitational directions.
The invention will be described in detail below with reference to the drawings in connection with embodiments.
Referring to fig. 8, a first aspect of the present invention provides a lateral double-diffused field effect transistor, which includes: the initial substrate, the first well region 4, the body region 6, the drift region 5, the source 15, the drain 16, the gate 11, the lateral double diffusion field effect transistor further comprises: an oxidation medium region 8 formed in the drift region 5 and covered by polysilicon extending from the gate 11, wherein the oxidation medium region 8 and the polysilicon covered on the oxidation medium region 8 together serve as a field plate; wherein the oxidation medium region 8 is manufactured by a shallow trench isolation process; and the oxidation isolation region 2 is in a strip-shaped configuration, is formed at the junction of the body region 6 and the drift region 5, and extends downwards from the middle region at the junction of the body region 6 and the drift region 5 to the first well region 4.
Specifically, in an embodiment of the present invention, a lateral double diffusion field effect transistor includes: the initial substrate, the body region 6 and the drift region 5 are adjacently formed in the first well region 4, the source 15 is formed in the body region 6, the drain 16 is formed in the drift region 5, and the gate 11 is formed on the surface of the body region 6. The oxidation dielectric region 8 is formed in the drift region 5 by shallow trench isolation technology, polysilicon extending from the gate 11 covers the surface of the oxidation dielectric region 8, and the oxidation dielectric region 8 and the polysilicon covered thereon form a field plate structure. The oxidation dielectric region 8 is formed in the initial substrate, and can reduce the electric field of the transistor surface and prevent breakdown of the device surface.
An oxidation isolation region 2 is formed at the junction of the body region 6 and the drift region 5, the oxidation isolation region 2 extends downwards from the middle region at the junction of the body region 6 and the drift region 5 to the first well region 4, and the oxidation isolation region 2 is in a strip-shaped configuration. Since the body region 6 and the drift region 5 are doped with different types, when the voltage applied by the device reaches a certain level, electrons and holes in the body region 6 and the drift region 5 obtain enough energy under the action of an electric field, collide with atoms in the semiconductor, and generate more electron-hole pairs. These electron-hole pairs continue to move under the action of the electric field, further striking atoms, forming a chain reaction, causing a sharp rise in current and breakdown. The oxidation isolation region 2 can prevent electron-hole pairs from moving at the junction of the body region 6 and the drift region 5 in the initial substrate, so that the abrupt current rise is relieved, and breakdown is avoided. The oxide isolation region 2 has a high breakdown voltage, and the breakdown field strength is 10MV/cm, so that avalanche breakdown does not occur.
The lateral double-diffusion field effect transistor provided by the invention can avoid breakdown inside the device, improve the breakdown voltage of the lateral double-diffusion field effect transistor and enhance the reliability of the transistor in high-voltage application.
Further, the lateral width of the oxide isolation region 2 is between 0.5 and 1.5 microns. If the lateral width is too large, the lateral width of the transistor is increased, the area of the transistor is increased, the power consumption of the device is improved, the switching speed is reduced along with the increase of the heating value, and the integration level of the device is affected; if the lateral width is too thin, the breakdown voltage is reduced.
Further, the oxide isolation region 2 extends to the middle area of the first well region 4, and since the first well region 4 needs an external voltage, the oxide isolation region 2 does not block the first well region 4 when extending to the middle area of the first well region 4, and the first well region 4 on the left side can be externally connected with the first well region 4 on the right side through the second guard ring 17. Therefore, the first well region 4 on the left side does not need to be externally connected with voltage independently, so that the manufacturing steps of the transistor are simplified, the manufacturing cost is reduced, and the manufacturing efficiency is improved.
Further, the body region 6 has ion doping of the first conductivity type; the lateral double-diffusion field effect transistor further includes: a second well region 7 formed on a side of the initial substrate remote from the body region 6, the second well region 7 having ion doping of the first conductivity type.
Specifically, in the embodiment of the present invention, a second well region 7 is formed on a side of the initial substrate away from the body region 6, and the second well region 7 and the body region 6 are both doped with ions of the first conductivity type. The second well region 7 can improve the withstand voltage performance of the device, and when the transistor is affected by external voltage, the second well region 7 can effectively prevent the voltage from further increasing, so that the transistor is protected from being damaged.
Further, the lateral double-diffusion field effect transistor further includes: a first guard ring 13 formed in the body region 6 and adjacent to the source electrode 15, having ion heavy doping of the first conductivity type; a second guard ring 17 formed on a side of the first well region 4 near the drift region 5, and having ion heavy doping of the second conductivity type; wherein the second conductivity type is different from the ion doping species of the first conductivity type; a third guard ring 14 formed in the second well region 7 and heavily doped with ions of the first conductivity type.
Specifically, in the embodiment of the present invention, a guard ring is further formed in the lateral double-diffused field effect transistor, and the first guard ring 13 is formed in the body region 6 and is disposed close to the source electrode 15, and has ion heavy doping of the first conductivity type. The first guard ring 13 is capable of voltage protecting the lateral double diffused field effect transistor. And meanwhile, carriers flowing into the body region 6 from the drift region 5 when the field effect transistor is conducted can be adsorbed, the concentration of the carriers in the body region 6 is reduced, the conduction of parasitic triodes in the transverse double-diffusion field effect transistor is avoided, and the breakdown voltage of the transverse double-diffusion field effect transistor is improved.
A second guard ring 17 is formed on the side of the first well region 4 near the drift region 5, and the second guard ring 17 is heavily doped with ions of the second conductivity type. A third guard ring 14 heavily doped with ions of the first conductivity type is formed in the second well region 7. The second guard ring 17 and the third guard ring 14 can be externally connected with voltage to perform voltage protection on the lateral double-diffusion field effect transistor.
Further, the lateral double-diffusion field effect transistor further includes: a first shallow trench isolation 9 is formed between the drain 16 and the second guard ring 17. The first shallow trench isolation 9 is used for isolation.
Further, the lateral double-diffusion field effect transistor further includes: a second shallow trench isolation 10 formed between the second guard ring 17 and the third guard ring 14; and a polysilicon protection structure 12 formed on the surface of the second shallow trench isolation 10.
Specifically, in the embodiment of the present invention, the second guard ring 17 is heavily doped with the second conductivity type, and the third guard ring 14 is heavily doped with the first conductivity type, so that breakdown occurs between the second guard ring 17 and the third guard ring 14 when the voltage applied between the second guard ring 17 and the third guard ring 14 is too high. In order to avoid breakdown, a second shallow trench isolation 10 is formed between the second guard ring 17 and the third guard ring 14, the second guard ring 17 and the third guard ring 14 are isolated, meanwhile, a polysilicon guard structure 12 is formed on the surface of the second shallow trench isolation 10, and the second shallow trench isolation 10 and the polysilicon guard structure 12 can disperse the surface electric field of the transistor at the place, so that breakdown between the second guard ring 17 and the third guard ring 14 is prevented. The transistor is able to withstand higher voltages without dielectric breakdown, enhancing the reliability of the transistor in high voltage applications.
According to the lateral double-diffusion field effect transistor provided by the invention, breakdown between the second guard ring 17 and the third guard ring 14 can be prevented, the breakdown voltage of the device is improved, and the reliability of the transistor in high-voltage application is enhanced.
Further, the lateral double-diffusion field effect transistor further includes: and an oxidation isolation structure 3 which is formed on one side of the initial substrate close to the first well region 4 and extends downwards from the bottom of the second shallow trench isolation 10 to the position below the first well region 4.
Specifically, in the embodiment of the present invention, the first well region 4 and the initial substrate have different conductive types, so that a PN junction can be formed, and when the voltage applied by the first well region 4 and the initial substrate reaches a certain level, electrons and holes in the first well region 4 and the initial substrate obtain enough energy under the action of an electric field, collide with atoms in the semiconductor, and generate more electron-hole pairs. These electron-hole pairs continue to move under the action of the electric field, further striking atoms, forming a chain reaction, causing a sharp rise in current and breakdown. The second shallow trench isolation 10 and the polysilicon protection structure 12, while capable of reducing the electric field at the surface of the initial substrate to prevent surface breakdown, still cause breakdown inside the initial substrate. In order to avoid breakdown between the inside of the initial substrate and the first well region 4, an oxidation isolation structure 3 is formed between the first well region 4 and the second well region 7 on the side of the initial substrate close to the drift region 5, the oxidation isolation structure 3 is not in contact with the second shallow trench isolation 10, and the oxidation isolation structure 3 extends downwards from the bottom of the second shallow trench isolation 10 to below the first well region 4. The oxidation isolation structure 3 can prevent electron-hole pairs from moving between the first well region 4 and the initial substrate and the second well region 7, relieve the current from rising sharply, avoid breakdown, improve breakdown voltage, reduce the distance between the drain electrode 16 and the guard ring 14, and reduce the size of the device. The width of the oxidation isolation structure 3 is between 1 and 2 micrometers, if the lateral width is too large, the lateral width of the transistor is increased, the area of the transistor is increased, the power consumption of the device is improved, the switching speed is reduced along with the increase of the heating value, and the integration level of the device is influenced; if the lateral width is too thin, the breakdown voltage is reduced.
Further, the oxidation isolation structure 3 is arranged in the initial substrate and is closely attached to the first well region 4, so that breakdown resistance of the transistor can be further enhanced, breakdown voltage is improved, lateral width of the transistor is reduced, and area of the transistor is reduced.
According to the transverse double-diffusion field effect transistor provided by the invention, the first well region and the substrate can be prevented from being broken down in the device, the breakdown voltage of the transverse double-diffusion field effect transistor is improved, and the reliability of the transistor in high-voltage application is enhanced.
Further, the oxidation isolation structure 3 comprises a plurality of strip-shaped oxidation isolation strips which are spaced from each other.
As shown in fig. 9, in particular, in the embodiment of the present invention, the oxidation isolation structure 3 includes a plurality of strip-shaped oxidation isolation strips spaced apart from each other. This arrangement can improve the blocking effect of the oxide isolation structure 3 and improve the breakdown voltage of the device.
Referring to fig. 10, a second aspect of the present invention provides a method for manufacturing a lateral double-diffused field effect transistor, the method comprising: s101: forming an initial substrate, and forming an oxidation isolation region 2 in the initial substrate, wherein the oxidation isolation region 2 is in a strip-shaped configuration, is formed at the junction of a demarcation body region 6 and a demarcation drift region 5, and extends downwards from the middle region at the junction of the demarcation body region 6 and the demarcation drift region 5 to the demarcation first well region 4; s102: forming a first well region 4, a body region 6 and a drift region 5 by using an ion implantation process; s103: forming an oxidation medium region 8 in the drift region 5 by using a shallow trench isolation process; s104: forming a gate electrode 11 using a thermal oxidation process and a vapor deposition process; the polysilicon of the gate 11 extends to the drift region 5 to cover the oxidation medium region 8, and the oxidation medium region 8 and the polysilicon covered on the oxidation medium region 8 are used together as a field plate; s105: the source electrode 15 and the drain electrode 16 are formed using an ion implantation process.
Step S101 is first performed: an initial substrate is formed, an oxidation isolation region 2 is formed in the initial substrate, the oxidation isolation region 2 is in a strip-shaped configuration, the oxidation isolation region is formed at the junction of the demarcation body region 6 and the demarcation drift region 5, and the oxidation isolation region extends downwards from the middle region at the junction of the demarcation body region 6 and the demarcation drift region 5 to the demarcation first well region 4.
Further, the forming an initial substrate and forming an oxidation isolation region 2 in the initial substrate includes: providing an original substrate 1, and forming a trench of an oxidation isolation region 2 in the original substrate 1 through an etching process; filling the groove of the oxidation isolation region 2 by using a chemical vapor deposition process to form the oxidation isolation region 2; and bonding an external substrate on the surface of the original substrate 1, and taking the original substrate 1 and the external substrate as the initial substrate.
Further, the method further comprises: forming an oxidation isolation structure 3 at the same time of forming the oxidation isolation region 2; the oxide isolation structure 3 is formed on one side of the initial substrate close to the first well region 4, and extends downwards from the bottom of the second shallow trench isolation 10 to below the first well region 4.
Specifically, in the embodiment of the invention, the provided lateral double-diffusion field effect transistor can be an N-type lateral double-diffusion field effect transistor or a P-type lateral double-diffusion field effect transistor. When the lateral double-diffusion field effect transistor is an N-type lateral double-diffusion field effect transistor, the first doping type is P-type, and the second doping type is N-type; when the ldfet is a P-type ldfet, the first doping type is N-type and the second doping type is P-type, which is not limited in this regard, and the N-type ldfet is only used as an example in the following embodiments.
First, a P-type original substrate 1 shown in fig. 1 is provided, and a thin oxide layer is grown on the surface of the original substrate 1. And then coating a layer of photoresist on the surface of the oxide layer, exposing and developing the photoresist to form an etching window, and carrying out dry etching on the original substrate 1 through the etching window to form grooves of the oxide isolation region 2 and the oxide isolation structure 3 shown in fig. 2. And removing the photoresist, and performing chemical vapor deposition on a silicon dioxide medium to fill silicon dioxide into the grooves of the oxidation isolation region 2 and the oxidation isolation structure 3 to form the oxidation isolation region 2 and the oxidation isolation structure 3 shown in figure 3. The oxidation isolation region 2 is in a strip-shaped configuration, is formed at the junction between the demarcation body region 6 and the demarcation drift region 5, and extends downwards from the middle region at the junction between the demarcation body region 6 and the demarcation drift region 5 to the demarcation first well region 4. The oxide isolation structure 3 is formed on one side of the initial substrate close to the first well region 4, and extends downwards from the bottom of the second shallow trench isolation 10 to the lower part of the first well region 4. Referring to fig. 4, the chemical mechanical polishing removes silicon dioxide from the surface of the original substrate 1. Then, a P-type external substrate is adhered to the surface of the original substrate 1, and then the external substrate is thinned, and the original substrate 1 and the external substrate are used as initial substrates.
Furthermore, the oxide isolation region 2 extends into the bottom of the first well region 4, so that the oxide isolation region 2 and the oxide isolation structure 3 can be manufactured simultaneously, the step of etching the trenches of the oxide isolation region 2 and the oxide isolation structure 3 is simplified by adopting the same depth, and the trenches of the oxide isolation region 2 and the oxide isolation structure 3 can be formed by one etching.
Step S102 is then performed: the first well region 4, the body region 6 and the drift region 5 are formed using an ion implantation process.
Further, the body region 6 has ion doping of the first conductivity type; the method further comprises the steps of: a second well region 7 having ion doping of the first conductivity type is formed at a side of the initial substrate remote from the body region 6 using an ion implantation process.
As shown in fig. 5, in particular, in the embodiment of the present invention, a thin silicon dioxide layer is thermally oxidized on the surface of an initial substrate to form a sacrificial oxide layer, then a photoresist layer is formed on the sacrificial oxide layer, the photoresist layer is exposed and developed to form an implantation window, and N-type high-energy ion implantation is performed on the initial substrate through the implantation window to form an N-type first well region 4. Then, a photoresist layer is formed, the photoresist layer is exposed and developed to form an injection window, and N-type high-energy ion injection is carried out on the first well region 4 through the injection window to form a drift region 5. Then, a photoresist layer is formed, the photoresist layer is exposed and developed to form an implantation window, and P-type high-energy ion implantation is performed on the first well region 4 through the implantation window to form a body region 6. Then, a photoresist layer is formed, the photoresist layer is exposed and developed to form an injection window, and P-type high-energy ion injection is carried out on one side of the initial substrate far away from the body region 6 through the injection window to form a second well region 7. And (5) high-temperature annealing to remove the sacrificial oxide layer on the surface of the initial substrate.
Step S103 is then performed: an oxidation dielectric region 8 is formed in the drift region 5 using a shallow trench isolation process.
Further, the method further comprises: a first shallow trench isolation 9 is formed between the drain 16 and the second guard ring 17.
Further, the method further comprises: forming a second shallow trench isolation 10 between the second guard ring 17 and the third guard ring 14 while forming the first shallow trench isolation 9; a polysilicon protection structure 12 is formed on the surface of the second shallow trench isolation 10.
Specifically, in the embodiment of the present invention, a layer of silicon dioxide is oxidized again on the surface of the initial substrate, silicon nitride is vapor deposited, photolithography is performed, silicon nitride and silicon dioxide are dry etched, the initial substrate is dry etched, a trench of the oxide dielectric region 8 is formed in the drift region 5, a trench of the first shallow trench isolation 9 is formed between the demarcation drain electrode 16 and the demarcation second guard ring 17, and a trench of the second shallow trench isolation 10 is formed between the demarcation second guard ring 17 and the demarcation third guard ring 14. High density plasma chemical vapor deposition of silicon dioxide dielectric, high temperature annealing, chemical mechanical polishing to remove surface silicon dioxide dielectric, wet removal of silicon nitride and thick silicon dioxide to form oxide dielectric region 8, first shallow trench isolation 9 and second shallow trench isolation 10 as shown in fig. 6.
Step S104 is then performed: forming a gate electrode 11 using a thermal oxidation process and a vapor deposition process; the polysilicon of the gate 11 extends to the drift region 5 to cover the oxidation dielectric region 8, and the oxidation dielectric region 8 and the polysilicon covered on the oxidation dielectric region 8 together serve as a field plate.
As shown in fig. 7, in particular, in the embodiment of the present invention, thermal oxidation is performed on the initial substrate surface to form a thin oxide layer, and the oxide layer on the body region 6 is used as gate oxide. A layer of N-type heavily doped polysilicon is deposited by low-pressure chemical vapor deposition, photoresist is formed on the polysilicon, an etching window is formed by etching the photoresist, the polysilicon on the partial oxidation dielectric region 8, the polysilicon on the surface of the adjacent position of the body region 6 and the drift region 5 and the polysilicon on the surface of the second shallow trench isolation 10 are reserved by etching the polysilicon through the etching window. The polysilicon on the surface of the body region 6 adjacent to the drift region 5 and the gate oxide below form a gate 11, and the oxide dielectric region 8 and the polysilicon thereon form a field plate. Since the oxidation dielectric region 8 is formed in the initial substrate, the electric field of the transistor surface and the intermediate region can be dispersed, and breakdown of the device surface and the intermediate region can be prevented. The second shallow trench isolation 10 and the polysilicon guard structure 12 are able to disperse the surface electric field of the transistor thereat, preventing breakdown between the second guard ring 17 and the third guard ring 14. The transistor is able to withstand higher voltages without dielectric breakdown, enhancing the reliability of the transistor in high voltage applications.
Finally, step S105 is executed: the source electrode 15 and the drain electrode 16 are formed using an ion implantation process.
Further, the method further comprises: forming a first guard ring 13 heavily doped with ions of the first conductivity type at the body region 6 and proximate to the source electrode 15 by an ion implantation process; forming a second protection ring 17 with ion heavy doping of a second conductivity type on one side of the first well region 4 close to the drift region 5 by utilizing an ion implantation process; wherein the second conductivity type is different from the ion doping species of the first conductivity type; a third guard ring 14 heavily doped with ions of the first conductivity type is formed in the second well region 7 by an ion implantation process.
Specifically, referring to fig. 8, in the embodiment of the present invention, a thin silicon dioxide layer is thermally oxidized on the surface of an initial substrate to form a sacrificial oxide layer, then a photoresist layer is formed on the sacrificial oxide layer, the photoresist layer is exposed and developed to form an implantation window, N-type heavily doped ion implantation is performed on the initial substrate through the implantation window, a source electrode 15 is formed in the body region 6, a drain electrode 16 is formed in the drift region 5, and a second guard ring 17 is formed on the side of the first well region 4 close to the drift region 5. Removing the photoresist, then reforming the photoresist layer, exposing and developing the photoresist layer to form an injection window, performing P-type heavily doped ion injection on the body region 6 and the second well region 7 through the injection window, forming a first protection ring 13 with first conductive type ion heavy doping on one side of the body region 6 close to the source electrode 15, forming a third protection ring 14 with first conductive type ion heavy doping in the second well region 7, and performing voltage protection on the transverse double-diffusion field effect transistor. And (5) high-temperature annealing to remove the sacrificial oxide layer on the surface of the initial substrate. The implantation dosage of the N-type heavy doping ions is larger than that of the P-type heavy doping ions, and the implantation energy of the N-type heavy doping ions is smaller than that of the P-type heavy doping ions.
A third aspect of the invention provides a chip comprising a lateral double diffused field effect transistor as described above.
A fourth aspect of the invention provides a circuit comprising a lateral double diffused field effect transistor as described above.
The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the simple modifications belong to the protection scope of the present invention.
In addition, the specific features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described further.
Moreover, any combination of the various embodiments of the invention can be made without departing from the spirit of the invention, which should also be considered as disclosed herein.
Claims (17)
1. A lateral double-diffused field effect transistor comprising: the method is characterized in that the lateral double-diffusion field effect transistor further comprises the following steps:
The oxidation medium region is formed in the drift region and is covered by polysilicon extending out of the grid electrode, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together; wherein the oxidation medium region is manufactured by a shallow trench isolation process;
The oxidation isolation region is in a strip-shaped configuration, is formed at the junction of the body region and the drift region, and extends downwards from the middle region at the junction of the body region and the drift region to the first well region.
2. The lateral double-diffused field effect transistor of claim 1, wherein the oxide isolation region extends to a middle region of the first well region.
3. The lateral double-diffused field effect transistor of claim 1, wherein the body region has ion doping of the first conductivity type;
the lateral double-diffusion field effect transistor further includes:
and the second well region is formed on one side of the initial substrate far away from the body region and is provided with ion doping of the first conductivity type.
4. The lateral double-diffused field effect transistor of claim 3, the lateral double-diffusion field effect transistor is characterized by further comprising:
the first protection ring is formed in the body region and is close to the source electrode, and is heavily doped with ions of a first conductivity type;
The second protection ring is formed on one side of the first well region, close to the drift region, and is provided with ion heavy doping of a second conductivity type; wherein the second conductivity type is different from the ion doping species of the first conductivity type;
and the third protection ring is formed in the second well region and is provided with ion heavy doping of the first conductivity type.
5. The lateral double-diffused field effect transistor of claim 4, the lateral double-diffusion field effect transistor is characterized by further comprising:
And the first shallow groove isolation is formed between the drain electrode and the second protection ring.
6. The lateral double-diffused field effect transistor of claim 4, the lateral double-diffusion field effect transistor is characterized by further comprising:
a second shallow trench isolation formed between the second guard ring and the third guard ring;
and the polysilicon protection structure is formed on the second shallow slot isolation surface.
7. The lateral double-diffused field effect transistor of claim 6, the lateral double-diffusion field effect transistor is characterized by further comprising:
and the oxidation isolation structure is formed on one side of the initial substrate close to the first well region and extends downwards from the bottom of the second shallow trench isolation to the lower part of the first well region.
8. The lateral double-diffused field effect transistor of claim 7, wherein the oxide isolation structure comprises a plurality of spaced apart stripe-shaped oxide isolation strips.
9. A method of manufacturing a lateral double-diffused field effect transistor, the method comprising:
Forming an initial substrate, and forming an oxidation isolation region in the initial substrate, wherein the oxidation isolation region is in a strip-shaped configuration, is formed at the junction of the demarcation body region and the demarcation drift region, and extends downwards from the middle region at the junction of the demarcation body region and the demarcation drift region to the demarcation first well region;
forming a first well region, a body region and a drift region by utilizing an ion implantation process;
forming an oxidation medium region in the drift region by using a shallow trench isolation process;
Forming a grid electrode by utilizing a thermal oxidation process and a vapor deposition process; the polysilicon of the grid extends to the drift region to cover the oxidation medium region, and the oxidation medium region and the polysilicon covered on the oxidation medium region are used as a field plate together;
the source and drain electrodes are formed using an ion implantation process.
10. The method of manufacturing a lateral double-diffused field effect transistor according to claim 9, wherein forming an initial substrate and forming an oxide isolation region within the initial substrate comprises:
providing an original substrate, and forming an oxidation isolation region groove on the original substrate through an etching process;
filling the oxidation isolation region groove by using a chemical vapor deposition process to form the oxidation isolation region;
And bonding an external substrate on the surface of the original substrate, and taking the original substrate and the external substrate as the initial substrate.
11. The method of manufacturing a lateral double-diffused field effect transistor according to claim 9, wherein the body region has ion doping of the first conductivity type;
the method further comprises the steps of:
and forming a second well region doped with ions of the first conductivity type on one side of the initial substrate away from the body region by utilizing an ion implantation process.
12. The method of manufacturing a lateral double-diffused field effect transistor of claim 11, further comprising:
Forming a first protection ring heavily doped with ions of a first conductivity type at the body region and proximate to the source electrode by using an ion implantation process;
Forming a second protection ring with ion heavy doping of a second conductivity type on one side of the first well region, which is close to the drift region, by utilizing an ion implantation process; wherein the second conductivity type is different from the ion doping species of the first conductivity type;
And forming a third protection ring which is heavily doped with ions of the first conductivity type in the second well region by utilizing an ion implantation process.
13. The method of manufacturing a lateral double-diffused field effect transistor of claim 12, further comprising:
A first shallow trench isolation is formed between the drain and the second guard ring.
14. The method of manufacturing a lateral double-diffused field effect transistor of claim 13, further comprising:
Forming a second shallow trench isolation between the second guard ring and the third guard ring while forming the first shallow trench isolation;
And forming a polysilicon protection structure on the second shallow slot isolation surface.
15. The method of manufacturing a lateral double-diffused field effect transistor of claim 14, further comprising:
Forming an oxidation isolation structure at the same time of forming the oxidation isolation region; the oxidation isolation structure is formed on one side of the initial substrate close to the first well region, and extends downwards from the bottom of the second shallow trench isolation to the position below the first well region.
16. A chip comprising a lateral double diffused field effect transistor according to any one of claims 1 to 8.
17. A circuit comprising a lateral double diffused field effect transistor according to any of claims 1 to 8.
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| US7741661B2 (en) * | 2002-08-14 | 2010-06-22 | Advanced Analogic Technologies, Inc. | Isolation and termination structures for semiconductor die |
| US7635621B2 (en) * | 2002-11-22 | 2009-12-22 | Micrel, Inc. | Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Ron area product |
| KR20100079705A (en) * | 2008-12-31 | 2010-07-08 | 주식회사 동부하이텍 | Lateral double diffused metal oxide semiconductor device |
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