CN118262754B - Structure-assembled nonvolatile memory with single-side working mode and operation method thereof - Google Patents
Structure-assembled nonvolatile memory with single-side working mode and operation method thereof Download PDFInfo
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Abstract
The invention provides a pair-structure nonvolatile memory with a single-side working mode and an operation method thereof. In the pair-structure nonvolatile memory with the single-side working mode, a pair memory unit of a memory array comprises a first memory tube and a second memory tube, a first source-drain end of the first memory tube is connected with a first source-drain end of the second memory tube, a bit line is connected with a second source-drain end of a row of pair memory tubes of the pair memory unit, a second source-drain end of a row of pair memory tubes of the pair memory unit is connected with a source line, a word line is connected with a grid electrode of a row of second memory tube, and a control line is connected with a grid electrode of a row of first memory tube; wherein the first storage tube is fixed in a writing state. Thus, the circuit of the memory has low complexity, small chip area and high reliability of data storage. The invention also provides an erasing, writing and reading operation method of the structure nonvolatile memory of the single-side working mode.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a pair-structure nonvolatile memory with a single-side operation mode and an operation method thereof.
Background
Nonvolatile memory (NVM) is widely used in our daily life in various fields, including embedded systems, data storage products, and internet of things systems. The nonvolatile memory chip has advantages of high density, low price, electrically programmable and erasable, etc. As process technology nodes continue to shrink, the memory cell (cell) size of nonvolatile memory correspondingly shrinks. Because the memory cell needs to have better matching performance to the peripheral circuit, higher requirements are put on the performance, the integration level and the like of the memory array and the auxiliary circuit thereof.
As the process node continuously goes deep below 28nm, how to improve the reliability of the memory storage data under the condition of ensuring that the memory area can be continuously reduced is needed to be solved.
Disclosure of Invention
One of the purposes of the present invention is to provide a pair-structured nonvolatile memory with a single-sided operation mode, which has low complexity of the circuit, and is helpful for reducing the chip area, and the pair-structured nonvolatile memory with the single-sided operation mode eliminates the read interference from the structure, and is helpful for improving the reliability of the data stored in the memory. The invention also provides an erasing, writing and reading operation method of the structure nonvolatile memory of the single-side working mode.
In order to achieve the above object, a pairing structure nonvolatile memory of a unilateral operation mode provided by the present invention includes: the storage array comprises a plurality of group pair storage units which are arranged in rows and columns, wherein each group pair storage unit comprises a first storage tube and a second storage tube, and a first source-drain end of each first storage tube is connected with a first source-drain end of each second storage tube; a plurality of bit lines, one bit line is connected with the second source-drain ends of the second storage tubes of the group of memory cells; the second source drain ends of the first storage tubes of one row of the group-to-group storage units are connected with one source line; a plurality of word lines, one of which is connected to the gate of the second memory tube of the pair of memory cells; and a plurality of control lines, one of which is connected to the gate of the first memory tube of the pair of memory cells; the threshold voltage of the first storage tube is fixed in a set range, and the first storage tube is fixed in a writing state.
Optionally, the threshold voltage of the first storage tube is adjusted in a test stage of the structural nonvolatile memory in the group of the single-side working modes, so that the first storage tube is in a writing state.
Optionally, the extending direction of the source line and the extending direction of the bit line are perpendicular to each other.
Optionally, all memory tubes of the memory array are formed in the same well region.
Optionally, the first storage tube and the second storage tube are transistors with the same structure.
Optionally, the first memory tube and the second memory tube are transistors with the same conductivity type.
Optionally, the first storage tube and the second storage tube are both N-type transistors, and the threshold voltage of the first storage tube is kept positive; or the first storage tube and the second storage tube are P-type transistors, and the threshold voltage of the first storage tube is kept negative.
The invention also provides an erasing operation method of the nonvolatile memory with the structure of the pair of the unilateral working modes. The erasing operation method includes: applying a positive voltage to a well region where the memory array is located; applying a positive voltage to a control line connected to the memory cells for the group to be erased, and applying a negative voltage to a word line connected to the memory cells for the group to be erased; applying a positive voltage to both the control line and the word line connected to the memory cells of the group that does not need to be erased; applying a positive voltage to all bit lines; and applying a positive voltage to all source lines.
The invention also provides a writing operation method of the structure nonvolatile memory by the combination of the single-side working modes. The write operation method comprises the following steps: applying a first negative voltage to a well region where the memory array is located; applying a first negative voltage to control lines connected with the memory array, applying a first positive voltage to word lines connected with the memory cells of the group to be written, and applying a second negative voltage to word lines connected with the memory cells of the group not to be written, wherein the absolute value of the second negative voltage is smaller than that of the first negative voltage; applying a first negative voltage to bit lines connected with the memory cells of a group to be written, and applying a second positive voltage to the rest bit lines, wherein the second positive voltage is smaller than the first positive voltage; and applying a first negative voltage to all of the source lines.
The invention also provides a reading operation method of the nonvolatile memory with the structure of the pair of the unilateral working modes. The read operation method includes: applying a first voltage to a well region where the memory array is located; applying a second voltage to a word line connected to a second memory tube of the group pair memory cell to be read, and applying an opening positive voltage to a control line connected to a first memory tube of the group pair memory cell to be read, so that the first memory tube is opened; applying a first voltage to both a control line and a word line connected to the group of memory cells that do not need to be read; applying a read positive voltage to bit lines connected to the memory cells of the group to be read, and applying zero voltage or suspension to the rest bit lines; applying a first voltage to all of the source lines; the second voltage is set based on a threshold voltage distribution of the second storage tube writing state and a threshold voltage distribution of the second storage tube erasing state, and the first voltage and the second voltage are related and the difference value is in a set range.
In the group structure nonvolatile memory in the unilateral working mode, the memory array comprises a plurality of group memory cells arranged in rows and columns, each group memory cell comprises a first memory tube and a second memory tube, a first source-drain end of the first memory tube is connected with a first source-drain end of the second memory tube, a word line is connected with a grid electrode of the second memory tube of one row of group memory cells, a control line is connected with a grid electrode of the first memory tube of one row of group memory cells, a bit line is connected with a second source-drain end of the second memory tube of one row of group memory cells, and a second source-drain end of the first memory tube of one row of group memory cells is connected with one source line; the threshold voltage of the first storage tube is fixed in a set range, and the first storage tube is fixed in a writing state, namely the paired storage units are in a unilateral working mode. The configuration of bit lines and source lines in the nonvolatile memory with the single-side working mode is simple, and control signals are simpler when data operation is carried out on the memory array, so that the complexity of peripheral auxiliary circuits corresponding to the memory array is low, the occupied chip area is small, and the reduction of the chip area is facilitated; in addition, the combination of the single-side working modes can be used for fundamentally eliminating read interference from the structure of the nonvolatile memory, and is beneficial to improving the reliability of data storage of the memory.
Drawings
Fig. 1 is a circuit diagram of a pair-structure nonvolatile memory with a single-side operation mode according to an embodiment of the invention.
Fig. 2 is a schematic diagram illustrating a voltage application condition of the pair-structure nonvolatile memory in which the first memory tube is written in a page unit in a unilateral operation mode according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating a voltage application condition of the pair-structure nonvolatile memory in which the first memory tube is written in a sector unit in a unilateral operation mode according to an embodiment of the present invention.
FIG. 4 is a schematic diagram illustrating voltage application conditions of the pair of single-sided operation modes for performing a page erase operation on the structural nonvolatile memory according to an embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating a voltage application condition of a pair of single-sided operation modes for performing a sector erase operation on a structural nonvolatile memory according to an embodiment of the present invention.
FIG. 6 is a schematic diagram illustrating a voltage application condition of the pair of single-sided operation modes according to an embodiment of the invention when writing a structure of the nonvolatile memory.
FIG. 7 is a schematic diagram of voltage application conditions of the pair of single-sided operation modes according to an embodiment of the invention when the pair of single-sided operation modes is used for reading the structural nonvolatile memory.
Detailed Description
The following describes the set of unilateral operation modes of the present invention in further detail with reference to the drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a circuit diagram of a pair-structure nonvolatile memory with a single-side operation mode according to an embodiment of the invention. Referring to fig. 1, the pair-structure nonvolatile memory of the single-sided operation mode includes a memory array, a plurality of word lines WL, a plurality of control lines CL, a plurality of bit lines BL, and a plurality of source lines SL. The memory array comprises a plurality of group memory cells arranged in rows and columns, wherein each group memory cell comprises a first memory tube and a second memory tube, and a first source-drain end of the first memory tube is connected with a first source-drain end of the second memory tube; one bit line is connected with a second source-drain end of a second storage tube of a group of paired storage units; the second source-drain ends of the first storage tubes of the row of paired storage units are connected with a source line; one word line is connected with the grid electrode of the second storage tube of the row of the group-to-group storage units; one control line is connected with the grid electrode of the first storage tube of one row of paired storage units; the threshold voltage of the first storage tube is fixed in a set range, and the first storage tube is fixed in a writing state.
In this embodiment, all the memory tubes (including the first memory tube M1 and the second memory tube M2) of the memory array are formed in the same well region of the substrate. The well region is, for example, a P-well, but is not limited thereto.
In this embodiment, the first memory tube M1 and the second memory tube M2 are transistors with the same structure, so that the process integration is relatively simple, the number of layers of the photomask required to be increased for embedding the logic process is reduced, the production yield is improved, the chip cost is reduced, and the reliability is improved. The first memory tube M1 and the second memory tube M2 may be both charge trap type memory tubes or both floating gate type memory tubes.
In this embodiment, the first memory tube M1 and the second memory tube M2 are transistors with the same conductivity type. For example, the first memory tube M1 and the second memory tube M2 are both N-type transistors, or the first memory tube M1 and the second memory tube M2 are both P-type transistors.
For example, when the first memory tube M1 and the second memory tube M2 are both N-type transistors, the threshold voltage of the first memory tube M1 is kept positive, so that the first memory tube M1 is kept in a writing state; or when the first memory tube M1 and the second memory tube M2 are P-type transistors, the threshold voltage of the first memory tube M1 is kept negative, so that the first memory tube M1 is kept in a writing state.
Illustratively, referring to FIG. 1, the X-direction is the row direction of the memory array and the Y-direction is the column direction of the memory array, the row direction and the column direction being perpendicular to each other. Illustratively, the source line SL is elongated in the X direction and the bit line BL is elongated in the Y direction, with the source line extending in a direction perpendicular to the bit line extending in the Y direction.
In this embodiment, the pair-structured nonvolatile memory of the unilateral working mode may be applied to an embedded system, a data storage product, and an internet of things system, but is not limited thereto.
For example, the threshold voltage of the first memory tube M1 may be adjusted during the test phase of the pair of unilateral operation modes for the structural nonvolatile memory, so that the first memory tube M1 is in a writing state, and thus the threshold voltage (Vt) of the first memory tube M1 may be adjusted during the test, which increases the flexibility of the architecture.
For example, the first memory tube M1 of the memory array may be written to during the initial programming of the structural nonvolatile memory by the set of the single-sided operation modes, and the first memory tube M1 may be kept in a written state during the subsequent use of the memory.
When the first memory pipe M1 is programmed to the writing state, the first memory pipe M1 may be written in units of pages or the first memory pipe M1 may be written in units of sectors. Wherein, the first memory tube M1 connected with the same control line is one Page; the writing of the first memory tube M1 in units of sectors (sectors) is that the writing of the first memory tube M1 connected to a plurality of control lines is performed simultaneously.
Fig. 2 is a schematic diagram illustrating a voltage application condition of the pair-structure nonvolatile memory in which the first memory tube is written in a page unit in a unilateral operation mode according to an embodiment of the present invention. Referring to FIG. 2, during a write operation to the first memory tube M1 connected to the control line CL <1>, a first negative voltage Vp-is applied to the well region where the memory array is located, for example, a first negative voltage Vp-is applied to the P-well; a first positive voltage vp+ is applied to a control line CL <1> connected to the first memory tube M1 to be written, and a first negative voltage Vp-is applied to the remaining control lines CL <0>, CL <2> and CL <3 >; applying a first negative voltage Vp-to a word line WL <1> connected to a second memory tube M2 of the first memory tube M1 group pair to be written, and applying a third negative voltage Vp-3 to the remaining word lines WL <0>, WL <2> and WL <3 >; the first negative voltage Vp-is applied to all bit lines BL and all source lines SL. Wherein the absolute value of the third negative voltage Vp-3 is smaller than or equal to the absolute value of the first negative voltage Vp-.
Fig. 3 is a schematic diagram illustrating a voltage application condition of the pair-structure nonvolatile memory in which the first memory tube is written in a sector unit in a unilateral operation mode according to an embodiment of the present invention. Referring to FIG. 3, when writing operation is performed on the first memory tube M1 of the whole sector, a first negative voltage Vp-is applied to the well region where the memory array is located, for example, a first negative voltage Vp-is applied to the P-well; applying a first positive voltage vp+ to all control lines CL; applying a third negative voltage Vp-3 to all word lines WL; the first negative voltage Vp-is applied to all bit lines BL and all source lines SL. Wherein the absolute value of the third negative voltage Vp-3 is smaller than or equal to the absolute value of the first negative voltage Vp-.
In this embodiment, when the pair of unilateral operation modes performs erasing, writing and reading operations on the structural nonvolatile memory, the threshold voltage of the first storage tube is fixed within a set range, and the first storage tube is fixed in a writing state; and when erasing, writing and reading operations are performed, only the second storage tube is subjected to erasing, writing or reading operations, namely, only one side of the group pair storage unit is subjected to data operation.
The application provides an erasing operation method of a nonvolatile memory with a unilateral working mode. The erasing operation method of the structure nonvolatile memory of the group of the unilateral working modes comprises the following steps: applying a positive voltage to a well region where the memory array is located; applying a positive voltage to a control line connected to the memory cells for the group to be erased, and applying a negative voltage to a word line connected to the memory cells for the group to be erased; applying a positive voltage to both the control line and the word line connected to the memory cells of the group that does not need to be erased; applying a positive voltage to all bit lines; and applying a positive voltage to all source lines.
FIG. 4 is a schematic diagram illustrating voltage application conditions of the pair of single-sided operation modes for performing a page erase operation on the structural nonvolatile memory according to an embodiment of the present invention. For example, referring to fig. 4, taking the group pair memory cells in the dashed line frame as the group pair memory cells to be erased and the second memory tube M2 in the dashed line frame as the memory tube to be erased, when the row of the second memory tubes M2 connected with the word line WL <1> is the page to be erased, a positive voltage ve+ is applied to the well region where the memory array is located, for example, a positive voltage ve+ is applied to the P-well during the erase operation; applying a positive voltage ve+ to a control line CL <1> connected to a first memory tube M1 of a group pair memory cell to be erased, and applying a negative voltage Ve-to a word line WL <1> connected to a second memory tube M2 of the group pair memory cell to be erased; the positive voltage ve+ is applied to all of the control lines CL <0>, CL <2>, and CL <3> connected to the group pair memory cells that do not need to be erased, and the positive voltage ve+ is applied to the word lines WL <0>, WL <2>, and WL <3> connected to the group pair memory cells that do not need to be erased; applying a positive voltage ve+ to all bit lines BL; a positive voltage ve+ is applied to all the source lines SL.
FIG. 5 is a schematic diagram illustrating a voltage application condition of a pair of single-sided operation modes for performing a sector erase operation on a structural nonvolatile memory according to an embodiment of the present invention. Referring to fig. 5, when the sector erase operation is performed on the pair-structured nonvolatile memory in the single-sided operation mode, all the second memory tubes M2 of the memory array are erased, specifically, a positive voltage ve+ is applied to the well region where the memory array is located, for example, a positive voltage ve+ is applied to the P-well; applying a positive voltage ve+ to all control lines CL connected to the memory array, and applying a negative voltage Ve-to word lines WL <0>, WL <1>, WL <2> and WL <3> connected to all second memory tubes M2 of the memory array; applying a positive voltage ve+ to all bit lines BL; a positive voltage ve+ is applied to all the source lines SL.
The application provides a write operation method of a pair-structure nonvolatile memory in a unilateral working mode. The writing operation method of the structure nonvolatile memory of the group of the single-side working modes comprises the following steps: applying a first negative voltage to a well region where the memory array is located; applying a first negative voltage to control lines connected with the memory array, applying a first positive voltage to word lines connected with the memory cells of the group to be written, and applying a second negative voltage to word lines connected with the memory cells of the group not to be written, wherein the absolute value of the second negative voltage is smaller than that of the first negative voltage; applying a first negative voltage to bit lines connected with the memory cells of a group to be written, and applying a second positive voltage to the rest bit lines, wherein the second positive voltage is smaller than the first positive voltage; and applying a first negative voltage to all of the source lines.
FIG. 6 is a schematic diagram illustrating a voltage application condition of the pair of single-sided operation modes according to an embodiment of the invention when writing a structure of the nonvolatile memory. For example, referring to fig. 6, taking a group in a dashed line frame as a group to memory cell to be written, and taking a second memory tube M2 in the dashed line frame as a memory tube to be written, when writing, applying a first negative voltage Vp-to a well region where the memory array is located, for example, applying a first negative voltage Vp-to a P-well, applying a first negative voltage Vp-to control lines CL <0>, CL <1>, CL <2> and CL <3> connected to the first memory tube M1 in the memory array, applying a first positive voltage vp+ to word lines WL <1> connected to a second memory tube M2 of the memory cell to be written, applying a first positive voltage vp+ to word lines WL <0>, WL <2> and WL <3> connected to the second memory tube M2 of the memory cell to be not to be written, applying a second negative voltage Vp-2, wherein an absolute value of the second negative voltage Vp-2 is smaller than an absolute value of the first negative voltage Vp-to control lines CL <0>, CL <1>, CL <2> and CL <3> connected to the bit lines BL <0>, and applying a first positive voltage vp+vp 2 to the remaining bit lines vp+2; the first negative voltage Vp-is applied to all source lines SL.
The application provides a method for reading a structure nonvolatile memory by a pair of unilateral working modes. The method for reading the structure nonvolatile memory by the group of the single-side working modes comprises the following steps: a first voltage is applied to a well region where the memory array is located; applying a second voltage to a word line connected to a second memory tube of the group pair memory cell to be read, and applying an opening positive voltage to a control line connected to a first memory tube of the group pair memory cell to be read, so that the first memory tube is opened; applying a first voltage to both a control line and a word line connected to the group of memory cells that do not need to be read; applying a read positive voltage to bit lines connected to the memory cells of the group to be read, and applying zero voltage or suspension to the rest bit lines; applying a first voltage to all of the source lines; the second voltage is set based on the threshold voltage of the writing state of the second storage tube and the threshold voltage of the erasing state of the second storage tube, and the first voltage and the second voltage are related and the difference value is in a set range.
FIG. 7 is a schematic diagram of voltage application conditions of the pair of single-sided operation modes according to an embodiment of the invention when the pair of single-sided operation modes is used for reading the structural nonvolatile memory. For example, referring to fig. 7, taking a group pair memory cell in a dashed line frame as a group pair memory cell to be read, and a second memory tube M2 in the dashed line frame as a memory tube to be read as an example, when a read operation is performed, a first voltage Vpw is applied to a well region where the memory array is located, for example, a first voltage Vpw is applied to a P-well; applying a second voltage Vmg to a word line WL <1> connected to a second memory tube M2 of the group-pair memory cell to be read, and applying an on positive voltage Vsg for opening the first memory tube M1 to a control line CL <1> connected to a first memory tube M1 of the group-pair memory cell to be read; the first voltage Vpw is applied to all of control lines CL <0>, CL <2> and CL <3> connected to the memory cells of the group which do not need to be read, and the first voltage Vpw is applied to all of word lines WL <0>, WL <2> and WL <3> connected to the memory cells of the group which do not need to be read; applying a read positive voltage Vread to bit lines BL <0> connected to memory cells of a group to be read, and applying zero volt voltage or floating (Float) to the remaining bit lines; the first voltage Vpw is applied to all the source lines SL. The second voltage Vmg is set based on a threshold voltage distribution of the writing state of the second memory tube M2 and a threshold voltage distribution of the erasing state of the second memory tube M2, and the first voltage Vpw and the second voltage Vmg are related and have a difference value within a set range.
The second voltage Vmg is a voltage between the threshold voltage distribution of the second memory tube M2 in the written state and the threshold voltage distribution of the second memory tube M2 in the erased state, and preferably, the second voltage Vmg is a voltage at a middle line of the threshold voltage distribution of the second memory tube M2 in the written state and the threshold voltage distribution of the second memory tube M2 in the erased state. The second voltage Vmg and the first voltage Vpw are equal, for example, 0V, the on positive voltage Vsg is, for example, 2V to 2.5V, and the read voltage Vread is 0.5V, but the range of values of the voltages is not limited thereto.
It should be noted that, the above-mentioned method for erasing, writing and reading the structure nonvolatile memory by the group of unilateral operation modes is described by taking the first memory tube and the second memory tube as N-type transistors as an example, if the first memory tube and the second memory tube are P-type transistors, the erasing, writing and reading operation methods are similar, but the applied voltage electrical property and the applied voltage size can be adaptively adjusted.
In the group structure nonvolatile memory in the unilateral working mode, the memory array comprises a plurality of group memory cells arranged in rows and columns, each group memory cell comprises a first memory tube M1 and a second memory tube M2, a first source-drain end of the first memory tube M1 is connected with a first source-drain end of the second memory tube M2, a word line WL is connected with a grid electrode of the second memory tube M2 of a row of group memory cells, a control line CL is connected with a grid electrode of the first memory tube of a row of group memory cells, a bit line BL is connected with a second source-drain end of the second memory tube M2 of a column of group memory cells, and a second source-drain end of the first memory tube M1 of a row of group memory cells is connected with a source line; the threshold voltage of the first memory tube M1 is fixed within a set range, and the first memory tube M1 is fixed in a writing state, i.e. the paired memory cells are in a unilateral working mode. The configuration of bit lines and source lines in the nonvolatile memory with the single-side working mode is simple, and control signals are simpler when data operation is carried out on the memory array, so that the complexity of peripheral auxiliary circuits corresponding to the memory array is low, the occupied chip area is small, and the reduction of the chip area is facilitated; in addition, the combination of the unilateral working modes can eliminate read interference of the structural nonvolatile memory from the structure, thereby being beneficial to improving the reliability of data stored in the memory; the nonvolatile memory with the structure composed of the unilateral working modes can also solve the problem of IP design of embedded NOR Flash caused by deep process nodes below 28 nm.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
1. A pair-wise structured nonvolatile memory for a single-sided operating mode, comprising:
The storage array comprises a plurality of group pair storage units which are arranged in rows and columns, wherein each group pair storage unit comprises a first storage tube and a second storage tube, and a first source-drain end of each first storage tube is connected with a first source-drain end of each second storage tube;
A plurality of bit lines, one bit line is connected with the second source-drain ends of the second storage tubes of the group of memory cells;
The second source drain ends of the first storage tubes of one row of the group-to-group storage units are connected with one source line;
A plurality of word lines, one of which is connected to the gate of the second memory tube of the pair of memory cells; and
A plurality of control lines, one of which is connected with the grid electrode of the first storage tube of one row of the group-to-group storage units;
the threshold voltage of the first storage tube is fixed in a set range, and the first storage tube is fixed in a writing state.
2. The one-sided operation mode pair-structure nonvolatile memory of claim 1 wherein the threshold voltage of the first memory tube is adjusted during a test phase of the one-sided operation mode pair-structure nonvolatile memory to make the first memory tube a write state.
3. The paired structure nonvolatile memory of claim 1 wherein the source line and the bit line extend in directions perpendicular to each other.
4. The paired structure nonvolatile memory of claim 1 wherein all of the memory tubes of the memory array are formed in the same well region.
5. The paired structure nonvolatile memory of claim 1 wherein the first memory tube and the second memory tube are identical transistors.
6. The paired structure nonvolatile memory of claim 1 wherein the first memory tube and the second memory tube are transistors of the same conductivity type.
7. The paired structure nonvolatile memory of claim 1 wherein the first memory tube and the second memory tube are both N-type transistors, the threshold voltage of the first memory tube being held positive; or the first storage tube and the second storage tube are P-type transistors, and the threshold voltage of the first storage tube is kept negative.
8. A method of erasing a structured nonvolatile memory of a group of single-sided operation modes as claimed in any one of claims 1 to 6, comprising:
Applying a positive voltage to a well region where the memory array is located;
applying a positive voltage to a control line connected to the memory cells for the group to be erased, and applying a negative voltage to a word line connected to the memory cells for the group to be erased; applying a positive voltage to both the control line and the word line connected to the memory cells of the group that does not need to be erased;
Applying a positive voltage to all bit lines; and
A positive voltage is applied to all source lines.
9. A method of writing a set of unilateral modes of operation to a structural nonvolatile memory as claimed in any one of claims 1 to 6 comprising:
applying a first negative voltage to a well region where the memory array is located;
Applying a first negative voltage to control lines connected with the memory array, applying a first positive voltage to word lines connected with the memory cells of the group to be written, and applying a second negative voltage to word lines connected with the memory cells of the group not to be written, wherein the absolute value of the second negative voltage is smaller than that of the first negative voltage;
applying a first negative voltage to bit lines connected with the memory cells of a group to be written, and applying a second positive voltage to the rest bit lines, wherein the second positive voltage is smaller than the first positive voltage; and
A first negative voltage is applied to all source lines.
10. A method of reading a pair-wise structured nonvolatile memory in a single-sided operating mode as claimed in any one of claims 1 to 6, comprising:
applying a first voltage to a well region where the memory array is located;
applying a second voltage to a word line connected to a second memory tube of the group pair memory cell to be read, and applying an opening positive voltage to a control line connected to a first memory tube of the group pair memory cell to be read, so that the first memory tube is opened; applying a first voltage to both a control line and a word line connected to the group of memory cells that do not need to be read;
Applying a read positive voltage to bit lines connected to the memory cells of the group to be read, and applying zero voltage or suspension to the rest bit lines; and
Applying a first voltage to all of the source lines;
The second voltage is set based on a threshold voltage distribution of the second storage tube writing state and a threshold voltage distribution of the second storage tube erasing state, and the first voltage and the second voltage are related and the difference value is in a set range.
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| CN114171091A (en) * | 2022-02-14 | 2022-03-11 | 杭州领开半导体技术有限公司 | Data reading method for paired structure nonvolatile memory array |
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| JP4038823B2 (en) * | 1995-08-31 | 2008-01-30 | 株式会社ルネサステクノロジ | Semiconductor nonvolatile memory device and computer system using the same |
| JP4601316B2 (en) * | 2004-03-31 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | Nonvolatile semiconductor memory device |
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| CN115394331B (en) * | 2022-10-31 | 2023-03-24 | 杭州领开半导体技术有限公司 | Local bit line selection circuit and operation method of group-to-structure nonvolatile memory |
| CN116665738B (en) * | 2023-07-25 | 2023-10-20 | 上海领耐半导体技术有限公司 | 3D nonvolatile memory of pairing structure |
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