CN118248567A - Method for manufacturing semiconductor structure and semiconductor structure - Google Patents
Method for manufacturing semiconductor structure and semiconductor structure Download PDFInfo
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- CN118248567A CN118248567A CN202211665671.0A CN202211665671A CN118248567A CN 118248567 A CN118248567 A CN 118248567A CN 202211665671 A CN202211665671 A CN 202211665671A CN 118248567 A CN118248567 A CN 118248567A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 55
- 239000004020 conductor Substances 0.000 claims description 43
- 238000005520 cutting process Methods 0.000 claims description 19
- 239000003292 glue Substances 0.000 claims description 12
- 238000005507 spraying Methods 0.000 claims description 9
- 238000007650 screen-printing Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 69
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000010949 copper Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: mounting a plurality of chips on a carrier plate, wherein adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface and a chip side surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface; forming insulating film layers on the side surfaces of the chips, wherein a gap exists between two insulating film layers between two adjacent chips; forming a conductive structure, wherein the conductive structure comprises a first conductive part positioned at the side part of each chip and a second conductive part positioned at the back of each chip, and the first conductive part is positioned outside the insulating film layer positioned at the side part of each chip; the second conductive part at least covers part of the second pole, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, the surface of the control electrode, and the surface of the first electrode are on the same plane.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
Some existing chips, such as direct contact field effect transistors, have their source and gate on the front side of the chip and drain on the back side of the chip. As shown in fig. 14, when the chip 10 'is connected to the circuit board 30', the drain electrode 13 'is usually led to the front surface of the chip 10' by using the copper case 20', and the bottom wall 21' of the copper case 20 'is electrically connected to the drain electrode 13' of the chip 10 'through the conductive paste 40'. The side wall 22 'of the copper shell 20' extends to the front side of the chip 10 'to lead the drain electrode 13' of the chip 10 'to the front side of the chip 10', the side wall 22 'of the copper shell 20' is far away from the surface of the back of the chip 10', the source electrode 12' of the chip 10 'is far away from the conductive ball 51' arranged on the back of the chip 10', and the conductive ball 52' arranged on the surface of the grid electrode 11 'of the chip 10' far away from the back of the chip 10 'are respectively electrically connected with the circuit board, namely the electric connection between the chip and the circuit board 30' is realized
By adopting the scheme, the problems of inclination of the copper shell shown in fig. 15, inclination of the chip shown in fig. 16, deformation of the copper shell, excessive use of conductive adhesive shown in fig. 17 or insufficient use of conductive adhesive shown in fig. 18 can occur, so that the yield of products is low and the yield of connection between the chip and the circuit board is low.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of a semiconductor structure. The manufacturing method comprises the following steps:
Mounting a plurality of chips on a carrier plate, wherein adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface;
Forming an insulating film layer on the side surface of each chip, wherein a gap exists between two insulating film layers between two adjacent chips;
forming a conductive structure, wherein the conductive structure comprises a first conductive part positioned at the side part of each chip and a second conductive part positioned at the back of each chip, and the first conductive part is outside an insulating film layer positioned at the side part of each chip; the second conductive part at least covers part of the second pole, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
In one embodiment, the forming an insulating film layer on the side surface of each chip, and a gap exists between two insulating film layers between two adjacent chips, includes:
and spraying insulating glue on the side surfaces of the chips by adopting a spraying process to form an insulating film layer.
In one embodiment, the forming an insulating film layer on the side surface of each chip, and a gap exists between two insulating film layers between two adjacent chips, includes:
Filling insulating glue in a gap between two adjacent chips to form an insulating part;
And forming a through groove penetrating through the insulating parts on each insulating part, and forming an insulating film layer on the part of the insulating parts between the through groove and the chip.
In one embodiment, the forming the conductive structure includes:
Arranging conductive materials on the back surface of each chip and at least one side of each chip to obtain second conductive parts positioned on the back surface of each chip and obtain conductive blocks positioned between at least two adjacent chips;
and cutting the conductive block to form two first conductive parts which are arranged at intervals.
In one embodiment, the disposing a conductive material on the back surface of each of the chips and at least one side of each of the chips to obtain a second conductive portion located on the back surface of each of the chips, and to obtain a conductive block located at least between two adjacent chips, includes:
Respectively arranging conductive materials on the back surface of each chip and at least two sides of each chip to obtain a second conductive part positioned on the back surface of each chip, a conductive block positioned between two adjacent chips and a first conductive part positioned on the outer side of each chip in the edge area of the carrier plate;
Cutting the conductive block to form two first conductive parts which are arranged at intervals, and then obtaining a plurality of semiconductor structures; in the semiconductor structure, the first conductive portions are formed on at least two sides of each chip.
In one embodiment, the disposing a conductive material on the back side of each of the chips and on at least one side of each of the chips includes:
A sputtering process is adopted to set conductive materials on the back surface of each chip and at least one side of each chip; or alternatively
A dispensing process is adopted to set conductive materials on the back surface of each chip and at least one side of each chip; or alternatively
Setting conductive materials on the back surfaces of the chips and at least one side of the chips by adopting a screen printing process; or alternatively
And setting conductive materials on at least one side of each chip by adopting a dispensing process, and setting conductive materials on the back of each chip by adopting a screen printing process.
In one embodiment, the method further includes, after providing a conductive material on the back surface of each of the chips and at least one side of each of the chips to obtain a second conductive portion located on the back surface of each of the chips and to obtain a conductive block located at least between two adjacent chips, and before cutting the conductive block to form two first conductive portions located at intervals, the method further includes:
Removing the carrier plate to obtain a semiconductor intermediate structure;
forming a plurality of conductive balls on one side, away from the back surface of the chip, of the semiconductor intermediate structure by adopting a ball implantation process, wherein the control electrode and the first electrode are respectively and electrically connected with at least one conductive ball; the conductive block is electrically connected with at least two conductive balls;
after the conductive blocks are cut to form two first conductive parts which are arranged at intervals, each first conductive part is electrically connected with at least one conductive ball.
In one embodiment, the second conductive portion covers the entire area of the back surface of the chip, or the second conductive portion covers a partial area of the back surface of the chip.
In one embodiment, the first electrode is a source electrode and the second electrode is a drain electrode.
The embodiment of the application also provides a semiconductor structure, which comprises:
The chip comprises a front surface, a back surface opposite to the front surface of the chip, and a plurality of side surfaces connecting the front surface of the chip and the back surface of the chip, wherein the chip comprises a control electrode and a first electrode which are arranged on the front surface of the chip, and a second electrode which is arranged on the back surface of the chip;
The insulating film layer is positioned on at least one side of the chip, and the insulating film layer is made of insulating glue;
The conductive structure comprises a first conductive part positioned at the side part of the chip and a second conductive part positioned at the back of the chip, and the first conductive part is positioned outside the insulating film layer positioned at the side part of the chip; the second conductive part at least covers part of the second pole, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
In one embodiment, the semiconductor structure further includes a plurality of conductive balls located on a front side of the chip, and the first conductive portion, the control electrode, and the first electrode are electrically connected to at least one of the conductive balls, respectively.
The embodiment of the application achieves the main technical effects that:
According to the manufacturing method of the semiconductor structure and the semiconductor structure, the second conductive part positioned on the back surface of the chip and the first conductive part positioned on the side part of the chip are arranged, and the second electrode is electrically connected with the first conductive part through the second conductive part, so that the second electrode can be led to the front surface of the chip through the second conductive part and the first conductive part; the surface of the first conductive part, the surface of the control electrode, and the surface of the first electrode are on the same plane, so that the semiconductor structure is connected with the circuit board. According to the manufacturing method of the semiconductor structure and the semiconductor structure, provided by the embodiment of the application, the chip is attached to the carrier plate in the manufacturing process, the chip is not easy to incline, the copper shell and the conductive adhesive for electrically connecting the chip and the copper shell are not needed, the problem of low product yield caused by the inclination of the chip, the inclination of the copper shell and the uncomfortable consumption of the conductive adhesive can be avoided, and the connection yield of the semiconductor structure and the circuit board can be ensured; the gap exists between the two insulating film layers between the two adjacent chips, namely, only one through groove exists between the two adjacent chips, compared with the scheme of forming the two through grooves between the two adjacent chips, the process for forming the insulating film layers can be simplified, and the simplification of a manufacturing method is facilitated.
Drawings
Fig. 1 is a flow chart of a method of fabricating a semiconductor structure according to an exemplary embodiment of the present application;
FIG. 2 is a partial cross-sectional view of a wafer provided in accordance with an exemplary embodiment of the present application;
FIG. 3 is a cross-sectional view of a chip provided in an exemplary embodiment of the application;
FIG. 4 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;
FIG. 5 is a partial cross-sectional view of a second intermediate structure provided in an exemplary embodiment of the application;
FIG. 6 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;
FIG. 7 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;
FIG. 8 is a partial cross-sectional view of a fourth intermediate structure provided by another exemplary embodiment of the present application;
Fig. 9 is a cross-sectional view of a semiconductor structure provided in an exemplary embodiment of the present application;
Fig. 10 is a cross-sectional view of a semiconductor structure provided in another exemplary embodiment of the present application;
FIG. 11 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;
Fig. 12 is a cross-sectional view of a semiconductor structure provided by yet another exemplary embodiment of the present application;
Fig. 13 is a cross-sectional view of a semiconductor structure provided by yet another exemplary embodiment of the present application;
Fig. 14 is a schematic structural diagram of a chip provided by the application, which is obtained by connecting a copper shell with a circuit board;
FIG. 15 is a schematic view of the structure of FIG. 14 showing the problem of copper shell tilting;
FIG. 16 is a schematic diagram of a structure in which a chip tilt problem occurs in the structure shown in FIG. 14;
FIG. 17 is a schematic diagram of the structure of FIG. 14 showing the problem of excessive amounts of conductive paste;
fig. 18 is a schematic diagram of the structure shown in fig. 14, in which the problem of too little conductive paste is present.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.
Some embodiments of the application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
The embodiment of the application provides a manufacturing method of a semiconductor structure. Referring to fig. 1, the method for manufacturing the semiconductor structure includes the following steps 110 to 130.
In step 110, a plurality of chips are mounted on a carrier plate, and adjacent chips are arranged at intervals; the chip comprises a front surface, a back surface opposite to the front surface of the chip, and a plurality of side surfaces connecting the front surface of the chip and the back surface of the chip, wherein the chip comprises a control electrode and a first electrode which are arranged on the front surface of the chip, and a second electrode which is arranged on the back surface of the chip.
In step 120, an insulating film layer is formed on the side surface of each chip, and a gap exists between two insulating film layers between two adjacent chips.
In step 130, a conductive structure is formed, where the conductive structure includes a first conductive portion located at a side portion of each chip and a second conductive portion located at a back surface of each chip, and the first conductive portion is outside an insulating film layer located at a side portion of the chip; the second conductive part at least covers part of the second pole, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
According to the manufacturing method of the semiconductor structure, the second conductive part positioned on the back surface of the chip and the first conductive part positioned on the side part of the chip are arranged, and the second electrode is electrically connected with the first conductive part through the second conductive part, so that the second electrode can be led to the front surface of the chip through the second conductive part and the first conductive part; the surface of the first conductive part, the surface of the control electrode, and the surface of the first electrode are on the same plane, so that the semiconductor structure is connected with the circuit board. According to the manufacturing method of the semiconductor structure, the chip is mounted on the carrier plate in the manufacturing process, the chip is not easy to incline, the copper shell and the conductive adhesive for electrically connecting the chip and the copper shell are not needed, the problem of low product yield caused by the inclination of the chip, the inclination of the copper shell and the discomfort of the consumption of the conductive adhesive can be avoided, and the connection yield of the semiconductor structure and the circuit board can be ensured; the gap exists between the two insulating film layers between the two adjacent chips, namely, only one through groove exists between the two adjacent chips, compared with the scheme of forming the two through grooves between the two adjacent chips, the process for forming the insulating film layers can be simplified, and the simplification of a manufacturing method is facilitated.
The following describes each step of the method for manufacturing a semiconductor structure according to the embodiment of the present application in detail.
In step 110, a plurality of chips are mounted on a carrier plate, and adjacent chips are arranged at intervals; the chip comprises a chip front surface, a back surface opposite to the chip front surface, and a plurality of side surfaces connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface.
In one embodiment, the chip may be manufactured by the following process:
First, a wafer is provided. Referring to fig. 2, wafer 14 has a front side and a back side opposite the front side. The front surface of the wafer 14 is provided with a control electrode 11 and a first electrode 12, and the control electrode 11 and the first electrode 12 are arranged at intervals. The back side of the wafer is provided with a second pole 13.
In one embodiment, a rewiring structure may be formed on the front side of the wafer, the rewiring structure including a rewiring layer on the front side of the wafer and a conductive post on a side of the rewiring layer facing away from the wafer. The rewiring layer includes a plurality of leads, each of the control electrode 11 and the first electrode 12 being electrically connected to one of the leads, each of the leads being electrically connected to one of the conductive posts. Thus, by providing the rewiring structure, the distance between the control electrode 11 and the first electrode 12 can be increased, so that the subsequent chip can be connected with the circuit board conveniently.
Further, after the rewiring structure is formed, an insulating material layer covering the rewiring layer and the side surfaces of the conductive posts can be formed, and the surfaces of the conductive posts facing away from the wafer are flush with the surfaces of the insulating material layer facing away from the wafer. The layer of insulating material may include a rewiring structure.
Subsequently, the wafer 14 is diced. The wafer 14 may be diced along the positions of the dashed lines shown in fig. 2. The wafer 14 may be cut by mechanical dicing or by laser dicing. Through this step, the chip 10 shown in fig. 3 can be obtained. The front, side and back surfaces of the chip are all part of the surface of the chip. The chip 10 shown in fig. 4 is cube-shaped, the chip 10 comprising four sides.
In the embodiment of the application, if the front surface of the wafer is not formed with the rewiring structure, the control electrode and the first electrode of the wafer are the control electrode and the first electrode of the finally obtained chip. If the front side of the wafer has a rewiring structure formed thereon, the control electrode of the chip in the embodiment of the application may be considered as a conductive post electrically connected to the control electrode of the wafer, and the first electrode of the chip may be considered as a conductive post electrically connected to the control electrode of the wafer.
In one embodiment, the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode.
In one embodiment, the carrier plate 20 may be circular, rectangular, or other shape. The carrier 20 may be a small-sized wafer substrate or a larger-sized carrier, such as a stainless steel plate substrate, a polymer substrate, or the like.
A first intermediate structure as shown in fig. 4 may be obtained by step 110. The chip 10 may be attached to the carrier 20 by an adhesive layer. The adhesive layer may be of a readily peelable material for subsequent peeling of the carrier plate, for example, the adhesive layer may be of a thermally releasable material which is rendered tacky by heating.
In step 120, an insulating film layer is formed on the side surface of each chip, and a gap exists between two insulating film layers between two adjacent chips.
By this step a second intermediate structure as shown in fig. 5 is obtained. As shown in fig. 5, a gap exists between two insulating film layers 30 located between two adjacent chips 10, and there is no other structure between the two insulating film layers 30. That is, only one through groove 301 is provided between two adjacent chips 10, and the through groove 301 penetrates the insulating film layer 30 in the thickness direction of the insulating film layer 30.
In one embodiment, the step 120 of forming an insulating film layer on the side surface of each chip, where a gap exists between two insulating film layers between two adjacent chips includes the following steps:
and spraying insulating glue on the side surfaces of the chips by adopting a spraying process to form an insulating film layer.
By spraying the insulating glue on the side surface of the chip to form the insulating film layer by adopting a spraying process, the thickness of the insulating film layer can be controlled to be thinner by controlling the amount of the sprayed insulating glue, and further, two insulating film layers formed between two adjacent chips 10 cannot be connected together, namely, a gap exists between the two insulating film layers formed between the two adjacent chips 10. It is known that the formation process of the insulating film layer can be simplified by forming the insulating film layer by a spray coating process without performing other process treatments such as cutting on the insulating film layer.
In another embodiment, the step 120 of forming an insulating film layer on a side surface of each chip, where a gap exists between two insulating film layers between two adjacent chips includes the following steps:
First, an insulating adhesive is filled in a gap between two adjacent chips to form an insulating portion.
In this step, an insulating paste may be filled in the gap between the adjacent two chips 10 using a paste dispensing process. When the precision of the dispensing process is higher, the formation of insulating glue on the back surface of the chip can be avoided. If the precision of the dispensing process is low, a patterned release film can be arranged on the back of the chip before the dispensing process, and the release film is removed after the dispensing process is finished, so that the formation of insulating glue on the back of the chip is avoided.
Then, a through groove penetrating through the insulating parts is formed in each insulating part, and an insulating film layer is formed on the part, located between the through groove and the chip, of the insulating part.
Wherein the through groove penetrates the insulating part, which means that the through groove penetrates the insulating part in the thickness direction of the insulating part.
In one embodiment, the step of forming a through slot in each insulating portion, which penetrates through the insulating portion, includes the following steps: and cutting the insulating parts, and forming one through groove penetrating through the insulating parts on each insulating part. When the insulating part is cut, the middle part of the insulating part is cut off, the parts on the two sides are reserved, and each of the reserved two parts forms an insulating film layer. That is, two insulating film layers can be formed between two adjacent chips by performing a dicing process, which contributes to simplification of the process. In other embodiments, a laser process may be used to form the via on the insulating portion.
In one embodiment, before the step 120 of forming the insulating film layer on the side of each of the chips, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the chips 10 and the carrier 20, so that the insulating film layer 30 can be more closely connected to the chips 10 and the carrier 20, without delamination or cracking.
In step 130, a conductive structure is formed, where the conductive structure includes a first conductive portion located at a side portion of each chip and a second conductive portion located at a back surface of each chip, and the first conductive portion is outside an insulating film layer located at a side portion of the chip; the second conductive part at least covers part of the drain electrode, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
A third intermediate structure as shown in fig. 6 is obtained by step 130. As shown in fig. 6, the conductive structure 40 includes a first conductive portion 41 located at a side of the chip 10 and a second conductive portion 42 located at a back surface of each chip, and the second conductive portion 42 is connected to the first conductive portion 41. The second pole 13 of the chip 10 is led to the front side of the chip through the second conductive portion 42 and the first conductive portion 41 in this order. The material of the first conductive portion 41 may be the same as or different from the material of the second conductive portion 42.
In one embodiment, the step 130 of forming the conductive structure includes the following processes:
first, a conductive material is disposed on the back surface of each chip and at least one side of each chip, so as to obtain a second conductive portion located on the back surface of each chip, and a conductive block located at least between two adjacent chips.
Subsequently, the conductive block is cut to form two first conductive parts which are arranged at intervals.
In one embodiment, the step of providing a conductive material on the back surface of each of the chips and at least one side of each of the chips to obtain a second conductive portion located on the back surface of each of the chips, and to obtain a conductive block located at least between two adjacent chips includes the following steps: and respectively arranging conductive materials on the back surface of each chip and at least two sides of each chip to obtain a second conductive part positioned on the back surface of each chip, a conductive block positioned between two adjacent chips and a first conductive part positioned on the outer side of the chip in the edge region of the carrier plate. Wherein the outside of the chip refers to the side of the chip away from other chips, and no other chips are arranged outside the chip.
By this step a fourth intermediate structure as shown in fig. 7 or 8 can be obtained. As shown in fig. 7 and 8, a first conductive portion 41 is formed on the outer side of the chip 10 located in the edge region of the carrier; a conductive block 43 is formed between any two adjacent chips 10; the second conductive portions 42 are formed on the back surface of each chip. Thus, after the step of cutting the conductive blocks, at least two sides of each of the chips 10 are respectively formed with one first conductive portion 41. After the step of cutting the conductive block to form two first conductive parts which are arranged at intervals, a plurality of semiconductor structures are obtained; in the semiconductor structure, the first conductive portions 41 are formed on at least two sides of each of the chips 10, respectively. Even if one of the first conductive portions 41 and the second electrode 13 are not good in electrical connection, the other first conductive portions 41 and the second electrode 13 are electrically connected, so that the second electrode 13 can be guaranteed to be led to the front surface of the chip, and the reliability of the semiconductor structure can be improved. In some embodiments, one of the first conductive portions is provided on each of opposite sides of the chip 10. In other embodiments, some of the chips 10 may be provided with the first conductive portions 41 on only one side, or all sides of the chips 10 may be provided with the first conductive portions 41.
By cutting the conductive block, two objectives can be achieved: cutting the same conductive block into two first conductive portions 41; and dicing the semiconductor intermediate structure into a plurality of semiconductor structures. That is, by providing a gap between two insulating film layers between two adjacent chips, that is, by forming only one through groove 301 between two adjacent chips, the number of cutting times in the manufacturing process of the semiconductor structure can be reduced, which contributes to simplification of the manufacturing process.
After dicing the conductive blocks of the fourth intermediate structure shown in fig. 7 or 8, a semiconductor structure as shown in fig. 9 can be obtained. In the fourth intermediate structure shown in fig. 7 or fig. 8, the second conductive portion 42 located on the back surface of the chip covers a part of the area on the back surface of the chip, and in the semiconductor structure shown in fig. 9, the second conductive portion 42 covers a part of the area on the back surface of the chip; and the second conductive portion 42 includes two sub-conductive portions 421 disposed at intervals, and each sub-conductive portion 421 is in contact with one of the first conductive portions 41.
In another embodiment, the second conductive portion 42 covers a part of the area of the back surface of the chip, and then the resulting semiconductor structure is shown in fig. 10, where the second conductive portion 42 covers the whole area of the back surface of the chip, and the second conductive portion 42 is electrically connected to the two first conductive portions 41, respectively.
In one embodiment, before the step of cutting the conductive block, the carrier plate may be removed to obtain a semiconductor intermediate structure. And cutting the conductive block of the semiconductor intermediate structure to obtain the semiconductor structure. In another embodiment, the step of cutting the conductive block may be performed before removing the carrier, that is, the conductive block is cut to obtain a plurality of semiconductor structures, and then the semiconductor structures are separated from the carrier.
In one embodiment, the step of disposing a conductive material on the back surface of each of the chips and on at least one side of each of the chips includes the following steps: and setting conductive materials on at least one side of each chip and the back of each chip by adopting a sputtering process.
After a sputtering process is used to provide a conductive material on at least one side of each of the chips and on the back of each of the chips, a fourth intermediate structure as shown in fig. 7 is obtained. As shown in fig. 7, the conductive block 43 formed between two insulating film layers located between adjacent chips 10 does not entirely fill the gap between the two insulating film layers. The conductive block is more easily cut into two first conductive portions 41 at the time of cutting the conductive block later.
In another embodiment, the step of disposing a conductive material on the back surface of each of the chips and at least one side of each of the chips includes the following steps: and setting conductive materials on at least one side of each chip and the back of each chip by adopting a dispensing process.
In this embodiment, a dispensing process may be used to inject a conductive material into the gap between adjacent chips 10 to form the conductive bump 43, and to coat the conductive material on the outside of the chip located in the edge region of the carrier to form the first conductive portion 41, and then a dispensing process may be used to coat the conductive material on the back of the chip to form the second conductive portion 42. By this step a fourth intermediate structure as shown in fig. 8 is obtained. As shown in fig. 8, the conductive block 43 formed of two insulating film layers located between adjacent chips 10 fills the gap between the two insulating film layers entirely.
In yet another embodiment, the step of disposing a conductive material on the back side of each of the chips and on at least one side of each of the chips comprises the steps of: and arranging conductive materials on at least one side of each chip and the back of each chip by adopting a screen printing process.
In this embodiment, a screen printing process is used to print a conductive material to the gaps between adjacent chips to form the conductive bumps 43, and print a conductive material on the outside of the chip located in the edge region of the carrier to form the first conductive portions 41, and then print a conductive material on the back of the chip to form the second conductive portions 42.
In yet another embodiment, the step of providing the conductive material on the back surface of each of the chips and on at least one side of each of the chips comprises the following steps: and setting conductive materials on at least one side of each chip by adopting a dispensing process, and setting conductive materials on the back of each chip by adopting a screen printing process.
In this embodiment, a conductive material is injected into the gap between adjacent chips 10 by a dispensing process to form the conductive bump 43, and the conductive material is coated on the outer side of the chip located at the edge region of the carrier to form the first conductive portion 41, and then a screen printing process is used to print the conductive material on the back surface of the chip to form the second conductive portion 42.
In one embodiment, in the process of performing step 130, the step of providing a conductive material on the back surface of each chip and at least one side of the chip to obtain a second conductive portion located on the back surface of each chip, and obtaining a conductive block located at least between two adjacent chips, and before the step of cutting the conductive block to form two first conductive portions located at intervals, the manufacturing method further includes the following steps:
firstly, removing the carrier plate to obtain the semiconductor intermediate structure.
Then, forming a plurality of conductive balls on one side, away from the back surface of the chip, of the semiconductor intermediate structure by adopting a ball implantation process, wherein the control electrode and the first electrode are respectively and electrically connected with at least one conductive ball; the conductive block is electrically connected with at least two conductive balls.
A fifth intermediate structure as shown in fig. 11 can be obtained by the above steps. As shown in fig. 11, a plurality of conductive balls 50 are formed on the side of the semiconductor intermediate structure facing away from the back surface of the chip. The first conductive portion 41 is connected to one conductive ball 50, the control electrode 11 and the first electrode 12 are connected to two conductive balls 50, respectively, and the conductive block 43 is connected to two conductive balls 50.
After the step of cutting the conductive block to form two first conductive portions disposed at intervals, each of the first conductive portions 41 is electrically connected to at least one of the conductive balls 50 in the obtained semiconductor structure.
After dicing the conductive bumps, a plurality of semiconductor structures as shown in fig. 12 are obtained. As shown in fig. 12, the first conductive portion 41 is connected to one conductive ball 50, and the control electrode 11 and the first electrode 12 are connected to two conductive balls 50, respectively. The control electrode 11, the first electrode 12 and the first conductive portion 41 of the semiconductor structure can be soldered on the circuit board through the conductive balls 50, so as to facilitate connection of the semiconductor structure and the circuit board. The material of the conductive balls 50 may be metallic tin.
In the fifth intermediate structure shown in fig. 11, the second conductive portion 42 covers a part of the area on the back surface of the chip, and in the semiconductor structure shown in fig. 12 obtained by cutting the fifth intermediate structure shown in fig. 11, the second conductive portion 42 covers a part of the area on the back surface of the chip, and the second conductive portion 42 includes two sub-conductive portions 421 disposed at intervals, each sub-conductive portion 421 being in contact with one of the first conductive portions 41. When the second conductive portion 42 covers the entire area of the back surface of the chip, the semiconductor structure shown in fig. 13 is finally obtained.
The embodiment of the application also provides a semiconductor structure. As shown in fig. 9, 10, 12 and 13, the semiconductor structure includes a chip 10, an insulating film layer 30 located on at least one side of the chip 10, and a conductive structure 40. The chip 10 includes a front surface, a back surface opposite to the front surface of the chip, and a plurality of side surfaces connecting the front surface of the chip and the back surface of the chip, and the chip 10 includes a control electrode 11 and a first electrode 12 provided on the front surface, and a second electrode 13 provided on the back surface. The insulating film layer 30 is made of insulating glue. The conductive structure 40 includes a first conductive portion 41 located on a side of the insulating film 30 away from the chips 10, and a second conductive portion 42 located on a back surface of each of the chips 10, where the second conductive portion 42 covers at least a portion of the second pole 13, and the first conductive portion 41 is connected to the second conductive portion 42 on the back surface. The surface of the first conductive part 41 facing away from the back surface of the chip, the surface of the control electrode 11 facing away from the back surface of the chip, and the surface of the first electrode 12 facing away from the back surface of the chip are on the same plane.
In one embodiment, at least two sides of the chip 10 are respectively provided with a first conductive portion 41, and the second conductive portion 42 located on the back of the chip is respectively connected to at least two first conductive portions 41.
In one embodiment, as shown in fig. 12 and 13, the semiconductor structure further includes a plurality of conductive balls 50 located on the front side of the chip, and the first conductive portion 41, the control electrode 11, and the first electrode 12 are electrically connected to at least one of the conductive balls 50, respectively.
In one embodiment, the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode.
Embodiments of the method for manufacturing a semiconductor structure provided in the embodiments of the present application and embodiments of the semiconductor structure belong to the same inventive concept, and descriptions of related details and beneficial effects may be referred to each other, and are not repeated here.
It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (11)
1. A method of manufacturing a semiconductor structure, the method comprising:
Mounting a plurality of chips on a carrier plate, wherein adjacent chips are arranged at intervals; the chip comprises a chip front surface, a chip back surface opposite to the chip front surface, and a plurality of chip side surfaces connecting the chip front surface and the chip back surface, wherein the chip comprises a control electrode and a first electrode which are arranged on the chip front surface, and a second electrode which is arranged on the chip back surface;
Forming an insulating film layer on the side surface of each chip, wherein a gap exists between two insulating film layers between two adjacent chips;
forming a conductive structure, wherein the conductive structure comprises a first conductive part positioned at the side part of each chip and a second conductive part positioned at the back of each chip, and the first conductive part is outside an insulating film layer positioned at the side part of each chip; the second conductive part at least covers part of the second pole, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein forming an insulating film layer on a side surface of each of the chips with a gap between two of the insulating film layers between two adjacent chips, comprises:
and spraying insulating glue on the side surfaces of the chips by adopting a spraying process to form an insulating film layer.
3. The method of manufacturing a semiconductor structure according to claim 1, wherein forming an insulating film layer on a side surface of each of the chips with a gap between two of the insulating film layers between two adjacent chips, comprises:
Filling insulating glue in a gap between two adjacent chips to form an insulating part;
And forming a through groove penetrating through the insulating parts on each insulating part, and forming an insulating film layer on the part of the insulating parts between the through groove and the chip.
4. The method of manufacturing a semiconductor structure of claim 1, wherein forming a conductive structure comprises:
Arranging conductive materials on the back surface of each chip and at least one side of each chip to obtain second conductive parts positioned on the back surface of each chip and obtain conductive blocks positioned between at least two adjacent chips;
and cutting the conductive block to form two first conductive parts which are arranged at intervals.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein providing a conductive material on a back surface of each of the chips and at least one side of each of the chips to obtain a second conductive portion located on the back surface of each of the chips, and to obtain a conductive block located at least between two adjacent chips, comprises:
Respectively arranging conductive materials on the back surface of each chip and at least two sides of each chip to obtain a second conductive part positioned on the back surface of each chip, a conductive block positioned between two adjacent chips and a first conductive part positioned on the outer side of each chip in the edge area of the carrier plate;
Cutting the conductive block to form two first conductive parts which are arranged at intervals, and then obtaining a plurality of semiconductor structures; in the semiconductor structure, the first conductive portions are formed on at least two sides of each chip.
6. The method of manufacturing a semiconductor structure according to claim 4, wherein providing a conductive material on a back surface of each of the chips and at least one side of each of the chips comprises:
A sputtering process is adopted to set conductive materials on the back surface of each chip and at least one side of each chip; or alternatively
A dispensing process is adopted to set conductive materials on the back surface of each chip and at least one side of each chip; or alternatively
Setting conductive materials on the back surfaces of the chips and at least one side of the chips by adopting a screen printing process; or alternatively
And setting conductive materials on at least one side of each chip by adopting a dispensing process, and setting conductive materials on the back of each chip by adopting a screen printing process.
7. The method of manufacturing a semiconductor structure according to claim 4, wherein the providing of the conductive material on the back surface of each of the chips and at least one side of each of the chips results in a second conductive portion located on the back surface of each of the chips, and the manufacturing method further comprises, after obtaining the conductive bumps located at least between two adjacent chips and before the dicing the conductive bumps to form two first conductive portions located at intervals:
Removing the carrier plate to obtain a semiconductor intermediate structure;
forming a plurality of conductive balls on one side, away from the back surface of the chip, of the semiconductor intermediate structure by adopting a ball implantation process, wherein the control electrode and the first electrode are respectively and electrically connected with at least one conductive ball; the conductive block is electrically connected with at least two conductive balls;
after the conductive blocks are cut to form two first conductive parts which are arranged at intervals, each first conductive part is electrically connected with at least one conductive ball.
8. The method of manufacturing a semiconductor structure according to claim 1, wherein the second conductive portion covers an entire area of the back surface of the chip or a partial area of the back surface of the chip.
9. The method of claim 1, wherein the first electrode is a source electrode and the second electrode is a drain electrode.
10. A semiconductor structure, the semiconductor structure comprising:
The chip comprises a front surface, a back surface opposite to the front surface of the chip, and a plurality of side surfaces connecting the front surface of the chip and the back surface of the chip, wherein the chip comprises a control electrode and a first electrode which are arranged on the front surface of the chip, and a second electrode which is arranged on the back surface of the chip;
The insulating film layer is positioned on at least one side of the chip, and the insulating film layer is made of insulating glue;
The conductive structure comprises a first conductive part positioned at the side part of the chip and a second conductive part positioned at the back of the chip, and the first conductive part is positioned outside the insulating film layer positioned at the side part of the chip; the second conductive part at least covers part of the second pole, and the first conductive part positioned at the side part of the chip is connected with the second conductive part positioned at the back surface of the chip; the surface of the first conductive part, which is away from the back surface of the chip, the surface of the control electrode, which is away from the back surface of the chip, and the surface of the first electrode, which is away from the back surface of the chip, are on the same plane.
11. The semiconductor structure of claim 10, further comprising a plurality of conductive balls on a front side of the die, the first conductive portion, the control electrode, and the first electrode each being electrically connected to at least one of the conductive balls.
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| CN1855469A (en) * | 2002-04-23 | 2006-11-01 | 三洋电机株式会社 | Semiconductor device and method of manufacturing same |
| CN101465301A (en) * | 2007-12-21 | 2009-06-24 | 万国半导体股份有限公司 | Wafer level chip scale packaging |
| CN102122670A (en) * | 2011-01-31 | 2011-07-13 | 江阴长电先进封装有限公司 | Groove-interconnected wafer level MOSFET encapsulation structure and implementation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1855469A (en) * | 2002-04-23 | 2006-11-01 | 三洋电机株式会社 | Semiconductor device and method of manufacturing same |
| CN101465301A (en) * | 2007-12-21 | 2009-06-24 | 万国半导体股份有限公司 | Wafer level chip scale packaging |
| CN102122670A (en) * | 2011-01-31 | 2011-07-13 | 江阴长电先进封装有限公司 | Groove-interconnected wafer level MOSFET encapsulation structure and implementation method |
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