CN118231431A - Image sensor and manufacturing method thereof - Google Patents

Abstract

The invention discloses an image sensor and a manufacturing method thereof, which belong to the technical field of semiconductors, wherein the image sensor comprises: a substrate; photoelectric device the sensing area is provided with a sensing area, is disposed in the substrate; and a carrier-suppressing layer disposed in the substrate, and the carrier-suppressing layer covering a portion or all of the photo-sensing region and/or a portion of the storage node; the carrier inhibition layer comprises a first substance and a second substance, wherein the first substance is combined with a dangling bond in the substrate to form a chemical bond, and the second substance inhibits the outward diffusion of the first substance. The image sensor and the manufacturing method thereof can improve the electrical property of the image sensor.

Description

Image sensor and manufacturing method thereof

Technical Field

The present invention belongs to the field of semiconductor technology, and in particular relates to an image sensor and a manufacturing method thereof.

Background technique

The exposure modes of complementary metal oxide semiconductor (CMOS) image sensors include rolling exposure mode and global exposure mode. The characteristic of rolling exposure mode image sensors is that the exposure time of each row of a frame image is different, and the exposure time of the previous row is earlier than that of the next row. In the global exposure mode, each row of the entire image is exposed at the same time, and then the charge signal is transmitted and stored in the storage node of the pixel unit at the same time, and finally the signal of the storage node is read out row by row.

In image sensors, ions are injected into the substrate to form photoelectric sensing areas or storage nodes. Carriers are easily generated on the silicon surface that is not covered by the gate on the surface of the photoelectric sensing area or storage node, which leads to a decrease in the performance of the image sensor. If different types of doping regions are used to suppress carrier generation, electron residues will be generated between the photoelectric sensing area and other doping regions, further affecting the performance of the image sensor.

Summary of the invention

The object of the present invention is to provide an image sensor and a method for manufacturing the same, which can solve the problem of carrier overflow between different doping regions, thereby improving the performance of the image sensor.

To solve the above technical problems, the present invention is achieved through the following technical solutions:

The present invention provides an image sensor, comprising:

substrate;

A photoelectric sensing region is disposed in the substrate; and

A carrier suppression layer is disposed in the substrate, and the carrier suppression layer covers part or all of the photoelectric sensing area and/or covers part of the storage node;

The carrier suppression layer includes a first substance and a second substance. The first substance combines with dangling bonds in the substrate to form chemical bonds, and the second substance suppresses the first substance from diffusing outward.

In one embodiment of the present invention, the first substance includes fluorine, chlorine, bromine, iodine or hydrogen.

In one embodiment of the present invention, the second substance includes carbon or tin.

In one embodiment of the present invention, the image sensor further includes:

A storage node, wherein the storage node is disposed in the substrate and is located at one side of the photoelectric sensing region;

A first gate is disposed on the substrate, the first gate is located between the photoelectric sensing region and the storage node, and an orthographic projection of the first gate on the substrate covers a portion of the photoelectric sensing region and a portion of the storage node;

The second gate is arranged on the substrate, the second gate is located at a side of the storage node away from the photoelectric sensing region, and the orthographic projection of the second gate on the substrate is aligned with or overlaps the storage node.

In one embodiment of the present invention, the carrier suppression layer covers the storage node between the first gate and the second gate, and one edge of the carrier suppression layer overlaps with the edge of the storage node, and the other edge of the carrier suppression layer is aligned with or overlaps with the first edge.

In an embodiment of the present invention, the image sensor further includes an isolation layer, which is disposed in the substrate and covers the photoelectric sensing region on one side of the first gate.

In one embodiment of the present invention, the carrier suppression layer covers the storage node between the first gate and the second gate, and the photoelectric sensing region on one side of the first gate.

In one embodiment of the present invention, the image sensor further includes a second gate disposed on the substrate, the second gate being located on one side of the photoelectric sensing area, and an orthographic projection of the second gate on the substrate covering a portion of the photoelectric sensing area and a portion of the substrate close to the photoelectric sensing area.

In one embodiment of the present invention, the carrier suppression layer covers the entire photoelectric sensing region, and the edge of the isolation layer extends out of the photoelectric sensing region.

In one embodiment of the present invention, the carrier suppression layer covers a portion of the photoelectric sensing region, and the carrier suppression layer is located on a side close to the second gate.

In an embodiment of the present invention, the image sensor further includes an isolation layer, wherein the isolation layer is disposed in the photoelectric sensing region, and the isolation layer covers the photoelectric sensing region at a side away from the second gate.

The present invention also provides a method for manufacturing an image sensor, comprising the following steps:

providing a substrate;

forming a photoelectric sensing region in the substrate;

Forming a carrier suppression layer in the substrate, wherein the carrier suppression layer covers part or all of the photoelectric sensing area and/or covers part of the storage node;

The carrier suppression layer includes a first substance and a second substance. The first substance combines with dangling bonds in the substrate to form chemical bonds, and the second substance suppresses the first substance from diffusing outward.

In one embodiment of the present invention, before forming the carrier suppression layer, the method for manufacturing the image sensor further includes:

forming an isolation well in the substrate;

forming a gate on the substrate; and

Sidewall spacers are formed on both sides of the gate.

In summary, the present invention provides an image sensor and a method for manufacturing the same, which forms a carrier suppression layer on a photoelectric sensing region or a storage node to suppress the generation of carriers on the silicon surface without causing electron retention, thereby improving the performance of the image sensor.

Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned advantages at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of a structure for forming a photoelectric sensing region and a storage node in one embodiment.

FIG. 2 is a schematic diagram of a structure for forming an isolation well in one embodiment.

FIG. 3 is a schematic diagram of a structure for forming a gate in an embodiment.

FIG. 4 is a schematic diagram of a structure for forming a side wall in an embodiment.

FIG. 5 is a schematic diagram of a structure for forming a carrier suppression layer in one embodiment.

FIG. 6 is a schematic diagram of a structure in which an isolation layer is formed in one embodiment.

FIG. 7 is a schematic diagram of a structure for forming a floating diffusion region in one embodiment.

FIG. 8 is a schematic diagram of a structure for forming a carrier suppression layer in another embodiment.

FIG. 9 is a schematic diagram of a structure for forming a floating diffusion region in another embodiment.

FIG. 10 is a schematic diagram showing a structure of forming a photoelectric sensing region in yet another embodiment.

FIG. 11 is a schematic diagram of a structure for forming an isolation well in yet another embodiment.

FIG. 12 is a schematic diagram of a structure for forming a gate in yet another embodiment.

FIG. 13 is a schematic diagram of a structure for forming a side wall in yet another embodiment.

FIG. 14 is a schematic diagram showing a structure of forming a carrier suppression layer in yet another embodiment.

FIG. 15 is a schematic diagram of a structure for forming a floating diffusion region in yet another embodiment.

FIG. 16 is a schematic diagram of a structure for forming a carrier suppression layer in yet another embodiment.

FIG. 17 is a schematic diagram of a structure for forming an isolation layer and a floating diffusion region in yet another embodiment.

Detailed ways

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

Image sensors can be divided into two types according to the exposure mode: rolling shutter exposure mode and global shutter exposure mode. Image sensors with rolling shutter exposure mode are generally used in mobile phone cameras, digital cameras, and home security equipment. The characteristic of image sensors with rolling shutter exposure mode is that the exposure time of each row of a frame is different, and the exposure time of the previous row is earlier than that of the next row. The obtained image is not a true reflection of the photographed object at a certain moment. Therefore, when shooting high-speed moving objects, the image is prone to smearing. Image sensors with global exposure mode are widely used in the fields of industry, vehicle-mounted, road monitoring, and high-speed cameras. In the global exposure mode, each row of the entire image is exposed at the same time, and then the charge signal is simultaneously transmitted and stored in the storage node of the pixel unit, and finally the signal of the storage node is read out row by row. Since all rows of the entire image are exposed at the same time in the global exposure mode, there will be no smearing.

Please refer to FIG. 7, FIG. 9, FIG. 15 and FIG. 17. The present application provides an image sensor provided with a pixel array. The pixel array is the pixel area of the image sensor. The image sensor is also provided with a logic area other than the pixel area. The logic area can process the electrical signal output by the pixel array. Among them, the pixel array includes a plurality of pixel units, and each pixel unit includes a photodiode (PD) and a plurality of transistors. Each photodiode forms a pixel point. The scene is focused on the pixel array of the image sensor through an imaging lens. The photodiode can convert the surface light intensity into an electrical signal, and through the cooperation of a plurality of transistors, control the light conversion of the photodiode, and control the storage and output of the electrical signal. In the global exposure mode image sensor, in order to transfer the charge in the photodiode, a transmission tube and a transfer tube are provided. Among them. The transmission tube is arranged between the photoelectric sensing area 102 and the storage node 103, and can control the charge in the photoelectric sensing area 102 to be transferred to the storage node 103. The transfer tube is arranged between the storage node 103 and the floating diffusion area 111 to control the reset and charge transfer of the storage node 103. The photoelectric sensing region 102 can form a photodiode. In the rolling exposure mode image sensor, the storage node 103 is not provided, so only a transfer transistor is provided between the photoelectric sensing region 102 and the floating diffusion region 111 to control the transfer of charges in the photoelectric sensing region 102 .

Please refer to Figures 7 and 9. In one embodiment of the present invention, the image sensor is a global exposure mode image sensor, which includes a substrate 100, a photoelectric sensing region 102 and a storage node 103 arranged in the substrate 100, an isolation well arranged on the photoelectric sensing region 102 and the storage node 103, a transfer tube arranged on the substrate 100 and located between the photoelectric sensing region 102 and the storage node 103, a transfer tube arranged on a side of the storage node 103 away from the photoelectric sensing region 102, and a carrier suppression layer 109 arranged in the photoelectric sensing region 102 and the storage node 103.

Please refer to FIG. 1 . In one embodiment of the present invention, the substrate 100 may be any applicable semiconductor material, such as silicon, silicon germanium on insulator, silicon on insulator, silicon germanium on insulator, silicon germanium on insulator, or a stacked structure composed of these semiconductors. In this embodiment, the substrate 100 is made of single crystal silicon doped with impurities, and can be formed by implanting ions into the silicon substrate 100. The doping type of the impurities in the substrate 100 is set according to the type of semiconductor to be formed. In this embodiment, the substrate 100 is, for example, a P-type substrate, and a P-type substrate can be formed by doping trivalent ions such as boron in the silicon substrate. In other embodiments, the substrate 100 may also be an N-type substrate, and an N-type substrate can be formed by doping pentavalent ions such as phosphorus in the silicon substrate.

Referring to FIG. 1 , in one embodiment of the present invention, an oxide layer 101 is provided on a substrate 100. The oxide layer 101 can be used as a gate oxide layer or as a buffer layer during ion implantation. In the present application, the oxide layer 101 can be formed on the substrate 100 by a thermal oxidation method or an in-situ water vapor growth method.

Please refer to FIG. 1 . In one embodiment of the present invention, a photoelectric sensing region 102 and a storage node 103 are provided in a substrate 100. The photoelectric sensing region 102 and the storage node 103 are first-type doped regions. The doping type of the first-type doped region is opposite to the doping type of the substrate 100. In this embodiment, the first-type doped region is an N-type doped region, and is an N-type lightly doped region. In the present application, after forming the oxide layer 101, the oxide layer 101 can be used as an ion implantation buffer layer, and N-type impurities such as phosphorus (P) or arsenic (As) can be implanted into the substrate 100 to form the photoelectric sensing region 102 and the storage node 103.

Referring to FIG. 1 , in one embodiment of the present invention, the photoelectric sensing region 102 and the storage node 103 are arranged side by side in the substrate 100, and there is a preset distance between the photoelectric sensing region 102 and the storage node 103. In the growth direction of the image sensor, one side of the photoelectric sensing region 102 and the storage node 103 is in contact with the surface of the substrate 100, and the other side of the photoelectric sensing region 102 and the storage node 103 extends toward the bottom of the substrate 100. In this embodiment, the depth of the photoelectric sensing region 102 is greater than the depth of the storage node 103. When forming the photoelectric sensing region 102 and the storage node 103, the depth of the photoelectric sensing region 102 and the storage node 103 can be controlled by controlling the injection energy during ion implantation.

Please refer to FIG. 2 . In one embodiment of the present invention, an isolation well is further provided in the substrate 100. In the present application, the isolation well includes a first isolation well 104 located on the surface of the photoelectric sensing region 102, and a second isolation well 105 located on the surface of the storage node 103. The depths of the first isolation well 104 and the second isolation well 105 may be the same or different. The isolation well is a second type doping region, and the doping type of the second type doping region is the same as the doping type of the substrate 100. In the present embodiment, the second type doping region is a P-type doping region. In the present application, P-type impurities such as boron (B) are injected into the substrate 100 to form an isolation well.

Please refer to FIG. 2 , in one embodiment of the present invention, the first isolation well 104 is located on the surface of the photoelectric sensing region 102, the depth of the first isolation well 104 is much smaller than the depth of the photoelectric sensing region 102, and the width of the first isolation well 104 is equal to the width of the photoelectric sensing region 102. The first isolation well 104 is a P-type doped region, and the impurity concentration in the first isolation well 104 is slightly higher than the impurity concentration in the photoelectric sensing region 102. By setting the first isolation well 104 with a higher doping concentration, the photoelectric sensing region 102 is prevented from expanding toward the surface of the substrate 100, thereby reducing the dark current caused by dangling bonds on the surface of the substrate 100.

Referring to FIG. 2 , in one embodiment of the present invention, the second isolation well 105 is located on the surface of the storage node 103, and the depth of the second isolation well 105 is much smaller than the depth of the storage node 103, and the width of the second isolation well 105 is equal to the width of the storage node 103. The second isolation well 105 is a P-type doped region, and the impurity concentration in the second isolation well 105 is slightly higher than the impurity concentration in the storage node 103. The second isolation well 105 with different doping types disposed on the storage node 103 does not affect electron transfer while reducing dark current.

Please refer to FIG. 3 . In one embodiment of the present invention, a plurality of gates are further provided on the substrate 100 , including a first gate 106 forming a transmission tube and a second gate 107 forming a transfer tube. Among them, the gates of other transistors in the pixel, such as the reset tube, the source follower and the row selection tube, can also be formed simultaneously. In the present application, a gate material layer (not shown in the figure) can be formed on the oxide layer 101 , and the gate material layer can be a material such as polysilicon or a metal material. The polysilicon can be a heavily doped polysilicon layer, and the metal material can be magnesium, aluminum, nickel, copper, gold, silver, TiAl-based alloy, titanium carbide, tantalum carbide or tungsten silicide, etc., or an alloy of several materials. After the gate material layer is formed, a patterned photoresist layer (not shown in the figure) is formed on the gate material layer, and the patterned photoresist layer is used as a mask, for example, the gate material layer is etched by dry etching to form a plurality of gates.

3 , in one embodiment of the present invention, the first gate 106 is located between the photoelectric sensing region 102 and the storage node 103, and the orthographic projection of the first gate 106 on the substrate 100 covers a portion of the photoelectric sensing region 102 and a portion of the storage node 103. The second gate 107 is disposed on a side of the storage node 103 away from the photoelectric sensing region 102, and the orthographic projection of the second gate 107 on the substrate 100 is aligned with or overlaps the storage node 103.

Please refer to FIG. 4 . In one embodiment of the present invention, sidewalls 108 are further provided on both sides of the gate. In one embodiment of the present invention, the sidewalls 108 are provided on both sides of the first gate 106 and the second gate 107. The sidewalls 108 may be silicon oxide sidewalls, silicon nitride sidewalls, or silicon oxide and silicon nitride stacked on the sidewalls. When forming the sidewalls 108, a material layer may be first deposited on the gate, and the material layer may be an oxide layer, a nitride layer, or an oxide layer and a nitride layer stacked. Afterwards, the material layer is etched, and only the material layer on the sidewalls of the first gate 106 and the second gate 107 is retained to form the sidewalls 108.

Referring to FIGS. 5 to 9 , in some embodiments of the present invention, a carrier suppression layer 109 is further provided in the storage node 103 and/or the photoelectric sensing region 102. One side of the carrier suppression layer 109 is in contact with the surface of the substrate 100, and the depth of the carrier suppression layer 109 is equal to the depth of the first isolation well 104 or the second isolation well 105. Specifically, when forming the carrier suppression layer 109, the first substance and the second substance can be simultaneously injected into the substrate 100, wherein the first substance can be combined with the dangling bonds in the substrate 100 to form a chemical bond. The second substance can inhibit the first substance from diffusing outward. The first substance can be a VIIA group element such as fluorine, chlorine, bromine and iodine, as well as hydrogen. The second substance can be a substance of the same group as silicon, for example, including carbon and tin. In a specific embodiment, the first substance is, for example, fluorine, and the second substance is, for example, carbon, then the first substance is combined with the dangling bonds in the substrate 100 to form a Si-F chemical bond. The second substance is, for example, carbon. After the first substance and the second substance are implanted, in the subsequent annealing process, the carbon can inhibit the diffusion of fluorine.

Referring to FIG. 5 , in one embodiment of the present invention, the carrier suppression layer 109 covers the storage node 103 between the first gate 106 and the second gate 107, and the depth of the carrier suppression layer 109 is equal to the depth of the second isolation well 105. One edge of the carrier suppression layer 109 overlaps with the edge of the storage node 103, and extends toward the bottom of the second gate 107 at the same time as the storage node 103, and is aligned with or overlapped with the edge of the second gate 107. The other edge of the carrier suppression layer 109 extends toward the bottom of the first gate 106, and is aligned with or overlapped with the edge of the first gate 106. At this time, the second isolation well 105 and the carrier suppression layer 109 in the storage node 103 are arranged side by side, and the second isolation well 105 is located at the bottom of the first gate 106. When forming the carrier suppression layer 109, due to the shielding of the sidewall 108, the carrier suppression layer 109 can be extended toward the bottom of the first gate 106 and the second gate 107 by adjusting the angle of ion implantation. The carrier suppression layer 109 formed in the storage node 103 can suppress the generation of carriers on the silicon surface between the first gate 106 and the second gate 107, and no potential barrier will be generated between the storage node 103 and the floating diffusion area 111, thereby avoiding the generation of residual electrons.

Please refer to FIG. 6 . In one embodiment of the present invention, when the carrier suppression layer 109 only covers the storage node 103 between the first gate 106 and the second gate 107, an isolation layer 110 is further provided in the photoelectric sensing region 102. The isolation layer 110 is located in the substrate 100, one side of the isolation layer 110 is in contact with the surface of the substrate 100, and the depth of the isolation layer 110 is equal to the depth of the first isolation well 104. Specifically, the isolation layer 110 is a second type doping region. In this embodiment, the second type doping region is a P-type doping region. When forming the isolation layer 110, the isolation layer 110 can be formed by injecting P-type impurities such as boron (B) into the second isolation well 105.

Please refer to FIG. 6 , in one embodiment of the present invention, the isolation layer 110 covers the photoelectric sensing region 102 on one side of the first gate 106, and one edge of the isolation layer 110 coincides with the edge of the photoelectric sensing region 102, and the other edge is aligned with or overlaps the edge of the sidewall 108 on one side of the first gate 106. At this time, the first isolation well 104 and the isolation layer 110 are arranged side by side, and the first isolation well 104 is located at the bottom of the first gate 106. Since the content of P-type impurities in the isolation layer 110 is much higher than the content of P-type impurities in the first isolation well 104, the isolation layer 110 with a high doping concentration can prevent the photoelectric sensing region 102 from expanding toward the surface of the substrate 100, thereby reducing the dark current caused by dangling bonds on the surface of the substrate 100.

As shown in FIG. 7 , in one embodiment of the present invention, a floating diffusion region 111 is further provided in the substrate 100. The doping type of the floating diffusion region 111 is the same as the doping region type of the photoelectric sensing region 102, and is a first type doping region. In this embodiment, the floating diffusion region 111 is an N-type heavily doped region. In this application, after forming the isolation layer 110, N-type impurities such as phosphorus (P) or arsenic (As) may be injected into the substrate 100 to form the floating diffusion region 111. In this embodiment, the floating diffusion region 111 is located on the side of the second gate 107 away from the storage node 103. The floating diffusion region 111 is located on the surface of the substrate 100, and the depth of the floating diffusion region 111 is greater than the second isolation well 105, and is much smaller than the depth of the storage node 103.

Please refer to FIG. 8 , in another embodiment of the present invention, the carrier suppression layer 109 covers the storage node 103 between the first gate 106 and the second gate 107, and the photoelectric sensing region 102 on one side of the first gate 106. The depth of the carrier suppression layer 109 in the second isolation well 105 is equal to the depth of the second isolation well 105, and the depth of the carrier suppression layer 109 in the first isolation well 104 is equal to the depth of the first isolation well 104. At this time, in the storage node 103, one edge of the carrier suppression layer 109 overlaps with the edge of the storage node 103, and extends toward the bottom of the second gate 107 at the same time as the storage node 103, and is aligned with or overlapped with the edge of the second gate 107; the other edge of the carrier suppression layer 109 extends toward the bottom of the first gate 106, and is aligned with or overlapped with the edge of the first gate 106. In the photoelectric sensing region 102, one edge of the carrier suppression layer 109 overlaps with the edge of the photoelectric sensing region 102, and the other edge is aligned with or overlaps with the edge of the sidewall 108 on one side of the first gate 106. When forming the carrier suppression layer 109 at two positions, the angle of ion implantation can be adjusted so that the carrier suppression layer 109 extends toward the bottom of the first gate 106 and the second gate 107. At this time, the carrier suppression layer 109 located in the photoelectric sensing region 102 can play the same role as the isolation layer 110, and relative to forming the isolation layer 110, providing the carrier suppression layer 109 in the photoelectric sensing region 102 can save a photomask, and is more conducive to electron transmission and avoids the formation of electron residue.

As shown in FIG. 9 , in another embodiment of the present invention, a floating diffusion region 111 is further provided in the substrate 100. The doping type of the floating diffusion region 111 is the same as the doping region type of the photoelectric sensing region 102, and is a first type doping region. In this embodiment, the floating diffusion region 111 is an N-type heavily doped region. In this application, after forming the carrier suppression layer 109, N-type impurities such as phosphorus (P) or arsenic (As) can be injected into the substrate 100 to form the floating diffusion region 111. In this embodiment, the floating diffusion region 111 is located on the side of the second gate 107 away from the storage node 103. The floating diffusion region 111 is located on the surface of the substrate 100, and the depth of the floating diffusion region 111 is greater than the second isolation well 105, and is much smaller than the depth of the storage node 103.

Please refer to Figures 15 and 16, in yet another embodiment of the present invention, the image sensor is a rolling exposure mode image sensor, which includes a substrate 100, a photoelectric sensing region 102 arranged in the substrate 100, an isolation well arranged in the photoelectric sensing region 102, a transfer tube arranged on the substrate 100 and located on one side of the photoelectric sensing region 102, and a carrier suppression layer 109 arranged in the photoelectric sensing region 102.

Please refer to FIG. 10 . In another embodiment of the present invention, the substrate 100 may be any applicable semiconductor material, such as silicon, silicon germanium on insulator, silicon on insulator, silicon germanium on insulator, silicon germanium on insulator, or a stacked structure composed of these semiconductors. In this embodiment, the substrate 100 is made of single crystal silicon doped with impurities, and can be formed by implanting ions into the silicon substrate 100. The doping type of the impurities in the substrate 100 is set according to the type of semiconductor to be formed. In this embodiment, the substrate 100 is, for example, a P-type substrate, and a P-type substrate can be formed by doping trivalent ions such as boron in the silicon substrate. In other embodiments, the substrate 100 may also be an N-type doped substrate, and an N-type substrate can be formed by doping pentavalent ions such as phosphorus in the silicon substrate.

Referring to FIG. 10 , in another embodiment of the present invention, an oxide layer 101 is provided on a substrate 100. The oxide layer 101 can be used as a gate oxide layer or as a buffer layer during ion implantation. In the present application, the oxide layer 101 can be formed on the substrate 100 by a thermal oxidation method or an in-situ water vapor growth method.

Please refer to FIG. 10 , in another embodiment of the present invention, a photoelectric sensing region 102 is provided in the substrate 100. The photoelectric sensing region 102 is a first type doped region, and the first type doped region is an N-type doped region, and is an N-type lightly doped region. In the present application, after forming the oxide layer 101, the oxide layer 101 can be used as an ion implantation buffer layer to implant N-type impurities such as phosphorus (P) or arsenic (As) into the substrate 100 to form the photoelectric sensing region 102. One side of the formed photoelectric sensing region 102 contacts the surface of the substrate 100, and the other side extends toward the bottom of the substrate 100.

Referring to FIG. 11 , in another embodiment of the present invention, an isolation well is further provided in the substrate 100. In the present application, the isolation well includes a first isolation well 104 located on the surface of the photoelectric sensing region 102. The isolation well is a second type doping region. In the present embodiment, the second type doping region is a P-type doping region. In the present application, the isolation well can be formed by injecting P-type impurities such as boron (B) into the substrate 100.

Please refer to FIG. 11 , in another embodiment of the present invention, the first isolation well 104 is located on the surface of the photoelectric sensing region 102, the depth of the first isolation well 104 is much smaller than the depth of the photoelectric sensing region 102, and the width of the first isolation well 104 is equal to the width of the photoelectric sensing region 102. The first isolation well 104 is a P-type doped region, and the impurity concentration of the first isolation well 104 is greater than the impurity concentration in the photoelectric sensing region 102. By providing the first isolation well 104 with a high doping concentration, the photoelectric sensing region 102 is prevented from extending toward the surface of the substrate 100, thereby reducing the dark current caused by dangling bonds on the surface of the substrate 100.

Please refer to FIG. 12 . In another embodiment of the present invention, a gate is further provided on the substrate 100, including a second gate 107 of the transmission tube. Among them, the gates of other transistors in the pixel, such as the reset tube, the source follower and the row selection tube, can also be formed simultaneously. In the present application, a gate material layer (not shown in the figure) can be formed on the oxide layer 101, and the gate material layer can be a material such as polysilicon or a metal material. The polysilicon can be a heavily doped polysilicon layer, and the metal material can be magnesium, aluminum, nickel, copper, gold, silver, TiAl-based alloy, titanium carbide, tantalum carbide or tungsten silicide, etc., or an alloy of several materials. After the gate material layer is formed, a patterned photoresist layer (not shown in the figure) is formed on the gate material layer, and the patterned photoresist layer is used as a mask to, for example, etch the gate material layer by dry etching to form a plurality of gates. The formed second gate 107 is located at one side of the photoelectric sensing region 102 , and the orthographic projection of the second gate 107 on the substrate 100 covers a portion of the photoelectric sensing region 102 and a portion of the substrate 100 close to the photoelectric sensing region 102 .

Please refer to FIG. 13 , in another embodiment of the present invention, sidewalls 108 are further provided on both sides of the gate. In one embodiment of the present invention, the sidewalls 108 are provided on both sides of the second gate 107. The sidewalls 108 may be silicon oxide sidewalls, silicon nitride sidewalls, or silicon oxide and silicon nitride stacked on the sidewalls. When forming the sidewalls 108, a material layer may be first deposited on the gate, and the material layer may be an oxide layer, a nitride layer, or an oxide layer and a nitride layer stacked. Afterwards, the material layer is etched, and only the material layer on the sidewall of the second gate 107 is retained to form the sidewalls 108.

Referring to FIGS. 14 to 16 , in other embodiments of the present invention, a carrier suppression layer 109 is disposed in the photoelectric sensing region 102 . One side of the carrier suppression layer 109 is in contact with the surface of the substrate 100 , and the depth of the carrier suppression layer 109 is equal to the depth of the first isolation well 104 . Specifically, when forming the carrier suppression layer 109 , a first substance and a second substance may be simultaneously injected into the substrate 100 , wherein the first substance may be combined with the dangling bonds in the substrate 100 to form a chemical bond. The second substance may inhibit the first substance from diffusing outward. The first substance may be a VIIA group element such as fluorine, chlorine, bromine and iodine, and a hydrogen element. The second substance may be a substance of the same group as silicon, such as carbon and tin. In a specific embodiment, the first substance is, for example, fluorine, and the second substance is, for example, carbon, then the first substance is combined with the dangling bonds in the substrate 100 to form a Si-F chemical bond. The second substance is, for example, carbon. After the injection of the first substance and the second substance is completed, in the subsequent annealing process, the carbon may inhibit the diffusion of fluorine.

Referring to FIG. 14 , in another embodiment of the present invention, a carrier suppression layer 109 is disposed in the photoelectric sensing region 102, and the carrier suppression layer 109 covers the entire photoelectric sensing region 102, and the depth of the carrier suppression layer 109 is equal to the depth of the first isolation well 104. At this time, in the photoelectric sensing region 102, the carrier suppression layer 109 covers the first isolation well 104, and both edges of the carrier suppression layer 109 extend out of the photoelectric sensing region 102, and one edge of the carrier suppression layer 109 extends toward the bottom of the second gate 107, and is aligned with or overlaps the edge of the second gate 107. When forming the carrier suppression layer 109, the angle of ion implantation can be adjusted so that the carrier suppression layer 109 extends toward the bottom of the second gate 107. The carrier suppression layer 109 can suppress the generation of carriers on the silicon surface of the photoelectric sensing region 102. At this time, there is no need to form an isolation layer 110 on the photoelectric sensing region 102 , which saves an ion implantation process and can better avoid the generation of residual electrons.

Please refer to FIG. 15 , in another embodiment of the present invention, a floating diffusion region 111 is further provided in the substrate 100. The doping type of the floating diffusion region 111 is the same as the doping region type of the photoelectric sensing region 102, which is a first type doping region. In this embodiment, the floating diffusion region 111 is an N-type heavily doped region. In this application, after forming the carrier suppression layer 109, N-type impurities such as phosphorus (P) or arsenic (As) can be injected into the substrate 100 to form the floating diffusion region 111. In this embodiment, the floating diffusion region 111 is located on the side of the second gate 107 away from the photoelectric sensing region 102. The floating diffusion region 111 is located on the surface of the substrate 100, and the depth of the floating diffusion region 111 is greater than the carrier suppression layer 109, and is much smaller than the depth of the photoelectric sensing region 102.

Referring to FIGS. 13 to 17 , in another embodiment of the present invention, the carrier suppression layer 109 covers a portion of the photoelectric sensing region 102, and the depth of the carrier suppression layer 109 is equal to the depth of the first isolation well 104. At this time, in the photoelectric sensing region 102, the carrier suppression layer 109 is arranged close to the second gate 107. One edge of the carrier suppression layer 109 extends toward the bottom of the second gate 107, aligning with or overlapping the edge of the second gate 107, and the other edge of the carrier suppression layer 109 extends toward the middle of the photoelectric sensing region 102. At this time, in the substrate 100 on the side of the carrier suppression layer 109 relative to the second gate 107, the first isolation well 104 and the carrier suppression layer 109 are arranged side by side. When forming the carrier suppression layer 109, the angle of ion implantation can be adjusted so that the carrier suppression layer 109 extends toward the bottom of the second gate 107. The carrier suppressing layer 109 can suppress the generation of carriers on the silicon surface of the photoelectric sensing region 102 .

Please refer to FIG. 16 and FIG. 17 . In another embodiment of the present invention, when the carrier suppression layer 109 covers a portion of the photoelectric sensing region 102, an isolation layer 110 is further provided in the photoelectric sensing region 102. One side of the isolation layer 110 is in contact with the surface of the substrate 100, and the depth of the isolation layer 110 is equal to the depth of the carrier suppression layer 109. Specifically, the isolation layer 110 is a second type doped region. In this embodiment, the second type doped region is a P-type doped region. When forming the isolation layer 110, the isolation layer 110 can be formed by injecting P-type impurities such as boron (B) into the second isolation well 105.

Referring to FIG. 16 and FIG. 17 , in another embodiment of the present invention, the isolation layer 110 covers the photoelectric sensing region 102 on the side away from the second gate 107. Specifically, one edge of the isolation layer 110 extends out of the photoelectric sensing region 102, and the other edge contacts the carrier suppression layer 109. At this time, the carrier suppression layer 109 and the isolation layer 110 are arranged side by side, and the carrier suppression layer 109 is located on the side close to the second gate 107. Since the content of P-type impurities in the isolation layer 110 is much higher than the content of P-type impurities in the first isolation well 104, the isolation layer 110 with a high doping concentration can prevent the photoelectric sensing region 102 from extending toward the surface of the substrate 100, thereby reducing the dark current caused by dangling bonds on the surface of the substrate 100.

Referring to FIG. 16 and FIG. 17 , in another embodiment of the present invention, an isolation layer 110 and a carrier suppression layer 109 are used to cover the photoelectric sensing region 102, and the carrier suppression layer 109 is located at a key position of electron transmission between the photoelectric sensing region 102 and the floating diffusion region 111, thereby avoiding the influence of residual electrons. At the same time, the isolation layer 110 is used to cover part of the photoelectric sensing region 102, thereby better suppressing dark current.

Referring to FIG. 16 and FIG. 17 , in another embodiment of the present invention, a floating diffusion region 111 is further provided in the substrate 100. The doping type of the floating diffusion region 111 is the same as the doping region type of the photoelectric sensing region 102, and is a first type doping region. In this embodiment, the floating diffusion region 111 is an N-type heavily doped region. In this application, after forming the isolation layer 110, N-type impurities such as phosphorus (P) or arsenic (As) can be injected into the substrate 100 to form the floating diffusion region 111. In this embodiment, the floating diffusion region 111 is located on the side of the second gate 107 away from the photoelectric sensing region 102. The floating diffusion region 111 is located on the surface of the substrate 100, and the depth of the floating diffusion region 111 is greater than the carrier suppression layer 109, and is much smaller than the depth of the photoelectric sensing region 102.

Please refer to Figures 7, 9, 15 and 17. In the present application, after forming the photoelectric sensing region 102, the storage node 103, the isolation well, the isolation layer, the floating diffusion region 111 and other doping regions, the doping regions are annealed to repair the lattice structure. In the present application, after completing other doping of the photoelectric sensing region 102 and the storage node 103, the carrier suppression layer 109 is formed, which can reduce the impact of annealing on the carrier suppression layer 109.

An image sensor provided by the present invention includes an image sensor in a rolling exposure mode and an image sensor in a global exposure mode. In the image sensor in the global exposure mode, a carrier suppression layer is formed in all or part of the photoelectric sensing region and the storage node between the transmission tube and the transfer tube. In the image sensor in the rolling exposure mode, a carrier suppression layer is formed in all or part of the photoelectric sensing region. By forming the carrier suppression layer on the photoelectric sensing region and the storage node, the formation of carriers is suppressed without forming electron residues.

The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims (13)

1. An image sensor, comprising:

A substrate;

A photo-sensing region disposed in the substrate; and

A carrier-suppressing layer disposed in the substrate, and the carrier-suppressing layer covers a portion or all of the photo-sensing region and/or a portion of the storage node;

The carrier inhibition layer comprises a first substance and a second substance, wherein the first substance is combined with a dangling bond in the substrate to form a chemical bond, and the second substance inhibits the outward diffusion of the first substance.

2. The image sensor of claim 1, wherein the first substance comprises fluorine, chlorine, bromine, iodine, or hydrogen.

3. The image sensor of claim 1, wherein the second substance comprises elemental carbon or elemental tin.

4. The image sensor of claim 1, further comprising:

the storage node is arranged in the substrate and is positioned at one side of the photoelectric sensing area;

The first grid electrode is arranged on the substrate, is positioned between the photoelectric sensing area and the storage node, and the orthographic projection of the first grid electrode on the substrate covers part of the photoelectric sensing area and part of the storage node;

And the second grid electrode is arranged on the substrate, is positioned on one side of the storage node far away from the photoelectric sensing area, and is aligned or overlapped with the storage node in the orthographic projection manner.

5. The image sensor of claim 4, wherein the carrier-inhibiting layer covers the storage node between the first gate and the second gate, and wherein one edge of the carrier-inhibiting layer overlaps an edge of the storage node and the other edge of the carrier-inhibiting layer is aligned with or overlaps the first edge.

6. The image sensor of claim 5, further comprising an isolation layer disposed in the substrate, the isolation layer covering the photo-sensing region on the first gate side.

7. The image sensor of claim 4, wherein the carrier-inhibiting layer covers the storage node between the first gate and the second gate, and the photo-sensing region on a side of the first gate.

8. The image sensor of claim 1, further comprising a second gate disposed on the substrate, the second gate being located on a side of the photo-sensing region, and a front projection of the second gate on the substrate covering a portion of the photo-sensing region and a portion of the substrate proximate to the photo-sensing region.

9. The image sensor of claim 8, wherein the carrier-inhibiting layer covers all of the photo-sensing region and an edge of the isolation layer extends beyond the photo-sensing region.

10. The image sensor of claim 8, wherein the carrier-inhibiting layer covers a portion of the photo-sensing region and the carrier-inhibiting layer is located on a side proximate to the second gate.

11. The image sensor of claim 10, further comprising an isolation layer disposed in the photo-sensing region, and the isolation layer covers the photo-sensing region on a side remote from the second gate.

12. A method for manufacturing an image sensor, comprising the steps of:

providing a substrate;

forming a photoelectric sensing region in the substrate;

forming a carrier suppression layer in the substrate, wherein the carrier suppression layer covers part or all of the photoelectric sensing region and/or part of the storage node;

The carrier inhibition layer comprises a first substance and a second substance, wherein the first substance is combined with a dangling bond in the substrate to form a chemical bond, and the second substance inhibits the outward diffusion of the first substance.

13. The method of manufacturing an image sensor according to claim 12, wherein before forming the carrier-suppressing layer, the method of manufacturing an image sensor further comprises: forming an isolation well in the substrate;

forming a gate electrode on the substrate; and

And forming side walls on two sides of the grid electrode.