CN118228644A

CN118228644A - Method, apparatus, device, storage medium and program product for digital chip design

Info

Publication number: CN118228644A
Application number: CN202211651093.5A
Authority: CN
Inventors: 王纯; 金晖; 李海龙; 黄琴; 孟硕; 刘瑜; 张一丁; 曹威
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-12-21
Filing date: 2022-12-21
Publication date: 2024-06-21

Abstract

Embodiments of the present disclosure provide methods, apparatus, devices, storage media and program products for digital chip design, relating to the chip arts. The provided method includes receiving module information and user input for a plurality of modules in a chip, wherein the user input includes an operation for at least one of the plurality of modules. The method further includes determining a hierarchical layout plan of the chip and an architectural design based on the layout plan prior to logic synthesis based on the user input and the module information. The method further includes updating, based on the architectural design, register transfer level code corresponding to the chip to obtain updated register transfer level code for logic synthesis. In this way, architecture design and register transfer level code can be updated quickly without logic synthesis, thereby improving the efficiency of chip design.

Description

Method, apparatus, device, storage medium and program product for digital chip design

Technical Field

Embodiments of the present disclosure relate generally to the field of chip design tools. More particularly, embodiments of the present disclosure relate to methods, apparatuses, devices, computer-readable storage media, and computer program products for digital chip design.

Background

Electronic design automation (electronic design automation, EDA) software is widely used in the process of functional design, synthesis, verification, simulation, etc. of chips. With EDA software, engineers can easily perform digital chip design processes such as architectural design and Register Transfer Level (RTL) code design, logic synthesis (synthesis), design for test (DFT), physical implementation (physical development), and signature (signoff). In the architecture design and RTL code design phase, engineers determine the architecture design of the chip, such as the function and initial layout plan of the individual modules, based on design requirements, and write the RTL code for describing the logic functions of the circuit using a hardware description language (e.g., verilog or VHDL). In the logic synthesis stage, considering the specific manner (e.g., appropriate units and processes) for implementing the logic functions of the circuit, the RTL code is converted into a netlist (netlist) in the form of logic gates. In the physical implementation stage, engineers determine finer physical layout plans and corresponding layout and routing based on the netlist, thereby determining the final chip design.

Typically, the design process of digital chips involves multiple iterations between the stages described above. Therefore, there is a need for an efficient chip design scheme for reducing iteration time, thereby speeding up design progress and reducing resource consumption.

Disclosure of Invention

Embodiments of the present disclosure provide a solution for digital chip design.

In a first aspect of the present disclosure, a method for digital chip design is provided. The method includes receiving module information and user input for a plurality of modules in a chip, wherein the user input includes an operation for at least one of the plurality of modules. The method further includes determining a hierarchical layout plan of the chip and an architectural design based on the layout plan prior to logic synthesis based on the user input and the module information. The hierarchical layout plan includes a plurality of layout plans at different levels and the plurality of layout plans are interrelated. The method further includes updating register transfer level, RTL, code corresponding to the chip based on the architectural design to obtain updated RTL code for logic synthesis. In this way, architecture design and RTL code can be updated quickly without logic synthesis, thereby improving the efficiency of chip design.

In some embodiments of the first aspect, determining the hierarchical layout plan of the chip comprises: determining a placement of a top-level module of the plurality of modules and a placement of a sub-module of the top-level module, wherein the placement of the top-level module correlates to the placement of the sub-module. In this way, a fine, hierarchical layout plan can be determined at the architectural design and RTL code design stages without the need for physical implementation tools.

In some embodiments of the first aspect, determining an architectural design based on the layout plan includes at least one of: determining the wiring between the plurality of modules, determining the insertion of register modules for time synchronization. In some embodiments of the first aspect, updating the RTL code corresponding to the chip based on the architectural design includes updating the RTL code based on at least one of the architectural designs: a new port associated with a trace through the plurality of modules; and a new register module for time synchronization. In this way, RTL code may be automatically updated based on through-wire and/or register module insertion.

In some embodiments of the first aspect, updating the RTL code comprises: based on the architecture design, register transfer level RTL codes corresponding to the chips are updated in real time. In some embodiments of the first aspect, the method further comprises: code portions corresponding to the updates of the architectural design are marked in the updated RTL code. In some embodiments of the first aspect, the method further comprises providing the RTL code updated. In this way, a user can be made to conveniently perceive the architecture design and the updating of the RTL code, thereby improving the user experience and speeding up the design flow.

In some embodiments of the first aspect, the module information includes at least one of: the area of each module of the plurality of modules, the location of each module, the interconnection relationship between the plurality of modules, and the hierarchical relationship between the plurality of modules. In some embodiments of the first aspect, determining the hierarchical layout plan of the chip includes determining the hierarchical layout plan with nanometer-scale accuracy.

In a second aspect of the present disclosure, an apparatus for digital chip design is provided. The apparatus includes a receiving unit configured to receive module information of a plurality of modules in a chip and user input including an operation for at least one of the plurality of modules. The apparatus further comprises an architectural design determination unit configured to determine a hierarchical layout plan of the chip and an architectural design based on the layout plan prior to logical synthesis based on the user input and the module information. The hierarchical layout plan includes a plurality of layout plans at different levels and the plurality of layout plans are interrelated. The apparatus further includes an RTL code updating unit configured to update an RTL code corresponding to the chip based on the architectural design to obtain an updated RTL code for logic synthesis.

In some embodiments of the second aspect, the architectural design determination unit is further configured to: determining a placement of a top-level module of the plurality of modules and a placement of a sub-module of the top-level module, wherein the placement of the top-level module correlates to the placement of the sub-module.

In some embodiments of the second aspect, the architectural design determination unit is further configured to determine at least one of: determining a trace between the plurality of modules, and determining an insertion of a register module for time synchronization. In some embodiments of the second aspect, the RTL code updating unit is further configured to update the RTL code based on at least one of the following in the architectural design: a new port associated with a trace through the plurality of modules; and a new register module for time synchronization.

In some embodiments of the second aspect, the RTL code update unit is further configured to: based on the architecture design, register transfer level RTL codes corresponding to the chips are updated in real time. In some embodiments of the second aspect, the apparatus further comprises a marking unit configured to: code portions corresponding to the updates of the architectural design are marked in the updated RTL code. In some embodiments of the second aspect, the apparatus further comprises an RTL code providing unit configured to: the updated RTL code is provided.

In some embodiments of the second aspect, the module information includes at least one of: the area of each module of the plurality of modules, the location of each module, the interconnection relationship between the plurality of modules, and the hierarchical relationship between the plurality of modules. In some embodiments of the second aspect, the architectural design determination unit is further configured to: determining the hierarchical layout plan with nanometer-scale precision.

In a third aspect of the present disclosure, there is provided an electronic device comprising: at least one computing unit; at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit cause the apparatus to implement the method provided by the first aspect.

In a fourth aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program, wherein the computer program is executed by a processor to implement the method provided in the first aspect.

In a fifth aspect of the present disclosure, there is provided a computer program product comprising computer executable instructions which, when executed by a processor, implement some or all of the steps of the method of the first aspect.

It will be appreciated that the electronic device of the third aspect, the computer storage medium of the fourth aspect or the computer program product of the fifth aspect provided above are each for performing the method provided by the first aspect. Therefore, the explanation or explanation concerning the first aspect is equally applicable to the third aspect, the fourth aspect, and the fifth aspect. The advantages achieved by the third, fourth and fifth aspects are referred to as advantages in the corresponding methods, and will not be described here.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic diagram of an example environment in which various embodiments of the present disclosure may be implemented;

FIG. 2 illustrates a flowchart of an example process for digital chip design, according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic diagram of an example process of determining architectural designs and RTL codes, according to some embodiments of the present disclosure;

FIG. 4 illustrates a schematic diagram of an example process of automatically updating RTL code, according to some embodiments of the present disclosure;

FIG. 5 illustrates a schematic diagram of an example process of iterative architectural design and RTL code, according to some embodiments of the present disclosure;

FIG. 6 illustrates a schematic block diagram of an apparatus for digital chip design in accordance with some embodiments of the present disclosure; and

FIG. 7 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As briefly mentioned above, the design process of a digital chip involves a reciprocating iteration between stages. Typically, different stages require different tools (e.g., a drawing tool and EDA software) or different functional units in EDA software to achieve the corresponding goals. Specifically, in the architectural design and RTL code design phases, a drawing tool may be utilized to determine an initial layout plan (also referred to as paper floorplan) for the chip and a corresponding initial architectural design. For example, the location of critical modules in the chip and the interconnection relationship between these critical modules may be determined. In general, conventional initial layout planning is non-hierarchical. For example, the initial layout plan may only indicate the placement of modules in a single hierarchy and not the placement of sub-modules in the modules. As another example, the initial layout plan may simply indicate the placement of modules in one or both levels without involving complex associations between the different levels. Furthermore, conventional initial layout planning is often relatively coarse. For example, conventional initial layout plans indicate the approximate shape and location of a module with a lower accuracy (e.g., micron-scale accuracy).

In the physical implementation phase, the initial layout plan and the initial architectural design are fine-tuned. EDA software as a physical implementation tool may determine finer layout plans and architectural designs based on netlists and physical information obtained by logical synthesis of the initial RTL code. For example, the physical implementation tool may determine hierarchical layout plans with greater precision (e.g., nanometer-scale precision) and determine finer architectural designs. The hierarchical layout plan may include a plurality of layout plans at different levels and the plurality of layout plans are interrelated. Multiple layout plans of different levels may indicate the placement of modules in the respective levels. For example, the hierarchical layout plan may indicate the placement of modules at the top level (also referred to simply as top level modules, e.g., important functional modules), and may indicate the placement of sub-modules (primary, secondary, or more) of the top level modules. The interrelated plurality of layout plans may influence and depend on each other. In some examples, the placement of sub-modules and the placement of top-level modules may be interrelated. When determining the placement of the top module, the latest placement result of the sub-modules of the top module may be referred to. In other examples, as the shape of the top module changes, the placement of sub-modules of the top module may be changed accordingly.

In this case, since logic synthesis is required to finely adjust the architectural design of the chip in the physical implementation stage, a single iteration time of the conventional architectural design is long. Furthermore, for each updated conventional architectural design, engineers need to manually update the RTL code, which would consume a significant amount of human resources. For example, if a first architectural design determined in a physical implementation phase does not meet the performance, power, area (PPA) requirements of a chip, RTL code needs to be manually updated and logically synthesized to generate an updated netlist for determining a second architectural design again in the physical implementation phase.

To at least partially address the above-referenced problems, as well as other potential problems, various embodiments of the present disclosure provide a solution for digital chip design. According to various embodiments described herein, a method for digital chip design is provided. The method includes receiving module information for a plurality of modules in a chip and user input including an operation for at least one of the plurality of modules. The method further includes determining a hierarchical layout plan of the chip and an architectural design based on the layout plan prior to logic synthesis based on the user input and the module information. The hierarchical layout plan may include a plurality of layout plans at different levels and the plurality of layout plans are interrelated. The method further includes updating RTL code corresponding to the chip based on the architectural design to obtain updated RTL code for logic synthesis.

Because the hierarchical layout planning of the chip and the architecture design based on the layout planning are determined before logic synthesis, rather than simply planning the placement of the top-level module in a non-hierarchical manner as in conventional designs, the scheme according to the embodiment of the disclosure can quickly adjust the architecture design of the chip without logic synthesis, thereby saving the time of logic synthesis in the repeated iteration process of the chip design. Further, schemes according to embodiments of the present disclosure may update RTL code based on adjustments in the architectural design of the chip. Such updating of the architecture-based design adjustments may be accomplished in an automated fashion, which further increases the efficiency of the digital chip design.

Various example embodiments of the disclosure are described below with reference to the accompanying drawings. FIG. 1 illustrates a schematic diagram of an example environment 100 in which various embodiments of the present disclosure may be implemented. As shown in FIG. 1, environment 100 includes an architecture design tool 110, a logical synthesis tool 120, and a physical implementation tool 130. In some embodiments, the architecture design tools 110, the logic synthesis tools 120, and the physical implementation tools 130 may be different EDA software. Alternatively, the architecture design tool 110, the logic synthesis tool 120, and the physical implementation tool 130 may be units or modules in the same EDA software for performing different functions.

The architecture design tool 110 receives inputs 101 associated with a chip design and provides corresponding outputs 102. The output 102 includes an architectural design 122 of the chip and RTL code 123 corresponding to the architectural design 122. In some embodiments, the input 101 received by the architecture design tool 110 may include design requirements of the chip, such as metrics associated with PPA. Alternatively or additionally, the input 101 may include module information determined based on design requirements. Examples of the module information may include at least one of a function, a number, an area, a location, a hierarchical relationship between modules, an interconnection relationship between modules, or the like of the modules. It should be understood that the term "module" as used herein may refer to various functional modules, IP (intellectual property) modules, macro-units, etc. in an digital chip design.

Alternatively or additionally, the input 101 may include user input to the architecture design tool 110. The user input may include a user operation of a module in the chip. The architecture design tools 110 may provide a representation of the modules in the chip. Examples of representations of modules may include graphical representations, numbered representations, and/or textual representations. The user's manipulation of the module may include manipulation of various forms of representations of the module. Examples of operations may include at least one of: placing modules, selecting modules to inquire module information, deleting or adding modules and the like.

The architecture design tool 110 determines the architecture design 122 and corresponding RTL code 123 of the chip based on the inputs 101. Architecture design 122 may indicate logical and physical information of the chip. In some embodiments, the architectural design 122 may be a physical architectural planning design, including, for example, at least one of: for the shape, position of the modules, insertion of register modules for time synchronization, or routing between modules. The architectural design 122 may be determined based on nanoscale-accurate, hierarchical layout planning. In other words, the architectural design 122 determined by the architectural design tool 110 has a higher accuracy and includes finer, hierarchical module location information and interconnection information than the initial architectural design determined at the architectural design and RTL code design stages discussed above.

In some embodiments, the architectural design 122 may be a design exchange format (design exchange format, DEF). In this way, the architectural design 122 may be conveniently provided to the logic synthesis tool 120 and the physical implementation tool 130 for use in a later stage of the chip design.

As shown in FIG. 1, logic synthesis tool 120 receives output 102 and determines a corresponding netlist 124 based on RTL code 123 and the physical information. Netlist 124 is input to physical implementation tool 130. Physical implementation tool 130 may perform layout routing, clock tree synthesis, etc. steps based on netlist 124 to generate layout 125 for chip fabrication.

It should be appreciated that the logic synthesis tool 120 and the physical implementation tool 130 may be commercially available tools, and the scope of the present disclosure is not limited in this regard. Furthermore, the examples and corresponding descriptions shown in FIG. 1 are illustrative only and not limiting. The scope of the present disclosure is not limited in terms of the specific implementation of the architecture design tools 110.

Fig. 2 illustrates a flowchart of an example process 200 for digital chip design, according to some embodiments of the present disclosure. Process 200 may be implemented by any suitable computing unit. For example, it may be performed by a computer or other electronic device having computing or circuit design capabilities. In particular, the architecture design tool 110 may be implemented by a processor of a computer to perform the process 200 according to data and/or instructions stored in a memory, for example. An example process 200 for digital chip design will be described below with reference to fig. 1.

At block 210, a processor receives module information and user input for a plurality of modules in a chip, wherein the user input includes operations for at least one of the plurality of modules. The module information and user input may be at least part of the input 101 shown in fig. 1.

In some embodiments, the architecture design tools 110 implemented by the processor may have a graphical user interface (GRAPHICAL USER INTERFACE, GUI) and may interact with user inputs using the GUI. For example, the architecture design tools 110 may receive user input based on gestures, contacts, styluses, mouse pointers. Alternatively or additionally, the architecture design tool 110 may receive user input based on code instructions. For example, a user may input operations for a module in code commands to the architecture design tool 110. These module information and user inputs received by the architecture design tools 110 are provided to the processor.

In some embodiments, the architecture design tools 110 may have received and stored module information prior to receiving user input, such as in memory, and recalled from memory for execution by the processor as needed. In addition, the architecture design tools 110 may provide the module information to the user as auxiliary information when the user operates the module, such as for display on a display. Alternatively or additionally, the architecture design tool 110 may take the module information as a constraint, thereby restricting the user's operation of the module so that the user's operation of the module meets design requirements.

The processor may provide the module information in a variety of suitable forms. For example, the hierarchical relationship between modules may be indicated in the architecture design tools 110 in the form of a hierarchical directory. Additionally or alternatively, the hierarchy of modules may be indicated in the architecture design tool 110 in the naming of the modules. Additionally or alternatively, the representation of the module may be linked to module information for providing the module information to the user in response to a query by the user.

At block 220, the processor determines a hierarchical layout plan for the chip and a layout plan-based architectural design 122 prior to logic synthesis based on the user inputs and the module information. In other words, the processor may directly determine the hierarchical layout plan and architectural design 122 without invoking the logic synthesis tool 120 to logically synthesize the initial RTL code into a netlist and the physical implementation tool 130 to determine the hierarchical layout plan. Therefore, by utilizing the scheme of the embodiment of the disclosure, hierarchical layout planning and architecture design can be determined in the stage of architecture design and RTL code design, so that the updating speed of the architecture design is increased.

In some embodiments, the processor may determine a hierarchical layout plan of nanometer-scale accuracy based on the user input and the module information. The processor may determine the placement of the top-level module based on the user's movement of the top-level modules in the modules, and may determine the placement of the sub-modules based on the user's movement of the sub-modules of one or more levels of the top-level module. The placement of sub-modules and the placement of top-level modules may be interrelated.

For example, based on the hierarchical relationship of the modules, the processor may determine the placement of the modules layer by layer. Alternatively or additionally, the processor may alternatively determine the placement of modules at different levels. In one example, in the processor-implemented architecture design tools 110, the top-level modules may be placed one level after the top-level modules are placed, and the top-level modules may be repositioned after the one level of sub-modules are placed. The placement results of the sub-modules may be associated with the corresponding top-level module, and the user may query the placement results of the sub-modules by clicking on the top-level module. In some embodiments, the processor may provide the determined location of the module in real time. For example, in the processor-implemented architecture design tools 110, the placement of modules may be displayed in real-time. Alternatively or additionally, the placement results of one or more tiers of modules may be selectively displayed.

Based on the hierarchical layout plan, the processor also determines the architectural design 122 corresponding thereto. In some embodiments, the processor may determine the routing between the modules based on the received user input. The routing between modules may include routing through channels and routing through modules (also known as feedthru). In some embodiments, the architecture design tools 110 implemented by the processor may provide the user with interconnection information of the modules while receiving user input to guide the user in planning the routing between the modules.

Alternatively or additionally, the processor may add or delete modules based on received user input. For example, the architecture design tool 110 implemented by the processor may receive a user operation to add or delete modules to determine the architecture design 122 of the chip. For example, the architectural design tool 110 can insert a register module for time synchronization in response to user input. Alternatively or additionally, the architecture design tool 110 may determine any other suitable architecture design based on user input and module information.

At block 230, the processor updates the RTL code 123 corresponding to the chip based on the architectural design 122 to obtain updated RTL code. In some embodiments, the processor may identify a target design in the architectural design 122 and update a code portion associated with the identified target design in the RTL code 123. The target design may be a predetermined architectural design that causes a change in the RTL code. Examples of target designs may include through-wiring, insertion of register modules for time synchronization, and the like.

In some embodiments, in response to identifying a pass-through trace in the architectural design 122, the processor may automatically update a code portion corresponding to a new port associated with the pass-through trace in the RTL code 123. Alternatively or additionally, the processor may automatically add a code portion corresponding to a newly added register module in the RTL code based on the register module.

In some embodiments, the processor may identify a target design such as a pass-through trace based on an algorithm such as graphical collision detection. Alternatively or additionally, the processor may record operations of the user for architectural design and identify operations associated with the target design from among the operations based on characteristics of the operations. In response to the identified target design, the processor may generate a code portion corresponding to the target design and update the RTL code with the generated code portion. For example, the processor may modify a pre-written code template based on the identified target design to generate a corresponding code portion. Alternatively or additionally, the processor may update the RTL code based on the received user input. For example, the architectural design tool 110 implemented by the processor may receive user input for determining RTL code corresponding to the architectural design.

Alternatively or additionally, the processor may update the RTL code 123 accordingly based on the updating of the architectural design based on any other suitable method. Accordingly, with the scheme according to the embodiment of the present disclosure, the RTL code can be automatically updated based on the updating of the architectural design without requiring an engineer to manually write the RTL code, thereby increasing the updating speed of the RTL code.

In some embodiments, the processor may update the RTL code 123 in real-time based on the architectural design 122. For example, the architecture design tools 110 implemented by the processor may provide a first window in the GUI for receiving user input to update the architecture design 122 and a second window for providing real-time updated RTL code 123, thereby providing the updated RTL code 123 to the user in what-you-see-is-what-you-get form. In this way, a user can conveniently learn about the updating of the architectural design 122 and the RTL code 123 so that the architectural design can be iterated quickly and the final RTL code determined.

Alternatively or additionally, the processor may output a file of the RTL code 123 via an output component of the computing device to provide the updated RTL code 123 to the user. Alternatively or additionally, the processor, when updating the RTL code 123, may mark the code portion corresponding to the update of the architectural design. In some examples, the added code portions may be presented in a highlighted form. In other examples, the updated code portions may be presented in different colors.

FIG. 3 illustrates a schematic diagram of an example process 300 of determining architectural designs and RTL codes, according to some embodiments of the present disclosure. Process 300 may be implemented by any suitable computing unit. For example, it may be performed by a computer or other electronic device having computing or circuit design capabilities. In particular, the architecture design tool 110 may be implemented by a processor of a computer to perform the process 300 according to data and/or instructions stored in a memory, for example. An example process 300 of determining architectural design and RTL code is described below with reference to fig. 1.

As shown in fig. 3, the processor may determine a hierarchical layout plan 301 and an architectural design 302 corresponding to the hierarchical layout plan 301 based on user input and module information. Hierarchical layout plan 301 may include a plurality of layout plans at different levels and with the plurality of layout plans being interrelated. Multiple layout plans of different levels may indicate the placement of modules in the respective levels. For example, the hierarchical layout plan 301 may include a placement of top-level modules and a placement of sub-modules (e.g., primary, secondary, or more sub-modules) of the top-level modules. In some embodiments, hierarchical layout plan 301 may have nanometer-scale precision. The architectural design 302 corresponding to the hierarchical layout plan 301 may include inter-module traces, such as channel-type traces 303 and through-type traces 304. Although not shown, the architectural design 302 may also include traces between sub-modules, register modules for time synchronization, and/or other architectural designs.

FIG. 3 also shows an example portion 310 of the architectural design 302. Specifically, in the example portion 310 in the architectural design 302, the module 311 (labeled u_e) and the module 312 (labeled u_f) are connected to each other via the trace 321 labeled xx 1. There is no connection between module 313 (labeled U_ABC_0) and module 314 (labeled U_M), and there is no connection between module 313 and module 315 (labeled U_H). The modules 314 and 315 are interconnected via traces 322 labeled (xx 2, xx 3), and the traces 322 run through the modules 313.

FIG. 3 also shows the update process of RTL code caused by the newly added trace 322 in the example section 310. FIG. 3 shows RTL code portion 330 before trace 322 is added and RTL code portion 340 after trace 322 is added. RTL code portion 330 and RTL code portion 340 correspond to module 313. As shown in fig. 3, after adding trace 322, the RTL code portion 340 of module 313 has added to it the code portion 341 of the two ports associated with trace 322.

FIG. 4 illustrates a schematic diagram of an example process 400 for automatically updating RTL code, according to some embodiments of the present disclosure. Process 400 may be implemented by any suitable computing unit. For example, it may be performed by a computer or other electronic device having computing or circuit design capabilities. In particular, the architecture design tool 110 may be implemented by a processor of a computer to perform the process 400 according to data and/or instructions stored in a memory, for example. An example process 400 for automatically updating RTL code will be described below with reference to fig. 1 and 3.

As shown in fig. 4, at block 410, the processor may perform a graphical collision detection to detect collisions (e.g., through-wires) between modules and wires in the architectural design 122. Referring to fig. 3, the processor may detect a collision between the module 313 and the trace 322. At block 420, the processor may parse the RTL code to identify code portions corresponding to the crashed modules. For example, the processor may identify the portion of RTL code 330 corresponding to module 313 in the chip's RTL code. At block 430, the processor may define the threading location and port at which the collision occurred to determine the code portion corresponding to the detected pass-through trace. For example, the processor may determine the location of the threading based on image recognition of the graphical representation of the architectural design 122 and define the newly added port based on predetermined code rules. At block 440, the processor may automatically update the RTL code. For example, the processor may add a code portion 341 corresponding to the newly added port to the parsed RTL code portion 330 corresponding to the module 313 to obtain the updated RTL code portion 340.

FIG. 5 illustrates a schematic diagram of an example process 500 of updating architectural designs and RTL code, according to some embodiments of the present disclosure. Process 500 may be implemented by any suitable computing unit. For example, it may be performed by a computer or other electronic device having computing or circuit design capabilities. In particular, the architecture design tool 110 may be implemented by a processor of a computer to perform the process 500 according to data and/or instructions stored in a memory, for example. An example process 500 of determining updated architectural design and RTL code will be described below with reference to fig. 1.

As shown in fig. 5, at block 510, the processor may receive an input 101. The received input 101 may include interactive input by a user to the architecture design tool 110. Additionally or alternatively, the received input may include module information. Additionally or alternatively, the received inputs may include any suitable inputs for determining and updating layout plans, architectural designs, and/or RTL code, e.g., updated constraints for the RTL code.

At block 520, the processor may determine (or update) a hierarchical layout plan of the chip based on the received inputs 101. In some embodiments, the processor may first determine the placement of the top-level module. The processor may then determine the placement of the primary sub-modules of the top module. The processor may then adjust the placement of the top module based on the placement of the first level sub-module. For example, the distance between the two top layer modules is enlarged in consideration of the close arrangement positions of the sub-modules in the first top layer module and the second top layer module.

At block 530, the processor may determine (or update) the architectural design 122 of the chip based on the determined hierarchical layout plan and the received inputs 101. In some embodiments, the processor may determine the routing between the top-level modules based on the placement of the top-level modules. Alternatively or additionally, the processor may add register modules on the basis of the timing requirements of the circuit on the basis of the layout plan for reducing metastability by register beating and for achieving synchronization of different clock domains.

At block 540, the processor may determine or update corresponding RTL code based on the determined architectural design 122. In some embodiments, the processor may perform an image-based analysis on the graphical representation of the architectural design to determine a target design in the architectural design that will cause a change in the RTL code.

As shown in FIG. 5, the processor may iterate through the steps at blocks 510, 520, 530, and 540 multiple times to iteratively update the layout plan, architectural design, and RTL code without invoking the logical synthesis tool 120 and the physical implementation tool 130. For example, if a first architectural design determined in the architectural design and RTL code design phase does not meet the requirements, the architectural design tool 110 implemented by the processor may directly modify the first architectural design to determine a second architectural design and determine automatically updated RTL code corresponding to the second architectural design.

Therefore, by utilizing the scheme of the embodiment of the disclosure, the situation that the layout planning and the architecture design can be determined by logic synthesis can be avoided, so that the layout planning and the architecture design can be quickly adjusted. In particular, by directly determining hierarchical layout and architecture designs using the architecture design tool 110 during hierarchical chip design, situations can be avoided in which the top-level architecture design can be determined after logic synthesis and layout planning for each module. In this way, logic synthesis for each module may not be required each time the architecture design is adjusted, thereby greatly speeding up the design flow and reducing resource consumption.

The principles and details of an approach for digital chip design according to embodiments of the present disclosure are described above with reference to fig. 1-5. It should be understood that the above-described processes 200, 400, 500 are merely exemplary and are not to be construed as limiting the scope of the present disclosure.

Example apparatus and apparatus

Fig. 6 shows a block diagram of an apparatus 600 for digital chip design according to an embodiment of the disclosure. In particular, the device 600 may be an EDA software device. The apparatus 600 may include a plurality of modules for performing corresponding steps in the processes 200, 400, and 500 as discussed in fig. 2, 4, and 5. As shown in fig. 6, the apparatus 600 includes a receiving unit 610 configured to receive module information of a plurality of modules in a chip and user input including an operation for at least one of the plurality of modules. The apparatus 600 further comprises an architectural design determination unit 620 configured to determine a hierarchical layout plan of the chip and an architectural design based on the layout plan prior to logical synthesis based on the user input and the module information. The hierarchical layout plan includes a plurality of layout plans at different levels and the plurality of layout plans are interrelated. The apparatus 600 further comprises an RTL code updating unit 630 configured to update the RTL code corresponding to the chip based on the architectural design to obtain an updated RTL code, the updated RTL code being used for logic synthesis.

In some embodiments, the architectural design determination unit 620 is further configured to: and determining the placement of the top layer module and the placement of the sub-modules in the top layer module in the plurality of modules, wherein the placement of the top layer module is related to the placement of the sub-modules. In some embodiments, the architectural design determination unit 620 is further configured to: a hierarchical layout plan of nanometer-scale accuracy is determined.

In some embodiments, the architectural design determination unit 620 is further configured to determine at least one of: determining a trace between a plurality of modules, and determining an insertion of a register module for time synchronization. In some embodiments, the RTL code update unit 630 is further configured to update the RTL code based on at least one of the following in the architectural design: a new port associated with a trace through the plurality of modules; and a new register module for time synchronization.

In some embodiments, the RTL code update unit is further configured to: based on the architecture design, the RTL code corresponding to the chip is updated in real time. In some embodiments, the apparatus 600 further comprises a marking unit configured to: code portions corresponding to updates of the architectural design are marked in the updated RTL code. In some embodiments, the apparatus 600 further comprises an RTL code providing unit configured to: updated RTL code is provided.

In some embodiments, the module information includes at least one of: the area of each of the plurality of modules, the location of each of the plurality of modules, the interconnection relationship between the plurality of modules, and the hierarchical relationship between the plurality of modules.

Fig. 7 shows a schematic block diagram of an example device 700 that may be used to implement embodiments of the present disclosure. As shown, the device 700 includes a computing unit 701 that may perform various suitable actions and processes in accordance with computer program instructions stored in a Random Access Memory (RAM) 703 and/or a Read Only Memory (ROM) 702 or loaded into the RAM703 and/or ROM 702 from a storage unit 708. In the RAM703 and/or the ROM 702, various programs and data required for the operation of the device 700 may also be stored. The computing unit 701 and the RAM703 and/or the ROM 702 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

Various components in device 700 are connected to I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, etc.; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, an optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The computing unit 701 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 701 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as processes 200, 400, and 500. For example, in some embodiments, the processes 200, 400 and 500 may be implemented as computer software programs, in particular EDA programs, tangibly embodied on a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 700 via RAM and/or ROM and/or communication unit 709. One or more of the steps of the processes 200 and 500 described above may be performed when a computer program is loaded into RAM and/or ROM and executed by the computing unit 701. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the processes 200, 400, and 500 by any other suitable means (e.g., by means of firmware).

In the above embodiments, the method flows may be implemented in whole or in part by software, hardware, firmware, or any combination thereof, and when implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions which, when loaded and executed on a server or terminal, fully or partially produce a process or function in accordance with embodiments of the present application. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer readable storage medium may be any available medium that can be accessed by a server or terminal or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape, etc.), an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid state disk, etc.).

Moreover, although operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims

1. A method for digital chip design, comprising:

Receiving module information and user input of a plurality of modules in a chip, wherein the user input comprises an operation for at least one module in the plurality of modules;

determining, prior to logical synthesis, a hierarchical layout plan of the chip and an architectural design based on the layout plan based on the user input and the module information, the hierarchical layout plan including a plurality of layout plans at different levels and the plurality of layout plans being interrelated; and

Based on the architectural design, register transfer level RTL code corresponding to the chip is updated to obtain updated RTL code, the updated RTL code being used for the logic synthesis.

2. The method of claim 1, wherein determining a hierarchical layout plan for the chip comprises:

determining a placement of a top-level module of the plurality of modules and a placement of a sub-module of the top-level module, wherein the placement of the top-level module correlates to the placement of the sub-module.

3. The method of claim 1 or 2, wherein determining an architectural design based on the layout plan comprises at least one of:

Determining a trace between the plurality of modules,

The insertion of a register module for time synchronization is determined.

4. A method according to any one of claims 1 to 3, wherein updating RTL code corresponding to the chip based on the architectural design comprises: updating the RTL code based on at least one of the following in the architectural design:

A new port associated with a trace through the plurality of modules; and

A new register module for time synchronization.

5. The method of claim 4, the updating register transfer level, RTL, code corresponding to the chip based on the architectural design comprising:

based on the architecture design, register transfer level RTL codes corresponding to the chips are updated in real time.

6. The method of claim 5, further comprising:

code portions corresponding to updates of the architectural design are marked in the updated RTL code.

7. The method of any of claims 1 to 6, wherein the module information comprises at least one of:

the area of each module of the plurality of modules, the location of each module, the interconnection relationship between the plurality of modules, and the hierarchical relationship between the plurality of modules.

8. The method of any of claims 1-7, wherein determining a hierarchical layout plan of the chip comprises: determining the hierarchical layout plan with nanometer-scale precision.

9. An apparatus for digital chip design, comprising:

A receiving unit configured to receive module information of a plurality of modules in a chip and a user input including an operation for at least one of the plurality of modules;

an architectural design determination unit configured to determine, prior to logic synthesis, a hierarchical layout plan of the chip and an architectural design based on the layout plan, the hierarchical layout plan including a plurality of layout plans at different levels and the plurality of layout plans being associated with each other, based on the user input and the module information; and

And an RTL code updating unit configured to update an RTL code corresponding to the chip based on the architecture design to obtain an updated RTL code, the updated RTL code being used for the logic synthesis.

10. The apparatus of claim 9, wherein the architectural design determination unit is further configured to:

11. The apparatus according to claim 8 or 9, wherein the architectural design determination unit is further configured to determine at least one of:

Determining a trace between the plurality of modules,

The insertion of a register module for time synchronization is determined.

12. The apparatus of any of claims 9 to 11, wherein the RTL code updating unit is further configured to update the RTL code based on at least one of the architectural designs:

A new port associated with a trace through the plurality of modules; and

A new register module for time synchronization.

13. The apparatus of claim 12, wherein the RTL code update unit is further configured to:

14. The apparatus of claim 13, further comprising a marking unit configured to:

15. The apparatus of any of claims 9 to 14, wherein the module information comprises at least one of:

16. The apparatus of any of claims 9 to 15, wherein the architectural design determination unit is further configured to:

Determining the hierarchical layout plan with nanometer-scale precision.

17. An electronic device, comprising:

At least one computing unit;

At least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit, cause the electronic device to perform the method of any one of claims 1-8.

18. A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method according to any of claims 1-8.

19. A computer program product comprising computer executable instructions, wherein the computer executable instructions when executed by a processor implement the method according to any one of claims 1-8.