[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN118211555B - Chip design method, chip design system, and readable storage medium - Google Patents

Chip design method, chip design system, and readable storage medium Download PDF

Info

Publication number
CN118211555B
CN118211555B CN202410638159.XA CN202410638159A CN118211555B CN 118211555 B CN118211555 B CN 118211555B CN 202410638159 A CN202410638159 A CN 202410638159A CN 118211555 B CN118211555 B CN 118211555B
Authority
CN
China
Prior art keywords
sub
regions
decoupling
chip design
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202410638159.XA
Other languages
Chinese (zh)
Other versions
CN118211555A (en
Inventor
请求不公布姓名
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Bi Ren Technology Co ltd
Original Assignee
Shanghai Bi Ren Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Bi Ren Technology Co ltd filed Critical Shanghai Bi Ren Technology Co ltd
Priority to CN202410638159.XA priority Critical patent/CN118211555B/en
Publication of CN118211555A publication Critical patent/CN118211555A/en
Application granted granted Critical
Publication of CN118211555B publication Critical patent/CN118211555B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/392Floor-planning or layout, e.g. partitioning or placement

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention provides a chip design method, a chip design system and a readable storage medium. The chip design method comprises the following steps: carrying out layout planning; executing a script to divide the chip into a plurality of sub-regions; calculating a plurality of standard cell utilization rates of a plurality of subareas; and inserting at least one decoupling cell in at least one of the plurality of sub-regions according to the standard cell utilization of each of the plurality of sub-regions. The invention can automatically and properly insert the decoupling unit. The chip design method, the chip design system and the computer readable storage medium can effectively improve the problem of voltage drop violations of the whole and the part of the chip.

Description

Chip design method, chip design system, and readable storage medium
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a chip design method, a chip design system, and a readable storage medium.
Background
In conventional chip design processes, the insertion of decoupling cells (DECAP CELL) is typically implemented using built-in commands of electronic design automation (Electronic design automation, EDA) software. In this regard, the conventional insertion of decoupling cells has a problem that the number of decoupling cells in a certain area of the chip is not positively correlated with the number of standard cells, and thus the problem of voltage drop (IR-drop) violations in areas where the decoupling cells are less distributed cannot be effectively improved. Or too many decoupling units are inserted in a certain area of the chip, so that power consumption is increased.
Disclosure of Invention
The present invention is directed to a chip design method, a chip design system, and a computer-readable storage medium, which can realize an automatic and efficient operation of inserting (placing) decoupling cells.
According to an embodiment of the present invention, the chip design method of the present invention includes the steps of: carrying out layout planning; executing a script to divide the chip into a plurality of sub-regions; calculating a plurality of standard cell utilization rates of the plurality of sub-areas; and inserting at least one decoupling cell in at least one of the plurality of sub-regions according to the standard cell utilization for each of the plurality of sub-regions.
In an embodiment of the invention, the standard cell utilization and decoupling cell utilization of each of the plurality of sub-regions are positively correlated.
In an embodiment of the invention, the step of calculating the plurality of standard cell utilizations of the plurality of sub-regions comprises: and calculating the proportion of the areas of the standard cells of each of the plurality of subareas to the area of the corresponding subarea.
In an embodiment of the invention, the step of inserting the at least one decoupling cell at the at least one of the plurality of sub-regions according to the standard cell utilization of each of the plurality of sub-regions comprises: inserting a corresponding proportion of the at least one decoupling cell in the at least one of the plurality of sub-regions according to the proportion of the standard cell area of each of the plurality of sub-regions.
In an embodiment of the invention, the standard cell comprises logic circuitry.
In an embodiment of the present invention, the chip design method further includes the steps of: judging whether the number of the integral decoupling units of the plurality of subareas is larger than or equal to a global specified amount; and selecting at least one of the plurality of sub-regions to supplement insertion of at least one decoupling cell when the number of integral decoupling cells of the plurality of sub-regions is not greater than or equal to the globally specified amount.
In an embodiment of the invention, the step of selecting said at least one of said plurality of sub-regions to supplement the insertion of said at least one decoupling cell comprises: the sub-region of the plurality of sub-regions having the most standard cells is preferentially selected for insertion of the at least one decoupling cell.
In an embodiment of the invention, the step of executing the script comprises: and executing the script after the wiring flow of the layout planning.
According to an embodiment of the present invention, the computer-readable storage medium of the present invention stores instructions. The instructions are executed by a processor to implement the chip design method as described above.
According to an embodiment of the present invention, a chip design system of the present invention includes a processor and a storage device. A storage device is coupled to the processor and configured to store a script. The processor performs layout planning and executes a script to divide the chip into a plurality of sub-regions. The processor calculates a plurality of standard cell utilizations of the plurality of sub-regions and inserts at least one decoupling cell in at least one of the plurality of sub-regions based on the standard cell utilizations of each of the plurality of sub-regions.
Based on the above, the chip design method, the chip design system and the computer readable storage medium of the present invention can achieve a uniform decoupling cell insertion effect by dividing the chip into a plurality of sub-regions and evaluating the sub-regions respectively to insert the corresponding proportion of the number of decoupling cells respectively.
The present invention may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and for the sake of brevity of the drawings, various drawings in the present invention depict only a portion of the apparatus, and the particular components in the drawings are not necessarily drawn to scale. In addition, the number and size of the components in the drawings are illustrative only and are not intended to limit the scope of the invention.
Drawings
FIG. 1 is a schematic diagram of a chip design system according to an embodiment of the invention;
FIG. 2 is a flow chart of a chip design method of an embodiment of the invention;
FIG. 3 is a layout effect diagram of a chip according to an embodiment of the present invention;
FIG. 4 is a layout effect diagram of a chip according to an embodiment of the present invention;
FIG. 5 is a layout effect diagram of a chip according to an embodiment of the present invention;
fig. 6 is a layout effect diagram of a chip according to an embodiment of the present invention.
Description of the reference numerals
100: A chip design system;
110: a processor;
120: a storage device;
121: a script;
122: layout data;
300: a module;
301-304: a sub-region;
310_1 to 310_8: a standard cell;
320_1 to 320_9: a decoupling unit;
S210-S240: and (3) step (c).
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 1 is a schematic diagram of a chip design system according to an embodiment of the invention. Referring to fig. 1, a chip design system 100 includes a processor 110 and a storage 120. The processor 110 is coupled to the storage device 120. The storage 120 may store scripts 121 and layout data 122. In this embodiment, the processor 110 may execute electronic design automation (Electronic design automation, EDA) software to perform layout planning (Floorplan) of the chip according to the layout data 122. Layout data 122 may include, but is not limited to, data related to a layout generated by processor 110 reading netlist (netlist) data and mapping it to a physical layout, or may also include parameters related to a chip layout (e.g., chip size, shape, placement of input-output cells and/or Macro (Macro) cells, etc.), power supply planning (Powerplan) parameters, layout (space) and routing (Route) constraints, and/or pin constraint files, etc.
In this embodiment, the script 121 may be edited by a tool command language (Tool Command Language, TCL). During the layout planning of the processor 110, the processor 110 may execute the script 121 to perform the automated decoupling unit (DECAP CELL) insertion operation, so as to effectively improve the overall and local voltage drop (IR-drop) violation problem of the chip. Notably, the electronic design automation software in the layout planning process is not additionally used in the execution of the script 121 by the processor 110 to implement the insertion operation of the decoupling unit. In addition, the decoupling cell may be comprised of a capacitor or an associated charge storage unit.
In this embodiment, the Processor 110 may be, for example, a central processing unit (Central Processing Unit, CPU), other programmable general purpose or special purpose Microprocessor (Microprocessor), digital signal Processor (DIGITAL SIGNAL Processor, DSP), programmable controller, application SPECIFIC INTEGRATED Circuits (ASIC), programmable logic device (Programmable Logic Device, PLD), other similar processing devices, or a combination of these devices. Storage 120 is, for example, a computer-readable storage medium. The computer readable storage medium has computer readable instructions stored thereon. When executed by the processor 110, the chip design methods described with reference to the various embodiments of the invention may be performed. The computer readable storage medium in embodiments of the present invention may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (ddr SDRAM), enhanced Synchronous Dynamic Random Access Memory (ESDRAM), synchronous Link Dynamic Random Access Memory (SLDRAM), and direct memory bus random access memory (DR RAM). The storage 120 may store scripts 121, layout data 122, programs of a compiler, and software, programs, algorithms, etc. required to implement the present invention, and is executed by the processor 110.
Fig. 2 is a flow chart of a chip design method according to an embodiment of the invention. Referring to fig. 1 and 2, the processor 110 may execute the following steps S210 to S240 to implement an efficient and automatic decoupling unit insertion process. In step S210, the processor 110 performs layout planning. In the present embodiment, the processor 110 may perform a layout planning process according to the layout data 122. The layout planning process may include, in Order, a power planning (Powerplan) process, a layout (Place) process, a Clock tree integration (Clock TREE SYNTHESIS, CTS) process, a routing (Route) process, an engineering change instruction (ENGINEERING CHANGE Order, ECO) process, and a validation (Signoff) process. In this embodiment, the processor 110 may execute the script 121 after the routing process of the layout plan to perform the insertion process of the decoupling unit. In step S220, the processor 110 executes the script 121 to divide the chip into a plurality of sub-areas. In this embodiment, the script 121 may divide the layout range of the module (or sub-module) of the chip into a plurality of sub-areas according to a preset division number, so as to analyze the sub-areas individually.
In step S230, the processor 110 calculates a plurality of standard cell utilization rates for a plurality of sub-regions. The standard cell includes logic circuitry. In step S240, the processor 110 inserts at least one decoupling cell in at least one of the plurality of sub-regions according to the standard cell utilization of each of the plurality of sub-regions. In this embodiment, the processor 110 may calculate an area ratio of the standard cells of each of the plurality of sub-regions, and the processor 110 may insert at least one decoupling cell of a corresponding ratio in at least one of the plurality of sub-regions according to the area ratio of the standard cells of each of the plurality of sub-regions. It should be noted that the plurality of sub-regions have the same area, and the respective ratio may refer to a ratio of an area of a standard cell in each sub-region to an area of the corresponding sub-region. The processor 110 may make a decision to insert a corresponding area ratio or a corresponding number of decoupling cells in the remaining area of each sub-area. In other words, the processor 110 may average the decoupling cell utilization among the plurality of sub-regions through the script 121 such that the standard cell utilization of each of the plurality of sub-regions is positively correlated with the decoupling cell utilization.
In addition, in the present embodiment, after the processor 110 inserts at least one decoupling unit in at least one of the plurality of sub-regions, the processor 110 may further determine whether the number of decoupling units in the whole of the plurality of sub-regions is greater than or equal to the global specified amount. In this regard, the processor 110 may end the insertion flow of decoupling cells when the number of overall decoupling cells for the plurality of sub-regions is greater than or equal to the globally specified amount. When the number of integral decoupling cells of the plurality of sub-regions is not greater than or equal to the globally specified amount, the processor 110 may select at least one of the plurality of sub-regions to supplement insertion of the at least one decoupling cell. In this regard, in the present embodiment, the processor 110 may preferentially select the sub-region having the most standard cells among the plurality of sub-regions to insert at least one decoupling cell, but the present invention is not limited thereto. In this way, for a sub-region with more standard cells, the decoupling cells can be relatively increased to help improve the voltage drop violation of this sub-region.
Additionally, in one embodiment, storage 120 is, for example, a computer-readable storage medium. The computer-readable storage medium stores instructions and the instructions are executable by the processor 110 to implement the chip design method as described above.
For example, referring to fig. 3 to 6 in combination, fig. 3 to 6 are layout effect diagrams of chips according to an embodiment of the invention. The processor 110 may execute a layout plan to generate a layout effect of the module 300 of the chip shown in fig. 3, wherein the module 300 may include a plurality of standard cells 310_1 to 310_8, including a standard cell 310_1, a standard cell 310_2, a standard cell 310_3, a standard cell 310_4, a standard cell 310_5, a standard cell 310_6, a standard cell 310_7, and a standard cell 310_8. Next, as shown in fig. 4, the processor 110 may divide the layout range of the module 300 of the chip into four sub-areas 301-304, including sub-area 301, sub-area 302, sub-area 304 and sub-area 304, according to a preset division number. The sub-areas 301-304 have the same layout area. Moreover, the processor 110 may analyze the four sub-areas 301-304 one by one to calculate the area ratio of the standard cells of each of the sub-areas 301-304. For this, the standard cell utilization of the sub-region 301 is, for example, 50%. The standard cell utilization of the sub-area 302 is for example 20%. The standard cell utilization of the sub-region 303 is for example 20%. The standard cell utilization of the sub-region 304 is for example 10%. As shown in fig. 4 to 6, the sub-region 301 may include a standard cell 310_1, a standard cell 310_2, a standard cell 310_3, the sub-region 302 may include a standard cell 310_4, a standard cell 310_5, the sub-region 303 may include a standard cell 310_6, a standard cell 310_7, and the sub-region 304 may include a standard cell 310_8.
Next, the processor 110 may insert a corresponding (area) ratio of decoupling units 320_1 to 320_8 into each of the sub-areas 301 to 304 according to the area ratio of the standard units of each of the sub-areas 301 to 304, including the decoupling units 320_1, 320_2, 320_3, 320_4, 320_5, 320_6, 320_7, and 320_8. For this, the subregion 301 is, for example, populated with decoupling cells of 50% of the total decoupling cell area. The sub-area 302 for example inserts decoupling cells of 20% of the total decoupling cell area. The sub-region 303 for example inserts decoupling cells of 20% of the total decoupling cell area. The sub-area 304 for example inserts decoupling cells of 10% of the total decoupling cell area. As shown in fig. 5, sub-region 301 may be inserted into decoupling cells 320_1, 320_2, 320_3, sub-region 302 may be inserted into decoupling cells 320_4, 320_5, sub-region 303 may be inserted into decoupling cells 320_6, 320_7, and sub-region 304 may be inserted into decoupling cells 320_8. In contrast, if any of the sub-regions 301 to 304 cannot be inserted with all the decoupling units to be inserted, the processor 110 may insert a part of the decoupling units to be inserted into the sub-region and stop the insertion of the decoupling units into the sub-region.
The processor 110 may then determine whether the number of global decoupling units for sub-regions 301-304 is greater than or equal to the global specified amount. In this regard, as shown in fig. 6, when the number of the overall decoupling cells of the sub-regions 301 to 304 is not greater than or equal to the globally specified amount, the processor 110 may preferably select the sub-region 301 having the most standard cells to insert the decoupling cell 320_9. In this regard, and so on, if the sub-region 301 cannot be inserted into the decoupling cell any more, the processor 110 selects the sub-region 302 or 303 having the second multi-standard cell to insert the decoupling cell 320_9. Accordingly, the decoupling unit can be effectively and automatically appropriately allocated to be inserted into each of the plurality of sub-regions of the chip to effectively improve the voltage drop violation of the local region of the chip.
Note that fig. 3 to 6 are schematic views showing only the occupation of the standard cells and the decoupling cells in each sub-area, and the area of each cell is not limited to the same size as that shown in fig. 3 to 6.
In summary, the chip design method and the chip design system of the present invention can implement the automatic and simple-operation decoupling unit insertion work in the chip design process by designing a specific script. The invention can realize script through tool command language, can be realized on any editing platform, and can be realized without using an electronic design automation tool additionally. The invention can effectively consider the standard unit utilization rate of each subarea by dividing the subareas of the chip, and can reasonably insert (put) the decoupling units. Therefore, the decoupling unit can fully utilize each decoupling unit to the maximum extent to improve the voltage drop violation condition of each subarea, and unnecessary power consumption can be effectively reduced.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (8)

1. A chip design method, comprising:
Carrying out layout planning;
Executing a script to divide the chip into a plurality of sub-regions;
Calculating a plurality of standard cell utilization rates of the plurality of sub-areas; and
Inserting at least one decoupling cell into at least one of the plurality of sub-regions according to the standard cell utilization of each of the plurality of sub-regions, wherein the standard cell utilization of each of the plurality of sub-regions is positively correlated with decoupling cell utilization;
after at least one decoupling unit is inserted into at least one of the plurality of sub-regions, further comprising:
Judging whether the number of the integral decoupling units of the plurality of subareas is larger than or equal to a global specified amount; and
When the number of the integral decoupling cells of the plurality of sub-regions is not greater than or equal to the globally specified amount, at least one of the plurality of sub-regions is selected to supplement insertion of at least one decoupling cell.
2. The chip design method according to claim 1, wherein the step of calculating the plurality of standard cell utilizations of the plurality of sub-regions comprises:
and calculating the proportion of the areas of the standard cells of each of the plurality of subareas to the area of the corresponding subarea.
3. The chip design method according to claim 2, wherein the step of inserting the at least one decoupling cell in the at least one of the plurality of sub-regions according to the standard cell utilization of each of the plurality of sub-regions comprises:
inserting a corresponding proportion of the at least one decoupling cell in the at least one of the plurality of sub-regions according to the proportion of the standard cell area of each of the plurality of sub-regions.
4. The chip design method according to claim 2, wherein the standard cell comprises a logic circuit.
5. The chip design method according to claim 1, wherein the step of selecting the at least one of the plurality of sub-regions to complement the insertion of the at least one decoupling cell comprises:
the sub-region of the plurality of sub-regions having the most standard cells is preferentially selected for insertion of the at least one decoupling cell.
6. The chip design method according to claim 1, wherein the step of executing the script comprises:
And executing the script after the wiring flow of the layout planning.
7. A computer-readable storage medium storing instructions that are executed by a processor to implement the chip design method of any one of claims 1 to 6.
8. A chip design system, comprising:
A processor; and
A storage device coupled to the processor and configured to store a script,
Wherein the processor performs layout planning, and executes a script to divide the chip into a plurality of sub-regions,
Wherein the processor calculates a plurality of standard cell utilizations of the plurality of sub-regions and inserts at least one decoupling cell in at least one of the plurality of sub-regions according to the standard cell utilization of each of the plurality of sub-regions, wherein the standard cell utilization of each of the plurality of sub-regions is positively correlated with the decoupling cell utilization; after at least one decoupling unit is inserted into at least one of the plurality of subareas, judging whether the number of the integral decoupling units of the plurality of subareas is larger than or equal to a global specified amount; when the number of the integral decoupling cells of the plurality of sub-regions is not greater than or equal to the globally specified amount, at least one of the plurality of sub-regions is selected to supplement insertion of at least one decoupling cell.
CN202410638159.XA 2024-05-22 2024-05-22 Chip design method, chip design system, and readable storage medium Active CN118211555B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410638159.XA CN118211555B (en) 2024-05-22 2024-05-22 Chip design method, chip design system, and readable storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410638159.XA CN118211555B (en) 2024-05-22 2024-05-22 Chip design method, chip design system, and readable storage medium

Publications (2)

Publication Number Publication Date
CN118211555A CN118211555A (en) 2024-06-18
CN118211555B true CN118211555B (en) 2024-09-20

Family

ID=91449437

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410638159.XA Active CN118211555B (en) 2024-05-22 2024-05-22 Chip design method, chip design system, and readable storage medium

Country Status (1)

Country Link
CN (1) CN118211555B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013045339A (en) * 2011-08-25 2013-03-04 Renesas Electronics Corp Placement and routing device
CN113515915A (en) * 2021-04-23 2021-10-19 成都海光集成电路设计有限公司 Method, device, equipment and storage medium for inserting filling unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7171645B2 (en) * 2002-08-06 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device
CN117952058A (en) * 2022-10-21 2024-04-30 中芯国际集成电路制造(上海)有限公司 Chip layout structure, layout method and chip
CN116578451A (en) * 2023-05-12 2023-08-11 上海壁仞智能科技有限公司 Method, system, device, medium for reducing violations due to voltage drop
CN117832205A (en) * 2023-12-28 2024-04-05 飞腾信息技术有限公司 Chip packaging structure and electronic equipment

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013045339A (en) * 2011-08-25 2013-03-04 Renesas Electronics Corp Placement and routing device
CN113515915A (en) * 2021-04-23 2021-10-19 成都海光集成电路设计有限公司 Method, device, equipment and storage medium for inserting filling unit

Also Published As

Publication number Publication date
CN118211555A (en) 2024-06-18

Similar Documents

Publication Publication Date Title
US5724250A (en) Method and apparatus for performing drive strength adjust optimization in a circuit design
US7137094B2 (en) Method for reducing layers revision in engineering change order
EP1305744B1 (en) Method and system for hierarchical metal-end, enclosure and exposure checking
US5764532A (en) Automated method and system for designing an optimized integrated circuit
US8219959B2 (en) Generating integrated circuit floorplan layouts
US20020029371A1 (en) Methods, systems, and computer program products for designing an integrated circuit that use an information repository having circuit block layout information
US20060242613A1 (en) Automatic floorplanning approach for semiconductor integrated circuit
US8522185B1 (en) Method for placement and routing of a circuit design
CN106775455A (en) In-line memory block with adjustable memory boundary
JP4955484B2 (en) Circuit design apparatus, circuit design method, and circuit design program
CN118211555B (en) Chip design method, chip design system, and readable storage medium
US7865852B2 (en) Method for automatically routing multi-voltage multi-pitch metal lines
JP4272647B2 (en) Layout method of semiconductor integrated circuit device and layout program thereof
CN113705141B (en) FPGA chip verification method, system, equipment and storage medium
Kuo et al. Engineering change using spare cells with constant insertion
US6260184B1 (en) Design of an integrated circuit by selectively reducing or maintaining power lines of the device
JP2007258215A (en) Program, apparatus and method of cell arrangement
US10643020B1 (en) System and method to estimate a number of layers needed for routing a multi-die package
JP2009231675A (en) Design method of semiconductor integrated circuit, design program of semiconductor integrated circuit, and design support device of semiconductor integrated circuit
JP5515255B2 (en) Automatic wiring device, automatic wiring method and automatic wiring program
US20040163068A1 (en) Logic circuit diagram input device
US10970452B2 (en) System for designing semiconductor circuit and operating method of the same
US9454632B1 (en) Context specific spare cell determination during physical design
JP2002217300A (en) Cell arrangement method
CN114662446A (en) Wiring optimization method for reducing dynamic power consumption

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant