CN118170439A

CN118170439A - Exception handling method and device

Info

Publication number: CN118170439A
Application number: CN202211582330.7A
Authority: CN
Inventors: 李国柱; 陈立福; 周若愚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2024-06-11
Also published as: WO2024120070A1

Abstract

The embodiment of the application provides an exception handling method and device, which relate to the technical field of computers, and comprise the following steps: running a plurality of block instructions corresponding to the computing task to execute the computing task; wherein each block instruction of the plurality of block instructions comprises at least one sub-task for implementing a computing task; at least one block instruction of the plurality of block instructions further includes a second instruction; the second instruction is used for indicating the function of at least one instruction in the block instructions to be accessing the appointed memory address; if the abnormal operation is detected, and the current block instruction currently operated contains a second instruction, stopping operating the current block instruction; and determining a first jump block instruction corresponding to the current block instruction with the abnormal operation, and operating the first jump block instruction, wherein the first jump block instruction is one of a plurality of block instructions and is executed after the current block instruction with the abnormal operation. The embodiment of the application can realize fixup processing without creating and searching fixup record tables, and is more efficient.

Description

Exception handling method and device

Technical Field

The embodiment of the application relates to the technical field of computers, in particular to an exception handling method and device.

Background

During the process of executing the computing task by the kernel of the operating system, exception repair fixup is used to process access exceptions in the computing task with respect to the specified memory address. fixup may include: the kernel accesses the appointed memory address indicated by the instruction in the calculation task, and if the corresponding hardware such as a processor is triggered to check the abnormal access result of the appointed memory address, the kernel performs the jump operation: and stopping executing the associated code of the instruction in the code of the computing task, and transferring the appointed code in the code of the computing task to ensure the safety of continuous execution and access of the computing task, thereby improving the user experience.

In the related art, the kernel of the operating system generally establishes fixup a record for storing the position of the associated code in the code of the computing task and the position of the specified code corresponding to the associated code in the code of the computing task, and then performs the jump operation by searching fixup the record.

However, access exceptions with respect to a specified memory address in a computing task are likely to occur multiple times, and the kernel lookup fixup records are typically traversal queries, resulting in inefficient exception handling.

Disclosure of Invention

In order to solve the technical problems, the application provides an exception handling method and an exception handling device. In the exception handling method, fixup processing is realized through the block instruction and the second instruction contained in the block instruction, and no additional establishment and search of fixup records are needed, so that the exception handling efficiency is improved.

In a first aspect, an embodiment of the present application provides an exception handling method, including: running a plurality of block instructions corresponding to the computing task to execute the computing task; the block instructions are respectively used for realizing different subtasks in the computing task; each block instruction of the plurality of block instructions includes at least one first instruction for implementing a subtask; at least one block instruction of the plurality of block instructions further includes a second instruction; the second instruction is used for indicating the function of at least one instruction in the block instructions to be accessing the appointed memory address; if the abnormal operation is detected, and the current block instruction currently operated contains a second instruction, stopping operating the current block instruction; and determining a first jump block instruction corresponding to the current block instruction with the abnormal operation, and operating the first jump block instruction, wherein the first jump block instruction is one of a plurality of block instructions and is executed after the current block instruction with the abnormal operation.

Illustratively, the current block instruction is the currently running block instruction. The specified memory address may generally include a memory address with access authority, a memory address allocated by adopting a delay loading mechanism, a misaligned memory address, a memory address which is uncertain whether to be accessed or not, and the like, which may be specifically set according to application requirements, and the embodiment of the present application is not limited thereto. That is, the exception corresponding to the specified memory address that can be processed by fixup is usually an expected exception, and the purpose is to achieve the effect that the code of the computing task is more concise and efficient to execute by triggering the page fault and skipping the execution of the associated code.

In the embodiment of the application, at least one block instruction of a plurality of block instructions respectively used for realizing different subtasks in the computing task comprises a second instruction for indicating that the block instruction has access to the appointed memory address. In this way, in the process of executing the computing task by executing the plurality of block instructions, if the currently running block instruction has an abnormal operation and includes the second instruction, it indicates that the execution of the block instruction can be directly stopped, and the execution jumps to the first jump block instruction corresponding to the block instruction to implement fixup processing, without additionally establishing and searching fixup records, thereby improving the efficiency of exception processing.

According to a first aspect, each block instruction of the plurality of block instructions includes a block header and a block body; the block header is used for indicating attribute information of the block instruction, and the block body comprises a first instruction in the block instruction; the second instruction is contained within the block header or the block body.

For example, the attribute information of the block instruction may be information such as a relationship between the block instruction and other block instructions in the plurality of block instructions, and the block body provides a specific implementation code of the subtask corresponding to the block instruction, that is, the first instruction. The second instruction is contained in the block header, i.e. the attribute information belonging to the block instruction. The second instruction is included in the block body and corresponds to an attribute of the block body, and is not used for realizing the subtask, but indicates that an instruction for accessing the specified memory address exists in the first instruction in the block body, so that the electronic device can perform fixup processing according to the second instruction. In one example, the second instruction in the block may be located in the first row of the block code for ease of viewing and management, etc.

According to the embodiment of the application, the first jump block instruction is contained in the block head and is not limited by a specific instruction in the block body, and the processor such as the first-level hardware for scheduling the block head in the computing resource of the CPU can finish exception processing without additional interaction with the second-level hardware for scheduling the block body in the computing resource of the CPU, so that the method is more efficient. The first jump block instruction is contained in the block body without additionally setting the block heads, so that the block heads of different block instructions are more unified, and batch processing based on the block heads is facilitated.

According to the first aspect, or any implementation manner of the first aspect, the second instruction is further configured to indicate a storage location of the first skip block instruction; determining a first jump block instruction corresponding to a current block instruction with abnormal operation, including: and acquiring a first jump block instruction according to the storage position.

For each block instruction, the block header of the block instruction corresponds to the block body, and based on this, the storage location of the block instruction may be the storage location of the block instruction header (such as the head address of the memory space occupied by the block header). According to the storage location, the first skip block instruction is obtained, for example, the first skip block instruction in the memory space corresponding to the storage location may be read.

According to the embodiment of the application, the first jump block instruction is determined according to the storage position of the first jump block instruction indicated by the second instruction, so that the first jump block instruction is executed in a jumping manner under the condition that the current jump block instruction runs abnormally, and the user experience is improved.

According to the first aspect, or any implementation manner of the first aspect, determining a first skip block instruction corresponding to the current block instruction with abnormal operation includes: determining an nth block instruction after a current block instruction with abnormal operation from a plurality of block instructions to obtain a first jump block instruction; wherein n is an integer greater than or equal to 1; the plurality of block instructions are ordered in an order of execution.

According to the embodiment of the application, the first jump block instruction is determined according to the execution sequence of the plurality of block instructions, so that the method and the device are more convenient.

According to a first aspect, or any implementation manner of the first aspect, according to the first aspect, or any implementation manner of the first aspect, before detecting that the current block instruction is abnormal and the current running current block instruction includes the second instruction, the method further includes: receiving an operation result of an instruction interrupt instruction of a current block of instructions; at least one block instruction of the plurality of block instructions further includes an predicate instruction; if the operation result is false, determining that the operation is abnormal.

According to a first aspect, or any implementation manner of the first aspect, according to the first aspect, or any implementation manner of the first aspect, if an abnormal operation is detected, and a current block instruction currently running includes a second instruction, the method further includes: obtaining abnormal information of abnormal operation; storing exception information through a preset register indicated by a third instruction in the current abnormal running block instruction; at least one block instruction of the plurality of block instructions further includes a third instruction.

According to the embodiment of the application, the register for storing the abnormal information is configured through the block head attribute of each block head or the corresponding block body attribute, so that the influence of the context difference of different block heads on the abnormal information is not involved, the context executed by the block head is not required to be stored, and the register for storing the context is not required to be additionally arranged, so that the method is more convenient and efficient. In addition, the embodiment of the application can directly determine the pre-configured register according to the block head attribute or the block body attribute in the current block instruction running abnormally, namely the second instruction, without determining the register for returning abnormal information according to fixup records or modifying the data stored in the register according to different abnormal information, thereby being more efficient.

According to the first aspect, or any implementation manner of the first aspect, after determining a first skip block instruction corresponding to the current block instruction with abnormal operation, and executing the first skip block instruction, the method further includes: if the first jump block instruction is detected to run abnormally and the first jump block instruction running abnormally contains a second instruction, sending a control instruction to a system register through a kernel; the system register is used for determining a second jump block instruction corresponding to the first jump block instruction with abnormal operation; the control instruction is used for indicating whether to determine the second jump block instruction or not; the second skip block instruction is one of a plurality of block instructions and is executed after the first skip block instruction that is running abnormally.

According to a first aspect, or any implementation of the first aspect above, according to the first aspect, or any implementation of the first aspect above, the second instruction is further configured to indicate that at least one block instruction of the plurality of block instructions has atomicity; wherein the atomicity includes that each instruction contained in the block instruction corresponding to the second instruction is completed to run.

Illustratively, the atomicity of a block instruction means that the action indicated by each instruction in the block instruction occurs, and the access result of each instruction in the block instruction to the memory address is output in a unified way and is not modified by the block instructions except the block instruction.

The exception handling mode provided by the embodiment of the application is realized by stopping executing the current block instruction for running exception and jumping to execute the first jumping block instruction which is different from the current block instruction for stopping executing, and the result of reading or updating the memory address by the block instruction is not modified, so that the exception handling mode can be suitable for the block instruction with atomicity, and the application scene of an exception handling method is expanded.

In a second aspect, an embodiment of the present application provides an exception handling apparatus, including: an execution module to execute a plurality of block instructions to perform a computing task; the block instructions are respectively used for realizing different subtasks in the computing task; each block instruction of the plurality of block instructions includes at least one first instruction for implementing a subtask; at least one block instruction of the plurality of block instructions further includes a second instruction; the second instruction is used for indicating the function of at least one instruction in the block instructions to be accessing the appointed memory address; the exception handling module is used for stopping running the current block instruction if the running exception is detected and the current block instruction which is currently running contains a second instruction; and determining a first jump block instruction corresponding to the current block instruction with the abnormal operation, and operating the first jump block instruction, wherein the first jump block instruction is one of a plurality of block instructions and is executed after the current block instruction with the abnormal operation.

According to a second aspect, each block instruction of the plurality of block instructions includes a block header and a block body; the block header is used for indicating attribute information of the block instruction, and the block body comprises a first instruction in the block instruction; the second instruction is contained within the block header or the block body.

According to a second aspect, or any implementation of the second aspect above, the second instruction is further configured to indicate a storage location of the first skip block instruction; the exception handling module is specifically configured to: and acquiring a first jump block instruction according to the storage position.

According to a second aspect, or any implementation manner of the second aspect, the exception handling module is specifically configured to: determining an nth block instruction after a current block instruction with abnormal operation from a plurality of block instructions to obtain a first jump block instruction; wherein n is an integer greater than or equal to 1; the plurality of block instructions are ordered in an order of execution.

According to a second aspect, or any implementation manner of the second aspect, the exception handling module is specifically configured to: before detecting that the operation is abnormal and the current block instruction currently operated contains the second instruction, receiving an operation result of the interrupt instruction of the current block instruction; at least one block instruction of the plurality of block instructions further includes an predicate instruction; if the operation result is false, determining that the operation is abnormal.

According to a second aspect, or any implementation manner of the second aspect, the exception handling module is specifically configured to: acquiring abnormal information of the operation abnormality after detecting that the operation abnormality exists and the current block instruction currently operated contains a second instruction; storing exception information through a preset register indicated by a third instruction in the current abnormal running block instruction; at least one block instruction of the plurality of block instructions further includes a third instruction.

According to a second aspect, or any implementation manner of the second aspect, the exception handling module is further configured to: after determining a first skip block instruction corresponding to the current block instruction and running the first skip block instruction, if the first skip block instruction is detected to run abnormally and contains a second instruction, sending a control instruction to a system register through a kernel; the system register is used for determining a second jump block instruction corresponding to the first jump block instruction with abnormal operation; the control instruction is used for indicating whether to determine the second jump block instruction or not; the second skip block instruction is one of a plurality of block instructions and is executed after the first skip block instruction that is running abnormally.

According to a second aspect, or any implementation of the second aspect above, the second instruction is further configured to indicate that at least one block instruction of the plurality of block instructions has atomicity; wherein the atomicity includes that each instruction contained in the block instruction corresponding to the second instruction is completed to run.

Any implementation manner of the second aspect and the second aspect corresponds to any implementation manner of the first aspect and the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation manner of the second aspect may be referred to the technical effects corresponding to the first aspect and any implementation manner of the first aspect, which are not described herein.

In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a transceiver; a memory for storing one or more programs; the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method as in the first aspect and any one of the implementations of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer readable medium storing a computer program comprising instructions for performing the method of the first aspect or any possible implementation of the first aspect.

In a fifth aspect, embodiments of the present application provide a computer program comprising instructions for performing the method of the first aspect or any possible implementation of the first aspect.

In a sixth aspect, an embodiment of the present application provides a chip, where the chip includes a processing circuit and a transceiver pin. Wherein the transceiver pin and the processing circuit communicate with each other via an internal connection path, the processing circuit performing the method of the first aspect or any one of the possible implementation manners of the first aspect to control the receiving pin to receive signals and to control the transmitting pin to transmit signals.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is an exemplary diagram of an execution queue in a superscalar CPU, shown schematically;

FIG. 2 is a diagram illustrating a comparison of the architecture of a conventional CPU and a block CPU;

FIG. 3 is a schematic diagram of an exemplary block instruction-based code architecture;

FIG. 4 is an organization of fixup codes shown by way of example;

Fig. 5 is a block diagram of an electronic device 500 according to an embodiment of the present application;

FIG. 6 is a flowchart of an exception handling method according to an embodiment of the present application;

FIG. 7 is an exemplary diagram of an organization of fixup codes based on block instructions provided by an embodiment of the present application;

Fig. 8 is a block diagram of an exception handling apparatus according to an embodiment of the present application.

Detailed Description

In order to facilitate understanding of the present embodiment, some technical terms and related techniques related to the present embodiment will be described first:

Superscalar CPU (central processing unit): and a CPU for executing a plurality of instructions at the same time to improve the running efficiency and the utilization rate of the computing resources in the CPU. For example, the CPU breaks down the computing task into a plurality of instructions for execution on different threads, and each thread independently uses different computing resources in the CPU, thereby improving the utilization rate of the computing resources in the CPU. For each thread, the next thread to execute may be predicted before the thread completes execution. That is, when the current instruction is not executed, the scheduled execution instruction is started and the execution is put into execution. Thus, if the prediction is correct, the execution result of the post-execution instruction can be directly used, so that the operation efficiency of the instruction is improved. If the prediction is wrong, the execution result of the predicted post-execution instruction can only be abandoned, and the correct instruction to be executed is redetermined from the instruction with the wrong prediction.

Typically, superscalar CPUs create an execution queue for managing non-executed completed instructions. Fig. 1 is an exemplary diagram of an execution queue in a superscalar CPU, which is schematically illustrated. As shown in fig. 1, the execution queue includes: an instruction record 101 for indicating the completed execution (discarded) instruction; an executing instruction record 102 for indicating a currently executing instruction; and determining an invalid instruction record 103 for indicating a mispredicted instruction. Wherein the instruction indicated by the instruction record 103 determined to be invalid is a post-execution instruction relative to the instruction indicated by the executing instruction record 102. After the superscalar CPU determines that an instruction record is invalid (e.g., instruction record 103 in fig. 1), the subsequent instruction records (e.g., instruction record 104 in fig. 1) are also all deleted, and valid instruction records are refilled from where they were invalid (e.g., instruction record 103 in fig. 1).

However, from the standpoint of code logic, longer-span instruction execution predictions may be made in the scheduling of instructions to reduce the deletion and refilling of instruction records with efficient instruction records, improving efficiency. For example, as shown in table 1 below:

It is assumed that, when the instruction "If check_condition ()" is not executed, the predicted execution instruction is the instruction "do_conditional_business" and the instruction "do_general_business" in this order. At this time, if the instruction "If check_condition ()" completes execution and it is detected that the instruction "do_conditional_bussiness" is not required to be executed, the execution result of the instruction "do_conditional_bussiness" may be discarded without discarding the execution result of the instruction "do_general_bussiness". That is, from the standpoint of code logic, the instruction "do_general_business" may be executed without deleting an instruction after an invalid instruction and refilling a valid instruction record as in the superscalar CPU shown in fig. 1. Based on this, the code of the computational task may be implemented with block instructions to ensure longer-span instruction execution predictions, such as ensuring that instruction "do_general_business" may be executed.

Block instruction: instructions obtained by dividing the code of the computing task into different code blocks, one block instruction corresponding to each code block. Each block instruction is used to implement one of the subtasks in the computing task. For example, the CPU may divide the code schedule for the computing task into two layers by using a block instruction, where the first layer is a block description, also referred to as a block header, for indicating a dependency relationship between a block instruction corresponding to the block header and other block instructions, and the second layer is a block body, for implementing execution of the block instruction, and includes a code block in the block instruction for implementing a corresponding subtask, where the code block includes at least one instruction. Based on this, the code of computing task 2 may be as shown in table 2 below:

Block1 (attr= …) to Block3 (attr= …) in table 2, i.e., a Block header, is used to define a register used by a Block instruction corresponding to the Block header and whether to skip, and there is no more subtask execution detail. The scheduling of the block header is called block header scheduling, and the execution of the block instruction corresponding to the block header, that is, the block body, includes a specific set of instructions.

Finger (Instruction Fetch, IF): i.e., fetching an instruction, generally refers to the process in which the CPU reads an instruction from main memory (CPU's memory) and stores it in an instruction register. The value in a Program Counter (PC) is used to indicate the memory address in main memory of the instruction to be executed in the current instruction execution cycle. At the end of the fetch operation, the PC points to the instruction to be fetched in the next cycle.

Decoding (Instruction Decode, ID): the instruction decoder splits and interprets instructions stored in the instruction registers, identifies different instruction categories and methods of fetching operands, to obtain a series of control signals that are transmitted to the execution units.

Fig. 2 is a diagram illustrating the architecture of a conventional CPU and a block CPU. As shown in fig. 2, a conventional CPU is a CPU that schedules code that does not implement a computing task with block instructions. The conventional CPU performs code scheduling of calculation tasks based on the execution queue shown in fig. 1. Correspondingly, the instruction fetching and decoding logic of the traditional CPU is a hardware logic circuit or a processing circuit capable of running software for realizing instruction fetching and decoding, instruction sequences are fetched and decoded according to the instruction records in the execution queue, and then the computing unit of the traditional CPU executes the instructions indicated by the instruction records in the execution queue. This completes one execution cycle of the instruction: finger-decode-execute.

Still referring to FIG. 2, a block CPU is a CPU that schedules code for implementing computing tasks using block instructions. The difference from a conventional CPU is that the execution queue in a block CPU is a head of block execution queue, each instruction record in the head of block execution queue indicating a block instruction, i.e., at least one instruction. Correspondingly, the instruction fetching and decoding logic of the block CPU fetches and decodes the block header sequence according to the instruction record in the block header execution queue, and then the block engine of the block CPU executes the block instruction indicated by the instruction record in the block header execution queue. This completes one execution cycle of the block instruction, i.e., at least one instruction: finger-decode-execute. It will be appreciated that a block header in the sequence of block headers is used to indicate a block instruction. The block engine corresponding to each block instruction executes the block body in the block instruction, does not have a relation with other block instructions, is simpler to realize, and can improve the processing capacity of the CPU without greatly increasing the complexity of the CPU by increasing the number and the types of the block engines. In addition, the efficiency of the scheduler for the instruction queues of the same size for the block CPU can be improved.

For ease of understanding, the following is a comparative example of the code of the calculation task handled by the conventional CPU and the code of the calculation task handled by the block CPU in conjunction with table 3.

As shown in table 3 below, the computing task 3 is a multiplication of 10 by each element in the array, and compared with a conventional reduced instruction set computer (Reduced Instruction Set Computer, RISC, a computer with a shorter instruction length) instruction, the Block instruction corresponds to an instruction group obtained by dividing the code (for example, the first Block instruction is a Block header "Block input (r 1, r 2), br.cond=1f" to a first Block end "for implementing a subtask related to multiplication computation in the computing task 3), and each instruction group includes at least one instruction (for example, a second Block instruction" Block br=end "for implementing a subtask for returning a computation result in the computing task 3).

Fig. 3 is a schematic diagram of an exemplary block instruction-based code structure. As shown in fig. 3, block header1 to block header3 and the like correspond to at least one of block body minsn to block body minsnX, respectively. That is, the blocks corresponding to different block heads can be overlapped to realize code reuse and reduce the code volume. For example, block header1 corresponds to block bodies minsn to minsn, and block header3 corresponds to block bodies minsn1 to minsn. In addition, the specific code structure of the instructions in the block, that is, the instructions included in the block body, may be set according to the application requirements, which is not limited by the embodiment of the present application. For example, the intra-block instruction of the block instruction in the example of table 3 above is in the form of the formula: each instruction is provided with an output register, which is used by other instruction offsets (e.g., T #1 indicates the output of the previous instruction).

And (3) a kernel: the system is based on a first layer of software expansion of hardware, provides a part of software for safely accessing computer hardware for a plurality of application programs, and is responsible for managing processes, memory, device drivers, files and network systems of an operating system, so as to determine the performance and stability of the system.

Delay loading mechanism: when the operating system allocates memory for the access request of the user, only a virtual address space is allocated, an actual physical address space is not allocated, and the physical address space is allocated through page fault (page fault) triggered when the virtual address space is accessed, so that the memory pressure is reduced.

Memory address misalignment: the initial address in the memory address carries out modular operation on the length of the data type, if the result is 0, the memory address accessed at this time is aligned, otherwise, the memory address is not aligned.

Anomaly repair fixup:

in the process that the kernel of the operating system executes the computing task corresponding to the application program, a certain instruction in the code of the computing task indicates to access the appointed memory address, the kernel can directly access the appointed memory address to trigger hardware such as a processor to check whether the computing task can access the appointed memory address, if the computing task cannot access the appointed memory address, the hardware feeds back a checking result of the memory access abnormality corresponding to the appointed memory address to the kernel, which is equivalent to triggering the page fault. In this way, the kernel may perform a jump operation: and stopping executing the associated code of the instruction in the code of the computing task, and transferring the appointed code in the code of the computing task to ensure the safety of continuous execution and access of the computing task, thereby improving the user experience. The specified memory address may generally include a memory address with access authority, a memory address allocated by adopting a delay loading mechanism, a misaligned memory address, a memory address which is uncertain whether to be accessed or not, and the like, which may be specifically set according to application requirements, and the embodiment of the present application is not limited thereto. That is, the exception corresponding to the specified memory address that can be processed by fixup is usually an expected exception, and the purpose is to achieve the effect that the code of the computing task is more concise and efficient to execute by triggering the page fault exception and skipping the execution of the associated code.

Illustratively, as shown in Table 4 below, instructions "Ld r3, [ r2,40]" in the code of computing task 4 indicate that accessed memory address r2+40 is an address that is indeterminate whether it is accessible, i.e., a specified memory address. In this regard, the core may record the address and execute the instruction, i.e., access memory address r2+40. If the core detects that an exception has occurred and is caused by the address, for example, the hardware feeds back an access exception to memory address r2+40, the core skips the remaining execution flow, i.e., execution of the associated code of the instruction. Thus, the exception checking behavior is submitted to hardware processing (whether the accessed address is valid or not is checked by the hardware originally) without the effect that the kernel stops code execution due to exception, and the user experience can be improved. As can be seen, fixup applies to the execution logic of superscalar CPU on instructions: if the predicted instruction cannot be executed, the execution of the instruction can be stopped, and the executable instruction can be continuously executed.

The exception handling procedure in the above example may be implemented by macro "Fixup" shown in table 4. For example, fig. 4 is an organization of fixup codes as exemplarily shown. As shown in fig. 4 and table 4, the command fixup, that is, the command that needs to be processed in fixup (for example, "Ld r3, [ r2,40] in table 4), is required, and the fixup repair command fixup is the location of the command to be executed in a jump (for example, the location" 1f "of the command" 1: "corresponding to the sub-branch of the data boundary crossing processing in table 4), where the location of the command may be, for example, the number of lines of the command in the code, which may be specifically set according to the application requirement, and the implementation of the present application is not limited. In this regard, the code of the computing task 4 may be augmented with a macro "Fixup" for instructions "Ld r3, [ r2,40]" to obtain instructions "Fixup Ld r, [ r2,40],1f" to implement exception handling based on fixup. Specifically, the kernel instructs the compiler, based on macro "Fixup", to build a data item, such as the entry in the fixup table in fig. 4, at the time of compiling the code of the computing task, for recording the memory address (e.g., memory address r2+40) that needs to be processed by fixup, and the location of the jump executed instruction in fixup (e.g., "1f" in table 4). Thus, if instruction "Fixup Ld r, [ r2,40],1f" triggers a memory access exception when the kernel executes the code for the computing task in Table 4, the fixup table may be looked up and the exception handled according to the lookup result: the jump execution table 4 "data out-of-bound processing sub-branch" corresponds to the instruction, and the associated code of the instruction "Fixup Ld r, [ r2,40],1f" is skipped, namely the code of the instruction "Fixup Ld r, [ r2,40],1f" to the instruction "br end". In one example, the association code described above generally performs a common function with instructions that require exception handling, such as the association code and instructions "Fixup Ld r, [ r2,40],1f" in Table 4 are each used to multiply groups of occupants.

However, in the exception handling, an entry needs to be added to fixup tables for each instruction that needs fixup handling, and a table needs to be looked up fixup (as shown in fig. 4, which is a traversal query looking up from the first entry). However, the code of the computing task tends to have a larger volume, resulting in more entries in the fixup table, so that it takes more time to add entries or search the fixup table, and there is a problem of low exception handling efficiency.

In another example, a register reg_ba may be added in advance in the CPU for saving the storage location of the specified code. If an access violation occurs, the jump is made to the register specified by REG_BA. Thus, the cost of searching fixup tables is reduced by adding hardware to directly specify the position of the specified code which can be jumped to execute in the exception processing.

However, different contexts in the code corresponding to the computing task need to set different registers reg_ba, so that the registers reg_ba need to be modified continuously, and context switch information needs to be saved for switching the contexts of threads and the like, which also needs additional cost.

In view of the above problems, an embodiment of the present application provides an exception handling method. The exception handling method is applied to the electronic equipment, in the method, the code of the computing task comprises a plurality of block instructions for realizing different subtasks in the computing task, and at least one of the plurality of block instructions is preset with a second instruction for indicating the block instruction to access the appointed memory address. Thus, if an access exception occurs to the specified memory address during the execution of the block instruction, the execution of the block instruction can be directly stopped according to the second instruction, and the execution of the associated code and the skip operation can be stopped by skipping to the first skip block instruction corresponding to the block instruction fixup, so that fixup can be realized without additionally establishing and searching fixup records, thereby improving the exception handling efficiency. In addition, the scheme does not need to add a special hardware register, and does not need to modify the register aiming at different program contexts so as to realize fixup jump operation, which is more convenient.

Before the technical scheme of the embodiment of the application is described, the electronic equipment of the embodiment of the application is described with reference to the accompanying drawings. The embodiment of the application can be applied to electronic equipment such as computers, mobile terminals, wearable equipment, internet televisions, servers and the like. For example, fig. 5 is a block diagram of an electronic device 500 according to an embodiment of the present application. As shown in fig. 5, the electronic device 500 may include: a processor 501, communication lines 505, memory 503, storage medium 504, and some or all of the components of at least one communication interface 502.

The processor 501 is configured to execute the exception handling method provided in the subsequent embodiment of the present application.

In particular, the processor 501 may comprise a general purpose central processing unit (central processing unit, CPU), and the processor 501 may further comprise a microprocessor, a field programmable gate array (Field Programmable GATE ARRAY, FPGA), a digital signal processor (DIGITAL SIGNAL processing, DSP) or application-specific integrated circuit (ASIC), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.

The communication line 505 is used to connect the components in the electronic device 500. In particular, the communication lines 505 may include a data bus, a power bus, a control bus, a status signal bus, and the like. For clarity of illustration, however, the various buses are labeled as communication lines 505 in the drawing.

The memory 503 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The memory 503 may be separate and coupled to the processor 501 via a communication line 507505. Memory 503 may also be integrated with processor 501. Wherein the memory 503 stores computer instructions. The processor 501 may implement the exception handling method provided in the subsequent embodiments of the present application by executing computer instructions stored in the memory 503. Alternatively, the computer-executable instructions in this embodiment may be referred to as application program codes, which are not particularly limited in this embodiment.

The storage medium 504 is used for storing computer instructions and various data for implementing the technical solutions of the embodiments of the present application, so that when the electronic device 500 executes the exception handling method provided in the subsequent embodiments of the present application, the computer instructions and various data stored in the storage medium 504 are loaded into the memory 503, so that the processor 501 can implement the exception handling method provided in the embodiments of the present application by executing the computer instructions stored in the memory 503.

The communication interface 502 uses any transceiver-like electronic device for communicating with other devices or communication networks, such as ethernet, radio access network (radio access network, RAN), wireless local area network (wireless local area networks, WLAN), etc.

It should be understood that the electronic device 500 shown in fig. 5 is only one example of an electronic device, and that the electronic device 500 may have more or fewer components than shown in the figures, may combine two or more components, or may have a different configuration of components. The various components shown in fig. 5 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

The exception handling method provided by the embodiment of the present application is described below with reference to fig. 6 to 7.

Fig. 6 is a flowchart of an exception handling method according to an embodiment of the present application. As shown in fig. 6, the exception handling method provided in the embodiment of the present application, applied to an electronic device, may include, but is not limited to, the following steps:

s601, running codes of a computing task to execute the computing task, wherein the codes of the computing task comprise a plurality of block instructions which are respectively used for realizing a plurality of subtasks contained in the computing task; at least one of the plurality of block instructions is provided with a second instruction in advance, wherein the second instruction is used for indicating that the corresponding block instruction contains codes for accessing the appointed memory address.

The kernel of the electronic device may run code of the computing task to execute the computing task if execution instructions of the computing task are detected. This operation may be referred to above in fig. 2 for the prior description of the process of scheduling code by the block CPU to perform the computing task, and will not be described in detail herein. The block instructions may be referred to in the above-mentioned tables 2, 3 and 3, and will not be described herein. The specified memory address may generally include a memory address with access authority, a memory address allocated by adopting a delay loading mechanism, a misaligned memory address, a memory address which is uncertain whether to be accessed or not, and the like, which may be specifically set according to application requirements, and the embodiment of the present application is not limited thereto. That is, the exception corresponding to the specified memory address that can be processed by fixup is usually an expected exception, and the purpose is to achieve the effect that the code of the computing task is more concise and efficient to execute by triggering the page fault exception and skipping the execution of the associated code.

Based on this, the at least one block instruction includes code for accessing the specified memory address, and the electronic device may perform fixup processing on the at least one block instruction. Accordingly, a second instruction may be preset in the at least one block instruction, where the second instruction is used to indicate that the corresponding block instruction includes a code for accessing the specified memory address. That is, the second instruction may ensure that the electronic device performs fixup processing if it detects that the block of instructions has an access exception to the specified memory address. The access exception may be referred to as a specific exception, for example, a memory access out-of-range corresponding to a memory address with access authority, a page fault exception corresponding to a memory address allocated by a delayed loading mechanism, a misalignment exception corresponding to a misaligned memory address, a memory access out-of-range corresponding to a memory address with uncertainty of whether the memory access is accessible, and the like.

The second instruction may include a block header attribute in a block header, or a block instruction attribute in a block body, which may be specifically set according to an application requirement, which is not limited in the embodiment of the present application.

In one example, for the code of Block instruction based computing task 3, i.e., computing task 3 implemented by the Block instructions in table 3, at least one Block instruction, such as Block header "Block input (r 1, r 2), br.cond=1f", to the first "block.end" Block instruction, as shown in table 5 below, the second instruction may be a Block header attribute in the Block header: "attr= fixup, br= ret fixup _type= fallthrough". "attr= fixup" is used to indicate that the block instruction includes an instruction that accesses a specified memory address, and "br= ret fixup _type= fallthrough" is used to indicate a first skip block instruction that can continue to be executed when a memory access exception occurs in the block instruction (the first skip block instruction is described in subsequent S603 for a reasonable layout).

According to the embodiment of the application, the block instruction which needs to be processed by fixup is indicated by the block header attribute, and the method is not limited by the specific instruction content in the block instruction, so that the application scene of the exception handling method can be widened, and the convenience is improved. In addition, by adding the block header attribute, namely the attribute related to fixup, in the block header, the hardware used for executing the block header code in the hardware resource of the CPU (Central processing Unit) can be ensured, and in the process of executing the block header code, when the block instruction is abnormal, the first jump block instruction can be jumped to according to the block header attribute, and no additional interaction with the second level hardware is needed for jumping. The second-level hardware is hardware for executing the block body code in hardware resources of the CPU.

In one example, at least one Block instruction, such as a Block header "Block input (r 1, r 2), of Block instructions br.cond=1f" to the first "block.end", the second instruction may be a Block instruction attribute in the Block body: "set_ fixup _reg". For example, the instruction "set_ fixup _type" and "set_fix_address" in the block body indicate that fixup can be executed when an exception occurs in the block instruction corresponding to the block body, and the position of the first skip block instruction that can skip execution, respectively. In an alternative embodiment, the block instruction attributes may be located in the first row of the block body to facilitate distinction from the code in the block body that implements the subtasks.

According to the embodiment of the application, the second instruction can be the block instruction attribute in the block body, namely the instruction form in the block body, and the block head does not need to be subjected to additional attribute setting, so that the uniformity of the block head form can be improved, and the batch processing of the block head is facilitated.

S602, if the abnormal operation is detected, and the current block instruction currently operated contains a second instruction, stopping operation of the current block instruction.

And if the electronic equipment detects that the operation is abnormal and the current block instruction currently operated contains a second instruction in the process of operating the code of the calculation task to execute the calculation task, stopping operating the current block instruction. It will be appreciated that the current block instruction is the code of the computational task, i.e., the currently running block instruction of the plurality of block instructions.

Each block instruction of the computing task is used to implement a plurality of sub-tasks included in the computing task, respectively, and each block instruction includes at least one instruction (as described in the embodiment of table 3). That is, at least one instruction included in each block instruction implements the same subtask and is associated with each other, and if there is an abnormal instruction that needs to be processed by fixup in at least one instruction included in each block instruction, the associated code of the abnormal instruction is the associated instruction, that is, the instruction except the abnormal instruction in the block instruction. Based on this, if an operation exception is detected, and the current block instruction currently being operated includes a second instruction, that is, an exception instruction that needs to be processed by fixup exists in the current block instruction, the operation of the current block instruction may be stopped.

In one example, the electronic device detecting a code execution exception for a computing task may include: the kernel of the electronic device receives the memory access exception fed back by the processor of the electronic device, such as the CPU.

In one example, the electronic device detecting a code execution exception for a computing task may include: the kernel of the electronic device receives that the instruction execution condition in the block body is not satisfied. For example, as shown in table 5 above, in the Block instructions from the Block header "Block input (r 1, r 2), br.cond=1f" to the first "block.end", the instruction execution condition may be the instruction execution condition in the Block body: "assert. Lti T#1, MAX". The execution condition in this example is in the form of an asserted instruction such as "asserts", i.e. the execution condition must hold in the normal flow of a computing task: the subscript of the array member must be less than MAX. If not, i.e., the index of the array member is greater than or equal to MAX, meaning that the array member location cannot be calculated, the array member cannot be read, which corresponds to a memory address access exception, fixup may be performed. Similarly, for any content execution condition, such as assertion, if the execution condition is not satisfied, it means that the execution result of the instruction corresponding to the execution condition cannot be read/written, that is, corresponds to the memory address access exception, and fixup can be executed.

According to the embodiment of the application, the abnormality can be processed by applying fixup through the instruction execution conditions in the block body, such as assertion, without pre-determining information about the memory address (such as whether access permission is set, whether a delayed loading mechanism is adopted, etc.), and the method is more convenient. Moreover, the execution conditions, such as the assertion instruction, are conventional instructions in codes belonging to computing tasks, and are not instructions which are specially used for the fixup scene and are additionally learned, so that the execution conditions are more friendly to the developer and more convenient.

In the scenario where the execution condition is the predicate instruction, if the execution result of the predicate instruction is not satisfied, then fixup is executed. In this way, the electronic device does not need to execute actual operations (such as data calculation, access and the like) and only needs to judge the conditions, so that the electronic device is more efficient. Moreover, a large number of code branches can be reduced by asserting instructions, which is beneficial to code viewing.

In one example, for block instructions that do not have a jump function, the partitioning of additional block instructions for jumps may be reduced. Even the block instruction with the jump function, the form of the predicated instruction reduces the jump in the instruction execution, can ensure that codes are maintained in the same pipeline, improves the accuracy of the predicted instruction, and reduces the execution delay caused by the jump, thereby being beneficial to improving the running performance of a CPU. For the predicted instruction, reference is made to the description of code scheduling already provided in the description of superscalar CPU above, and further description is omitted here.

S603, determining a first skip block instruction corresponding to the current block instruction with abnormal operation, and executing the first skip block instruction, wherein the first skip block instruction comprises a block instruction executed after the current block instruction with abnormal operation in a plurality of block instructions.

After stopping running the current block instruction, the electronic device may determine a first skip block instruction corresponding to the current block instruction, and execute the first skip block instruction. The first skip block instruction includes a block instruction of the plurality of block instructions that is executable after the current block instruction, such that a skip operation in fixup processing is implemented. Illustratively, FIG. 7 is an exemplary diagram of an organization of fixup codes based on block instructions provided by an embodiment of the present application. As shown in fig. 7, the block header in the block header1 achieves the effect of the flag fixup, that is, when the predicate instruction in the block body corresponding to the block header1 triggers fixup to process, the associated instruction of the predicate instruction and the second instruction that can jump need not to be searched fixup table to determine, but the repair block is entered when the first-level hardware of the dispatch block header detects an abnormality, that is, jumps to the repair block and executes the repair block. The repair block is the first skip block instruction. For the first level hardware, reference is made to the previous description of the embodiment of table 5, and no further description is given here.

In this way, the embodiment of the application indicates the data needed for fixup in the form of code structure and instruction definition directly in the context of the code of the computing task, without searching fixup record table or special instruction processing exception, and the CPU directly jumps to the first jump block instruction in the computing task for execution.

In one example, the determining, by the electronic device, a first skip block instruction corresponding to a current block instruction of the abnormal operation may include: and the electronic equipment determines block instructions after the current block instruction with abnormal operation to obtain a first jump block instruction. The block instruction after the current block instruction may be an nth block instruction after the current block instruction, where n is greater than or equal to 1, and may specifically be set according to an application requirement, which is not limited in the embodiment of the present application. For example, assuming that the current Block instruction is the Block instruction from the Block header "Block input (r 1, r 2) to the first" Block end "in table 5, br.cond=1f", then the first skip Block instruction is the Block instruction from the Block header "Block br=ret" to the last "Block end".

In one example, the determining, by the electronic device, a first skip block instruction corresponding to a current block instruction of the abnormal operation may include: the electronic equipment determines a block instruction identifier from a second instruction contained in the current block instruction with abnormal operation, and acquires a first jump block instruction according to the block instruction identifier. Wherein the block instruction identifies a storage location for indicating the first skip block instruction. For example, the block instruction identification may be "br=ret" in the above table 5, or address in the block body attribute "set_fix_address". For each block instruction, the block header of the block instruction corresponds to the block body, and based on this, the storage location of the block instruction may be the storage location of the block instruction header (such as the head address of the memory space occupied by the block header). The obtaining the first skip block instruction according to the storage location, that is, the block instruction identifier may be, for example, reading the first skip block instruction in the memory space corresponding to the storage location.

In an alternative embodiment, after detecting an operation abnormality and the current block instruction currently running contains the second instruction, the electronic device may store, through a pre-configured register, abnormality information about the operation abnormality to facilitate processing such as abnormality prompting, analysis, recording, and the like. The exception information about the running exception may include a storage location of the block instruction where the exception occurs, an exception type (such as a page fault exception, an assertion exception, etc.), etc., which may specifically be set according to an application requirement, which is not limited in the embodiment of the present application.

In one example, the pre-configured registers may include system registers. The system register is a register for realizing functions provided by the kernel (such as page table management, etc., where a page table is used to record a mapping relationship between a virtual address space and a physical address space). The block heads of different block instructions are executed by different threads, the thread switch causes the executed block heads to be changed, the thread execution context, that is, the block head execution context is changed, and the abnormal information may be changed. Thus, it is also necessary to pre-configure a context register for storing the block header context to ensure the accuracy of the exception information. Based on this, the electronic device may acquire, after detecting that the operation is abnormal and the current block instruction currently running includes the second instruction, the abnormality information about the operation abnormality through the context register configured in advance, and save the abnormality information through the system register. In addition, when the electronic device uses the abnormality information, it is necessary to read the abnormality information from the system register to a general-purpose register for realizing a function other than the function provided by the core.

In one example, the pre-configured registers may include registers indicated in a block header attribute or a block body attribute of the at least one block instruction. As shown in table 6 below:

The block header attribute corresponds to a block header declaration, for example, a block header attribute "output= (r 1) shown in table 6, attr= fixup, br_type= ret fixup _type= fallthrough", or a register "r1" indicated in a block body attribute "set_ fixup _regr1" shown in table 6. In one example, the first skip block instruction may include an instruction for saving exception information regarding the operation exception, such as "input (r 1)" shown in table 6.

In an alternative embodiment, the at least one block instruction is preconfigured with a system register, where the system register is used to implement a function provided by a Kernel (Kernel) of the electronic device (such as page table management), and store information of the first jump block instruction. The system register is a register which can be accessed by the kernel of the electronic device, namely the kernel operation authority of the electronic device is higher than the scheduling hardware of the block instruction, such as the first-level hardware. In this way, when the kernel of the electronic device detects that the operation is abnormal and the current block instruction currently running includes the second instruction, a control instruction may be sent to the system register to instruct the system register to feed back/not feed back the information of the first skip block instruction to the primary hardware, so as to take over fixup processing, that is, determine whether to perform fixup processing by the kernel. Therefore, the kernel can be ensured to be controllable to the exception, namely, the kernel can decide whether to solve the exception or process fixup, so that the calculation task is ensured to be more controllable, and the user experience is improved. The current block instruction currently running contains a second instruction, namely, the running exception is indicated to occur in the block instruction which needs fixup to be processed. The electronic device may determine whether the current block instruction running the exception is a block instruction requiring fixup processing through the exception information stored in the above-described pre-configured register (also referred to as an exception status register).

For example, the operation exception may be a page fault exception fed back by the system register, and the core may specifically control the exception, or the core may determine to allocate a physical address space corresponding to the memory address accessed for the page fault exception, or perform fixup processing instead of performing the allocation. It can be appreciated that how the kernel handles the exception after the kernel is controllable may be set according to the application requirement, which is not limited by the embodiment of the present application.

In an alternative embodiment, the at least one block instruction is atomic, i.e. the access to the memory address by the block instruction is atomic with respect to block instructions other than the block instruction. The atomicity of the block instruction means that the action indicated by each instruction in the block instruction occurs, and the access result of each instruction in the block instruction to the memory address is output uniformly, that is, is not modified by the block instructions except the block instruction. In one example, the memory address accessed by this embodiment may be the smallest Cache unit CACHE LINE in the CPU Cache (Cache), and the access may specifically include a read or update. The exception handling mode provided by the embodiment of the application is realized by stopping executing the current block instruction and executing the first jump block instruction different from the current block instruction, and the result of reading or updating the memory address by the block instruction is not modified, so that the exception handling mode can be suitable for the block instruction with atomicity, and the application scene of the exception handling method is expanded.

For example, as shown in table 7 below, for computing task 3, assuming that the atomicity guaranteed array member is not 0 to multiply by 10, an instruction indicating atomicity (e.g., instruction "attr= (fixup, atomic)") may be included in the block header attribute to inform the kernel of the electronic device to execute the block instruction according to the rules of atomicity. Thus, if the block instruction triggers fixup processing, execution of the block instruction is stopped and execution of the corresponding first jump block instruction jumps, thereby ensuring that the entire block instruction can atomically access the memory address. In addition, the condition that the above-mentioned guaranteed array member is not 0 and multiplied by 10 can be indicated by an instruction in the block body of the block instruction, for example, the predicate instruction "assent. Neq t#1,0" in table 7.

In one example, the exception handling method provided by the embodiment of the present application may be implemented by exception handling logic based on an underlying language (e.g., an assembly language adopted by a kernel of an operating system, which may be referred to as examples in the tables above), where the exception handling logic may be encapsulated in a higher-level language (e.g., a more abstract programming language such as C language, c++ language, etc.), so as to compromise the exception handling method and the higher-level language functions provided by the embodiment of the present application. For example, as shown in table 8 below:

The instruction "block_try" represents a function implemented by a try instruction (meaning an execution operation) in a language such as c++ in the first computing logic and the second computing logic. The exception handling logic is packaged in a high-level language with an instruction "catch (block_ exception ret)" for handling exception, so that the function of the try instruction implementation is not affected, and the implementation of the exception handling method provided by the embodiment of the application can be ensured. Accordingly, the high-level language has the advantages of the exception handling method provided by the embodiment of the application.

It may be understood that each specific code and instruction in the embodiment of the present application are examples, and do not limit the specific form of the instruction and code in the exception handling method provided in the embodiment of the present application.

In one example, fig. 8 is a block diagram of an exception handling apparatus according to an embodiment of the present application. As shown in fig. 8, the exception handling apparatus 800 may include: a code running module 801 and an exception handling module 802;

A code running module 801, configured to run a code of a computing task to execute the computing task, where the code of the computing task includes a plurality of block instructions, and the plurality of block instructions are respectively configured to implement a plurality of subtasks included in the computing task; a second instruction is preset in at least one of the plurality of block instructions, and the second instruction is used for indicating that the corresponding block instruction contains codes for accessing the appointed memory address;

An exception handling module 802, configured to stop running the current block instruction when an operation exception is detected and the current block instruction that is currently running includes a second instruction; and determining a first skip block instruction corresponding to the current block instruction with abnormal operation, and executing the first skip block instruction, wherein the first skip block instruction comprises a block instruction which can be executed after the current block instruction with abnormal operation in a plurality of block instructions.

All relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.

The present embodiment also provides a computer storage medium having stored therein computer instructions which, when executed on an electronic device, cause the electronic device to execute the above-described related method steps to implement the exception handling method in the above-described embodiments.

The present embodiment also provides a computer program product which, when run on a computer, causes the computer to perform the above-described related steps to implement the exception handling method in the above-described embodiments.

The electronic device, the computer storage medium, the computer program product, or the chip provided in this embodiment are used to execute the corresponding methods provided above, so that the beneficial effects thereof can be referred to the beneficial effects in the corresponding methods provided above, and will not be described herein.

Any of the various embodiments of the application, as well as any of the same embodiments, may be freely combined. Any combination of the above is within the scope of the application.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. An exception handling method, the method comprising:

Executing a plurality of block instructions to perform a computing task; wherein the plurality of block instructions are respectively used for realizing different subtasks in the computing task; each block instruction of the plurality of block instructions includes at least one first instruction for implementing the subtask; at least one block instruction of the plurality of block instructions further includes a second instruction; the second instruction is used for indicating the function of the at least one instruction in the block instruction to be accessing the appointed memory address;

If the abnormal operation is detected, and the current block instruction currently operated contains the second instruction, stopping operating the current block instruction;

Determining a first jump block instruction corresponding to a current block instruction with abnormal operation, and operating the first jump block instruction, wherein the first jump block instruction is one of the plurality of block instructions and is executed after the current block instruction with abnormal operation.

2. The method of claim 1, wherein each block instruction of the plurality of block instructions comprises a block header and a block body; the block header is used for indicating attribute information of the block instructions, and the block body comprises the first instruction in the block instructions;

the second instruction is contained within the block header or the block body.

3. The method of claim 1 or 2, wherein the second instruction is further for indicating a storage location of the first skip block instruction;

The determining the first jump block instruction corresponding to the current block instruction with abnormal operation includes:

And acquiring the first jump block instruction according to the storage position.

4. The method according to claim 1 or 2, wherein the determining the first skip block instruction corresponding to the current block instruction of the abnormal operation includes:

Determining an nth block instruction after the current block instruction with abnormal operation from the plurality of block instructions to obtain the first jump block instruction; wherein n is an integer greater than or equal to 1; the plurality of block instructions are ordered in an order of execution.

5. The method of any of claims 1-4, wherein the method further comprises, if the run exception is detected and a current block instruction currently running contains the second instruction, before:

Receiving an operation result of the interrupt instruction of the current block instruction; at least one block instruction of the plurality of block instructions further includes the predicate instruction;

and if the operation result is false, determining that the operation is abnormal.

6. The method of any of claims 1-5, wherein after the detecting the execution exception and the current block instruction currently executing includes the second instruction, the method further comprises:

Obtaining abnormal information of the abnormal operation;

Storing the abnormality information through a preset register indicated by a third instruction in the current abnormal running block instruction; at least one block instruction of the plurality of block instructions also includes the third instruction.

7. The method of any of claims 1-6, wherein after determining a first skip block instruction corresponding to a current block instruction that is running abnormally and running the first skip block instruction, the method further comprises:

If the first skip block instruction is detected to run abnormally and contains the second instruction, sending a control instruction to a system register through a kernel;

The system register is used for determining a second jump block instruction corresponding to the first jump block instruction with abnormal operation; the control instruction is used for indicating whether to determine a second jump block instruction or not; the second skip block instruction is one of the plurality of block instructions and is executed after the first skip block instruction that is abnormally executed.

8. The method of any of claims 1-7, wherein the second instruction is further to indicate that at least one block instruction of the plurality of block instructions is atomic; and each instruction contained in the block instruction corresponding to the second instruction completes operation.

9. An exception handling apparatus, the apparatus comprising:

An execution module to execute a plurality of block instructions to perform a computing task; wherein the plurality of block instructions are respectively used for realizing different subtasks in the computing task; each block instruction of the plurality of block instructions includes at least one first instruction for implementing the subtask; at least one block instruction of the plurality of block instructions further includes a second instruction; the second instruction is used for indicating the function of the at least one instruction in the block instruction to be accessing the appointed memory address;

The exception handling module is used for stopping running the current block instruction if the running exception is detected and the current block instruction currently running contains the second instruction; determining a first jump block instruction corresponding to a current block instruction with abnormal operation, and operating the first jump block instruction, wherein the first jump block instruction is one of the plurality of block instructions and is executed after the current block instruction with abnormal operation.

10. The apparatus of claim 9, wherein each block instruction of the plurality of block instructions comprises a block header and a block body; the block header is used for indicating attribute information of the block instructions, and the block body comprises the first instruction in the block instructions;

the second instruction is contained within the block header or the block body.

11. The apparatus of claim 9 or 10, wherein the second instruction is further configured to indicate a storage location of the first skip block instruction;

The exception handling module is specifically configured to:

12. The apparatus according to claim 9 or 10, wherein the exception handling module is specifically configured to:

13. The apparatus according to any one of claims 9-12, wherein the exception handling module is specifically configured to:

Before the current block instruction which is detected to run abnormally and runs currently contains the second instruction, receiving a running result of the interrupt instruction of the current block instruction; at least one block instruction of the plurality of block instructions further includes the predicate instruction;

14. The apparatus according to any one of claims 9-13, wherein the exception handling module is specifically configured to:

after the if the run exception is detected and the current block instruction currently running contains the second instruction,

Obtaining abnormal information of the abnormal operation;

15. The apparatus of any of claims 9-14, wherein the exception handling module is further to:

The first jump block instruction corresponding to the current block instruction with abnormal operation is determined, and after the first jump block instruction is operated,

If the first jump block instruction is detected to run abnormally and the first jump block instruction running abnormally contains the second instruction, sending a control instruction to a system register through a kernel;

16. The apparatus of any of claims 9-15, wherein the second instruction is further to indicate that at least one block instruction of the plurality of block instructions is atomic; and each instruction contained in the block instruction corresponding to the second instruction completes operation.

17. An electronic device, comprising:

A processor and a transceiver;

A memory for storing one or more programs;

the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any of claims 1-8.

18. A computer readable storage medium comprising a computer program, characterized in that the computer program, when run on an electronic device, causes the electronic device to perform the method of any one of claims 1 to 8.

19. A chip comprising one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal from a memory of an electronic device and to send the signal to the processor, the signal including computer instructions stored in the memory; the computer instructions, when executed by the processor, cause the electronic device to perform the method of any one of claims 1 to 8.

20. A computer program product comprising a computer program which, when executed by an electronic device, causes the electronic device to perform the method of any one of claims 1 to 8.