CN118158487B

CN118158487B - Video data transmission system and method

Info

Publication number: CN118158487B
Application number: CN202410565552.0A
Authority: CN
Inventors: 李学瑞; 高杰; 刘付辉生; 金少峰
Original assignee: Shenzhen Sincevision Technology Co ltd
Current assignee: Shenzhen Sincevision Technology Co ltd
Priority date: 2024-05-09
Filing date: 2024-05-09
Publication date: 2024-08-06
Anticipated expiration: 2044-05-09
Also published as: CN118158487A

Abstract

The application discloses a video data transmission system and a method, comprising the following steps: the system comprises a target camera and an upper computer, wherein the target camera is connected with a network adapter in the upper computer, the target camera comprises a programmable logic device and a physical layer transceiver, the programmable logic device comprises an Ethernet interface IP core and a protocol control module, and the protocol control module comprises a camera detection module, a register writing module and a register reading module. Therefore, the Ethernet interface is adopted to transmit video data, and the video data is transmitted through the UDP protocol, so that a video data transmission system of the target camera and the upper computer is formed, the video transmission efficiency between the FPGA chip in the camera and the upper computer is improved, an additional video acquisition card is not needed, and the cost is saved.

Description

Video data transmission system and method

Technical Field

The application relates to the field of video data transmission, in particular to a video data transmission system and a video data transmission method.

Background

Currently, video data is generally transmitted by using interfaces such as HDMI (High Definition Multimedia Interface, high-definition multimedia interface), DVI (Digital Visual Interface, digital Video interface), VGA (Video GRAPHICS ARRAY ), displayPort, SDI (SERIAL DIGITAL INTERFACE, serial digital interface), and the like, and a display terminal is connected to a display of a corresponding port, so as to display the transmitted Video data. However, the industrial camera usually receives video data through an upper computer running on a host computer, and then analyzes and calculates the video data shot by the camera through analysis software, so as to control a moving part on a production line to make corresponding movement according to a calculation result, or directly reserve the video data for subsequent analysis and statistics. If the video connection line is also used, a video acquisition card needs to be additionally added, and the cost is additionally increased for users.

Disclosure of Invention

The embodiment of the application provides a video data transmission system and a method, which adopt an Ethernet interface to transmit video data and transmit the video data through UDP protocol to form a video data transmission system of a target camera and an upper computer, thereby being beneficial to improving video transmission efficiency between an FPGA chip and the upper computer in the camera, saving cost without an additional video acquisition card, and simultaneously realizing the functions of camera searching, register writing and register reading by respectively identifying and executing commands issued by the upper computer by a camera detection module, a register writing module and a register reading module in the FPGA chip.

In a first aspect, an embodiment of the present application provides a video data transmission system, including: the host computer comprises a network adapter, a target camera and a host computer, wherein,

The target camera comprises a programmable logic device and a physical layer transceiver, wherein the programmable logic device is connected with the physical layer transceiver, the physical layer transceiver is connected with the network adapter, the upper computer is used for sending a first data packet to the physical layer transceiver through the network adapter, the first data packet comprises a first port number and command information, the command information comprises first command information, second command information and third command information, the first command information is used for acquiring camera state information of the target camera, the second command information is used for controlling the programmable logic device to write first register value data in a first register address of a register of the programmable logic device, and the third command information is used for controlling the programmable logic device to read second register value data in a second register address of the register;

The programmable logic device comprises an Ethernet interface IP core, a data transmission protocol stack, a protocol control module, the register, a second switching control module and a conversion module; the protocol control module comprises a camera detection module, a register writing module and a register reading module; the Ethernet interface IP core is respectively connected with the physical layer transceiver and the data transmission protocol stack, the data transmission protocol stack is respectively connected with the camera detection module, the register writing module, the register reading module and the conversion module, the second switching control module is respectively connected with the protocol control module and the conversion module, and the protocol control module is connected with the register;

The ethernet interface IP core is configured to receive a first data packet from the physical layer transceiver and send the first data packet to the data transfer protocol stack, the data transfer protocol stack is configured to unpack the first data packet and send the first port number and the command information to the camera detection module, the register write module, and the register read module, the camera detection module is configured to determine the camera status information of the target camera according to the first command information and determine first return data when the first port number matches its second port number, the register write module is configured to write the first register value data in the first register address according to the second command information when the first port number matches its third port number is detected, and determine second return data, the register read module is configured to read the second register value data in the second register according to the third command information when the first port number matches its fourth port number is detected, and determine that the first return data includes at least the first return data, the first return data includes: a register write completion identification, a register write failure identification, the first register address and the first register value data, the third return data comprising at least one of: a register read completion identification, a register read failure identification, the second register address, and the second register value data;

The second switching control module is configured to receive the first return data or the second return data or the third return data from the protocol control module, and is configured to forward the first return data or the second return data or the third return data to the data transmission protocol stack through the conversion module, where the data transmission protocol stack is configured to package the first return data to obtain a second data packet or package the second return data to obtain a third data packet or package the third return data to obtain a fourth data packet, and send the second data packet or send the third data packet or send the fourth data packet to the ethernet interface IP core;

the Ethernet interface IP core is used for sending the second data packet or the third data packet or the fourth data packet to the upper computer through the physical layer transceiver.

In one possible example, the conversion module is configured to determine first information required to package the first return data or determine second information required to package the second return data or determine third information required to package the third return data, and send the first information and the first return data or send the second information and the second return data or send the third information and the third return data to the data transmission protocol stack; the data transmission protocol stack is configured to package the first return data according to the first information to obtain the second data packet or package the second return data according to the second information to obtain the third data packet or package the third return data according to the third information to obtain the fourth data packet.

In one possible example, the conversion module includes a speed control module for controlling a speed at which the conversion module sends data packets to the data transmission protocol stack.

In one possible example, the protocol control module includes a first switching control module connected to the second switching control module, the camera detection module, the register write module, and the register read module, respectively; the first switching control module is configured to acquire the first return data of the camera detection module, the second return data of the register write module, and the third return data of the register read module in a polling manner, and send the first return data or the second return data or the third return data to the second switching control module.

In one possible example, the programmable logic device includes a video data streaming module and a retransmission module, the retransmission module includes an internal memory and an interface protocol conversion buffer module, the video data streaming module is connected with an external memory of the target camera, the internal memory is connected with the interface protocol conversion buffer module and the video data streaming module, and the interface protocol conversion buffer module is connected with the second switching control module;

The video data stream transmission module is used for receiving video data from the external memory, packaging the video data to obtain a first video data packet, sending the first video data packet to the internal memory, storing the first video data packet by the internal memory, forwarding the first video data packet to the data transmission protocol stack by the interface protocol conversion buffer module, packaging the first video data packet by the data transmission protocol stack to obtain a fifth data packet, and sending the fifth data packet to the upper computer by the Ethernet interface IP core.

In one possible example, the programmable logic device includes a packet transmission control module, the retransmission module includes a cache write module and a cache read module, the packet transmission control module is respectively connected to the protocol control module, the cache read module and the cache write module, and the built-in memory is respectively connected to the cache read module and the cache write module; the data packet transmission control module is used for receiving an acknowledgement character instruction from the upper computer, and controlling the cache writing module to write the first video data packet after the first data packet identification into the built-in memory according to a data packet identification sequence according to a first data packet identification in the acknowledgement character instruction;

The data packet transmission control module is used for receiving a retransmission instruction from the upper computer, determining a second data packet identifier of a second video data packet to be retransmitted according to the retransmission instruction, sending the second data packet identifier to the cache reading module, reading the second video data packet from the built-in memory according to the second data packet identifier by the cache reading module, forwarding the second video data packet to the data transmission protocol stack through the interface protocol conversion cache module, and packaging the second video data packet by the data transmission protocol stack to obtain a sixth data packet and sending the sixth data packet to the upper computer through the Ethernet interface IP core.

In one possible example, the second switching control module is configured to acquire the first video data packet or the second video data packet from the interface protocol conversion buffer module and acquire the first return data or the second return data or the third return data from the first switching control module in a polling manner, and send the first return data or the second return data or the third return data or the first video data packet or the second video data packet to the conversion module.

In one possible example, the programmable logic device includes a port control module connected to the protocol control module and the conversion module, respectively; the port control module is used for distributing a fifth port number of the data transmission protocol stack for packing the first return data or the second return data or the third return data.

In a second aspect, a video data transmission method is applied to a video data transmission system, where the video data transmission system includes a target camera and a host computer, the host computer includes a network adapter, the target camera includes a programmable logic device and a physical layer transceiver, and the programmable logic device includes an ethernet interface IP core, a data transmission protocol stack, a protocol control module, a register, a second switching control module and a conversion module; the protocol control module comprises a camera detection module, a register writing module and a register reading module; the Ethernet interface IP core is respectively connected with the physical layer transceiver and the data transmission protocol stack, the data transmission protocol stack is respectively connected with the camera detection module, the register writing module, the register reading module and the conversion module, the second switching control module is respectively connected with the protocol control module and the conversion module, the protocol control module is connected with the register, and the physical layer transceiver is connected with the network adapter;

the video data transmission method comprises the following steps:

Transmitting a first data packet to the network adapter through the upper computer, forwarding the first data packet to the physical layer transceiver through the network adapter, wherein the first data packet comprises a first port number and command information, the command information comprises first command information, second command information and third command information, the first command information is used for acquiring camera state information of the target camera, the second command information is used for controlling the programmable logic device to write first register value data in a first register address of the register, and the third command information is used for controlling the programmable logic device to read second register value data in a second register address of the register;

the first data packet is sent to the Ethernet interface IP core through the physical layer transceiver, the first data packet is sent to the data transmission protocol stack through the Ethernet interface IP core, and the first data packet is respectively sent to the camera detection module, the register writing module and the register reading module through the data transmission protocol stack;

Determining, by the camera detection module, the camera status information of the target camera according to the first command information when the first port number is detected to match its second port number, and determining first return data or writing, by the register writing module, the first register value data in the first register address according to the second command information when the first port number is detected to match its third port number, and determining second return data, or reading, by the register reading module, the second register value data in the second register address according to the third command information when the first port number is detected to match its fourth port number, and determining third return data, the first return data including the camera status information, the second return data including at least one of: a register write completion identification, a register write failure identification, the first register address and the first register value data, the third return data comprising at least one of: a register read completion identification, a register read failure identification, the second register address, and the second register value data;

Receiving the first return data or the second return data or the third return data from the protocol control module through the second switching control module, sending the first return data or the second return data or the third return data to the conversion module through the second switching control module, and forwarding the first return data or the second return data or the third return data to the data transmission protocol stack through the conversion module;

packaging the first return data through the data transmission protocol stack to obtain a second data packet or packaging the second return data to obtain a third data packet or packaging the third return data to obtain a fourth data packet, and sending the second data packet or the third data packet or the fourth data packet to the Ethernet interface IP core;

And sending a second data packet or sending the third data packet or sending the fourth data packet to the physical layer transceiver through the Ethernet interface IP core, and sending the second data packet or sending the third data packet or sending the fourth data packet to the upper computer through the physical layer transceiver.

In one possible example, the programmable logic device includes a video data stream transmission module, a retransmission module, and a packet transmission control module, where the retransmission module includes an internal memory, an interface protocol conversion cache module, a cache write module, and a cache read module, the video data stream transmission module is connected to an external memory of the target camera, the internal memory is connected to the interface protocol conversion cache module, the video data stream transmission module, the cache read module, and the cache write module, the interface protocol conversion cache module is connected to the second switching control module, and the packet transmission control module is connected to the protocol control module, the cache read module, and the cache write module, respectively; the method further comprises the steps of:

Receiving video data from the external memory through the video data stream transmission module, packaging the video data to obtain a first video data packet, and sending the first video data packet to the internal memory;

Receiving a determined character instruction from the upper computer through the data packet transmission control module, controlling the cache writing module to write the first video data packet after the first data packet identifier into the built-in memory according to a data packet identifier sequence according to a first data packet identifier in the determined character instruction, forwarding the first video data packet to the data transmission protocol stack through the interface protocol conversion cache module, packaging the first video data packet through the data transmission protocol stack to obtain a fifth data packet, sending the fifth data packet to the Ethernet interface IP core, and sending the fifth data packet to the upper computer through the Ethernet interface IP core;

And receiving a retransmission instruction from the upper computer through the data packet transmission control module, determining a second data packet identifier of a second video data packet to be retransmitted according to the retransmission instruction, sending the second data packet identifier to the cache reading module, reading the second video data packet from the built-in memory through the cache reading module according to the second data packet identifier, sending the second video data packet to the data transmission protocol stack through the interface protocol conversion cache module, packaging the second video data packet through the data transmission protocol stack to obtain a sixth data packet, sending the sixth data packet to the Ethernet interface IP core, and sending the sixth data packet to the upper computer through the Ethernet interface IP core.

In a third aspect, an embodiment of the present application provides an electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing part or all of the steps as described in the second aspect of the embodiment of the present application.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program causes a computer to perform some or all of the steps described in the method of the second aspect of the embodiments of the present application.

It can be seen that, in the embodiment of the application, the video data is transmitted by using the ethernet interface, and the video data is transmitted by using the UDP protocol, so as to form a video data transmission system of the target camera and the upper computer, which is beneficial to improving the video transmission efficiency between the FPGA chip and the upper computer in the camera, and also does not need an additional video acquisition card, which is beneficial to saving the cost, and meanwhile, the camera detection module, the register writing module and the register reading module in the FPGA chip respectively identify and execute the commands issued by the upper computer, thereby realizing the functions of camera searching, register writing and register reading.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a video data transmission system according to an embodiment of the present application;

fig. 2 is a schematic diagram of another architecture of a video data transmission system according to an embodiment of the present application;

fig. 3 is a schematic diagram of an architecture of a target camera according to an embodiment of the present application;

fig. 4 is a flowchart of a video data transmission method according to an embodiment of the present application;

Fig. 5 is a flowchart of another video data transmission method according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The electronic device according to the embodiment of the present application may include various handheld devices, vehicle-mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem, and various forms of User Equipment (UE), mobile Station (MS), terminal devices (TERMINAL DEVICE), and so on. For convenience of description, the above-mentioned devices are collectively referred to as electronic devices. The electronic device may also be an industrial camera.

The application provides a video data transmission system and a video data transmission method, and the video data transmission system and the video data transmission method are described in detail below.

Referring to fig. 1, fig. 1 is a schematic diagram of an architecture of a video data transmission system according to an embodiment of the present application, where the system includes a target camera 10 and a host computer 30, the host computer 30 includes a network adapter 20, the target camera 10 includes a programmable logic device 100 and a physical layer transceiver 200, the programmable logic device 100 includes an ethernet interface IP core 101, the ethernet interface IP core 101 is connected to the physical layer transceiver 200, and the physical layer transceiver 200 is connected to the network adapter 20.

The upper computer 30 may be a terminal device, the network adapter 20 may be a network card, the programmable logic device 100 is an FPGA (Field Programmable GATE ARRAY ) chip, the physical layer transceiver 200 is a PHY chip, and the ethernet interface IP core 101 is a USXGMII (Universal Serial 10 Gigabit Ethernet Media Independent Interface ) IP core; the ethernet interface IP core 101 is connected to the physical layer transceiver 200 through a target serial interface, which includes but is not limited to a serdes (SERializer)/DESerializer (deserializer) interface, and the ethernet interface IP core 101 can be adaptively connected to the physical layer transceiver 200 and support connection speeds up to 100m,1g,2.5g,5g,10 g. The physical layer transceiver 200 and the network adapter 20 may be connected by a tera-ethernet, enabling 100m,1000m,2500m,5000m,10000m communication rates. The PHY chip and the MAC chip (USXGMII IP cores implement the functions of the MAC chip) cooperate to form a core part of a Network Interface Card (NIC). The MAC chip is responsible for tasks such as frame encapsulation, address identification, frame filtering, flow control, etc. of the data link layer, while the PHY chip is responsible for signal transmission and reception of the physical layer.

Referring to fig. 2, fig. 2 is a schematic diagram of an architecture of another video data transmission system according to an embodiment of the present application, where the system includes a target camera 10 and a host computer 30, the target camera 10 includes a programmable logic device 100 and a first optical module 300, the programmable logic device 100 includes an ethernet interface IP core 101, the ethernet interface IP core 101 is connected to the first optical module 300, the first optical module 300 is connected to a second optical module 40, and the second optical module 40 is connected to a network adapter 20 in the host computer 30.

Wherein the first optical module 300 and the second optical module 40 may be connected by a tera-megafiber.

Referring to fig. 3, fig. 3 is a schematic diagram of an architecture of a target camera according to an embodiment of the present application, where the target camera 10 includes a programmable logic device 100, a physical layer transceiver 200, a camera system control module 400, and an external memory 500, and the programmable logic device 100 includes an ethernet interface IP core 101, a data transmission protocol stack 102, a protocol control module 103, a second switching control module 104, a conversion module 105, a video data stream transmission module 106, a retransmission module 107, a data packet transmission control module 108, a port control module 109, and a register 110; the protocol control module 103 includes a camera detection module 1031, a register write module 1032, a register read module 1033, and a first switching control module 1034, the retransmission module 107 includes a built-in memory 1071, a cache write module 1072, a cache read module 1073, and an interface protocol conversion cache module 1074, and the conversion module 105 includes a speed control module 1051.

In one possible example, the programmable logic device 100 is connected to the physical layer transceiver 200, the physical layer transceiver 200 is connected to the network adapter 20, the host 30 is configured to send a first data packet to the physical layer transceiver 200 through the network adapter 20, the first data packet includes a first port number and command information, the command information includes first command information, second command information, and third command information, the first command information is configured to obtain camera status information of the target camera, the second command information is configured to control the programmable logic device 100 to write first register value data in a first register address of its register 110, the third command information is used to control the programmable logic device 100 to read second register value data in a second register address of the register; The ethernet interface IP core 101 is respectively connected to the physical layer transceiver 200 and the data transmission protocol stack 102, the data transmission protocol stack 102 is respectively connected to the camera detection module 1031, the register writing module 1032, the register reading module 1033 and the conversion module 105, the second switching control module 104 is respectively connected to the protocol control module 103 and the conversion module 105, and the protocol control module is connected to the register; The ethernet interface IP core 101 is configured to receive a first data packet from the physical layer transceiver 200 and send the first data packet to the data transmission protocol stack 102, the data transmission protocol stack 102 is configured to unpack the first data packet and send the first port number and the command information to the camera detection module 1031, the register writing module 1032 and the register reading module 1033, the camera detection module 1031 is configured to determine the camera status information of the target camera according to the first command information when detecting that the first port number matches with the second port number thereof, and determining first return data, the register write module 1032 being configured to write the first register value data in the first register address according to the second command information and determine second return data when the first port number is detected to match its third port number, the register read module 1033 being configured to read the second register value data in the second register address according to the third command information and determine third return data when the first port number is detected to match its fourth port number, the first return data including the camera status information, the second return data including at least one of: a register writing completion mark, Register write failure identification, the first register address, and the first register value data, the third return data comprising at least one of: a register read completion identification, a register read failure identification, the second register address, and the second register value data; the second switch control module 104 is configured to receive the first return data or the second return data or the third return data from the protocol control module 103, and send the first return data or the second return data or the third return data to the data transmission protocol stack 102 through the conversion module 105, where the data transmission protocol stack 102 is configured to package the first return data to obtain a second data packet or package the second return data to obtain a third data packet or package the third return data to obtain a fourth data packet, and send the second data packet or send the third data packet or send the fourth data packet to the ethernet interface IP core 101; The ethernet interface IP core 101 is configured to send the second data packet, or send the third data packet, or send the fourth data packet to the upper computer 30 through the physical layer transceiver 200.

The protocol control module 103 is GVCP (GigE Vision Control Protocol) modules, and GVCP is an application layer protocol based on a UDP transport layer protocol. Register read-write is implemented using GVCP protocol.

The camera detection module, the register writing module and the register reading module respectively correspond to a second port number, a third port number and a fourth port number, and the third port number and the fourth port number are the same or different.

Wherein the command information is a command field, the command information is any one of the first command information, the second command information and the third command information, and when the first port number is matched (the same as) the second port number, the command information is the first command information, which indicates a command issued by the upper computer 30 to the camera detection module 1031; when the first port number matches (is the same as) the third port number, the command information is second command information, which indicates a command issued by the host computer 30 to the register write module 1032; when the first port number matches (is the same as) the fourth port number, the command information is third command information, which indicates a command issued by the host computer 30 to the register read module 1033.

When the first port number matches the third port number, if the first register address is not read-only, the register write module 1032 may translate the second command information into information such as write register enable, write register address information (first register address) and write register data (first register value data), and send these information to the camera system control module 400, where the camera system control module 400 retrieves a corresponding first register address in the register 110 based on the write register address information, and executes a corresponding write operation at the first register address, and after the write is completed, the register write module 1032 determines that the second return data needs to be sent to the upper computer, where the second return data includes a register write completion identifier, the first register address and the first register value data, and when the write is failed, the register write module determines that the second return data needs to be sent to the upper computer, where the second return data includes a register write failure identifier, the first register address and the first register value data.

When the first port number matches the fourth port number, the register read module 1033 translates the third command information into information such as read register enable information and read register address information (second register address), and sends the information to the camera system control module 400, the camera system control module 400 retrieves the corresponding second register address based on the read register address information, reads the second register value data in the second register address, and sends the second register value data to the register read module 1033, and the register read module 1033 determines that the third return data needs to be sent to the upper computer 30, where the third return data includes a register read completion identifier, the first register address, and the first register value data, and when the read fails, the register read module 1033 also determines that the third return data needs to be sent to the upper computer 30, where the third return data includes a register read failure identifier, the first register address, and the first register value data. The first register address and the second register address are the same or different.

When the first port number does not match the second port number, the first return data determined by the camera detection module 1031 is information search failure status information. When the first port number is not matched with the third port number, the second return data determined by the register write module 1032 is write failure state information, and when the first port number is matched with the third port number, if the first register address is read-only, the second return data determined by the register write module 1032 is write failure state information; when the first port number does not match the fourth port number, the third return data determined by the register read module 1033 is read failure state information.

The second register value data includes a plurality of second register values, and the first register value data includes a plurality of first register values. The first register value data and the second register value data are the same or different.

The camera system control module 400 is connected to the external memory 500, and the first register value data may be command data for controlling the target camera 10 to start video data transmission, and after receiving the first register value data, the camera system control module 400 controls the external memory 500 to start sending video data to the video data stream transmission module 106; alternatively, the first register value data may be command data for controlling the target camera 10 to end video data transmission, and the camera system control module 400 controls the external memory 500 to stop transmitting video data to the video data streaming module 106 after receiving the first register value data.

The camera detection module 1031 is responsible for acquiring camera status information of the target camera pre-stored in the programmable logic device 100 or accessing the external memory 500 of the target camera 10 to acquire the camera status information when the first port number matches with the second port number thereof, and determining first return data, where the camera status information includes, but is not limited to, information of an IP address, a MAC address, a camera model, a camera name, a camera version number, a camera version compiling date, and the like of the target camera.

In this example, the ethernet interface is used to transmit video data, and the video data is transmitted through the UDP protocol, so as to form a video data transmission system of the target camera 10 and the upper computer 30, which is beneficial to improving video transmission efficiency between the FPGA chip and the upper computer in the camera, and does not need an additional video acquisition card, which is beneficial to saving cost, and meanwhile, the camera detection module, the register writing module and the register reading module in the FPGA chip respectively identify and execute commands issued by the upper computer, so as to realize functions of camera search, register writing and register reading.

In one possible example, the conversion module 105 is configured to determine first information required to package the first return data or determine second information required to package the second return data or determine third information required to package the third return data, and send the first information and the first return data or send the second information and the second return data or send the third information and the third return data to the data transmission protocol stack 102; the data transmission protocol stack 102 is configured to package the first return data according to the first information to obtain the second data packet or package the second return data according to the second information to obtain the third data packet or package the third return data according to the third information to obtain the fourth data packet.

The data transmission protocol Stack 102 may be a UDP (User Datagram Protocol ) Stack, where the data transmission protocol Stack 102 is configured to unpack a data packet transmitted from the upper computer 30, and to package data to be transmitted to the upper computer 30, for example: and packaging the first return data and/or the second return data and/or the third return data and/or the first video data packet and/or the second video data packet. And packaging the first video data packet to obtain a fifth data packet, and packaging the second video data packet to obtain a sixth data packet.

Wherein the first information includes a data length, a destination port number, a destination IP address, and the like, corresponding to the first return data, the second information includes a data length, a destination port number, a destination IP address, and the like, corresponding to the second return data, and the third information includes a data length, a destination port number, a destination IP address, and the like, corresponding to the third return data.

The ethernet interface IP core 101 sends the second data packet or the third data packet or the fourth data packet or the fifth data packet or the sixth data packet to the physical layer transceiver 200, the physical layer transceiver 200 sends the second data packet or the third data packet or the fourth data packet or the fifth data packet or the sixth data packet to the network adapter 20, and the network adapter 20 sends the second data packet or the third data packet or the fourth data packet or the fifth data packet or the sixth data packet to the upper computer 30.

In this example, the camera detection module 1031, the register writing module 1032 and the register reading module 1033 in the FPGA chip respectively identify and execute the commands issued by the upper computer, so as to realize the functions of camera searching, register writing and register reading, and transmit video data by using the ethernet interface, and transmit video data by using the UDP protocol, so as to form a video data transmission system of the target camera 10 and the upper computer 30, which is beneficial to improving the video transmission efficiency between the FPGA chip and the upper computer 30 in the camera, and does not need an additional video acquisition card, thereby being beneficial to saving cost.

In one possible example, the conversion module 105 includes a speed control module 1051, where the speed control module 1051 is configured to control a speed at which the conversion module 105 sends data packets to the data transmission protocol stack 102.

The upper computer 30 may control the speed of sending the data packet by the programmable logic device 100 through a command, the upper computer 30 may unpack the data packet carrying the fourth command information or the fifth command information by sending the data packet carrying the fourth command information or the fifth command information by the data transmission protocol stack 102, forward the fourth command information or the fifth command information to the speed control module 1051 in the conversion module 105 through the protocol control module 103, and the speed control module 1051 analyzes the fourth command information or the fifth command information to adjust the speed of sending the data packet to the data transmission protocol stack 102, thereby realizing that the upper computer 30 controls the speed of sending the data packet by the programmable logic device 100; the fourth command information is used for controlling the speed of sending the data packet, and the fifth command information is used for controlling the speed of sending the data packet to be reduced.

When the upper computer 30 detects that the current network environment is good, the fourth command information can be sent to the speed control module 1051 to control the speed of sending the data packet, and when the upper computer 30 detects that the current network environment is bad, the fifth command information can be sent to the speed control module 1051 to control the speed of sending the data packet to slow down, so that the relationship between the speed of sending the data packet and the packet loss is balanced according to the network environment.

It can be seen that, in this example, the upper computer 30 controls the speed of sending the data packet by the programmable logic device 100, so that the video data transmission system can operate at a faster packet sending speed, and the packet loss is less, which is beneficial to improving the stability of the data transmission of the video data transmission system.

In one possible example, the protocol control module 103 includes a first switching control module 1034, where the first switching control module 1034 is connected to the second switching control module 104, the camera detection module 1031, the register write module 1032, and the register read module 1033, respectively; the first switching control module 1034 is configured to acquire the first return data of the camera detection module 1031, the second return data of the register write module 1032, and the third return data of the register read module 1033 in a polling manner, and send the first return data or the second return data or the third return data to the second switching control module 104.

The first switching control module 1034 is AXI (Advanced eXtensible Interface) _interconnect IP core. The first switching control module 1034 performs 3-in-1 switching processing on the returned data of the 3-way AXI bus of the camera detection module 1031, the register write module 1032 and the register read module 1033 to form axi_stream1.

Specifically, the first switching control module 1034 accesses the camera detection module 1031, the register writing module 1032, and the register reading module 1033 in a polling manner, for example, acquires first return data of the camera detection module 1031, sends the first return data to the second switching control module 104, acquires second return data of the register writing module 1032, sends the second return data to the second switching control module 104, and finally acquires the register reading module 1033, and sends third return data to the second switching control module 104. The polling mode may be manually set or default by the system, and is not limited herein.

Optionally, the priority of the first switching control module 1034 to access the camera detection module 1031, the register writing module 1032, and the register reading module 1033 may also be set, for example: the priority order is that the camera detection module 1031 is accessed, the register read module 1033 is accessed, and the register write module 1032 is accessed, and when the camera detection module 1031, the register write module 1032, and the register read module 1033 all have return data, the first switching control module 1034 first acquires the first return data of the camera detection module 1031, then first acquires the third return data of the register read module 1033, and finally acquires the return data of the register write module 1032. The priority may be set manually or by default, and is not limited herein.

It can be seen that, in this example, the first switching control module 1034 can control the ordered transmission of the first return data, the second return data and the third return data, which is beneficial to improving the stability of the data transmission of the video data transmission system.

In one possible example, the programmable logic device 100 includes a video data streaming module 106 and a retransmission module 107, the retransmission module 107 includes an internal memory 1071 and an interface protocol conversion buffer module 1074, the video data streaming module 106 is connected to the external memory 500 of the target camera 10, the internal memory 1071 is connected to the interface protocol conversion buffer module 1074 and the video data streaming module 106, and the interface protocol conversion buffer module 1074 is connected to the second switching control module 104; the video data stream transmission module 106 is configured to receive video data from the external memory 500, package the video data to obtain a first video data packet, send the first video data packet to the internal memory 1071, where the internal memory 1071 is configured to store the first video data packet, forward the first video data packet to the data transmission protocol stack 102 through the interface protocol conversion buffer module 1074, and the data transmission protocol stack 102 is configured to package the first video data packet to obtain a fifth data packet, and send the fifth data packet to the upper computer 30 through the ethernet interface IP core 101.

The external memory 500 may be a DDR (Double Data Rate) memory.

The video data stream transmission module 106 is GVSP (GigE Vision Stream Protocol) modules. The GigE Vision standard is based on the UDP protocol, and includes GVCP protocols and GVSP protocols. The GVCP protocol is used for configuring the camera, while the GVSP protocol is responsible for actual transmission of image data, and the two protocols work together to ensure seamless integration and efficient communication between the camera and the upper computer. The interface protocol conversion buffer module is an AXI-ST-FIFO, and the interface protocol conversion buffer module buffers the data packet to transmit the data packet to form a standard AXI bus data Stream, and the data Stream name is AXI_Stream3.

The video data Stream transmission module 106 is configured to perform buffering and packaging processing on video data of the target camera 10, and perform packaging processing on the video data to obtain GVSP data packets (first video data packets), wherein GVSP data packets can be normally transmitted on the basis of a UDP protocol, and the packets enable the video data to become a GVSP data Stream standard in the GigE Vision protocol, and the data Stream name is axi_stream2. The header packet, payload packet and Trailer packet of data are specified in GVSP data stream format.

The first video data packets correspond to data packet identifiers, the first video data packets are stored in the built-in memory 1071 according to the sequence of the data packet identifiers, the first video data packets are sequentially sent to the second switching control module 104 through the interface protocol conversion buffer module 1074, the second switching control module 104 sends the first video data packets to the conversion module 105, the conversion module 105 sends the first video data packets to the data transmission protocol stack 102, the data transmission protocol stack 102 packages the first video data packets further to obtain a fifth data packet, the fifth data packet is sent to the ethernet interface IP core 101, and the ethernet interface IP core 101 forwards the fifth data packet to the upper computer 30.

After receiving the first video data packet, the conversion module 105 may determine fourth information of the first video data packet packaged by the data transmission protocol stack 102, where the fourth information includes a data length, a destination port number, a destination IP address, and the like of video data in the first video data packet, the conversion module 105 sends the fourth information and the first video data packet to the data transmission protocol stack 102 together, the data transmission protocol stack 102 packages the first video data packet according to the fourth information to obtain a fifth data packet, and sends the fifth data packet to the ethernet interface IP core 101, where the ethernet interface IP core 101 sends the fifth data packet to the upper computer 30 through the physical layer transceiver 200. After receiving the second video data packet, the conversion module 105 may determine fifth information of the data transmission protocol stack 102 for packaging the second video data packet, where the fifth information includes a data length, a destination port number, a destination IP address, and the like of video data in the second video data packet. The conversion module 105 sends the fifth information and the second video data packet to the data transmission protocol stack 102, the data transmission protocol stack 102 packages the second video data packet according to the fifth information to obtain a sixth data packet, and sends the sixth data packet to the ethernet interface IP core 101, where the ethernet interface IP core 101 sends the sixth data packet to the upper computer 30 through the physical layer transceiver 200. The second video data packet is any one of a plurality of first video data packets stored in the built-in memory 1071.

It can be seen that, in this example, the video data stream transmission module 106 may package the video data of the target camera 10 to obtain GVSP data packets, so that the video data of the target camera 10 can be transmitted to the upper computer 30 based on the UDP protocol, which is beneficial to improving the video data transmission efficiency.

In one possible example, the programmable logic device 100 includes a packet transmission control module 108, the retransmission module 107 includes a cache write module 1072 and a cache read module 1073, the packet transmission control module 108 is respectively connected to the protocol control module 103, the cache read module 1073 and the cache write module 1072, and the built-in memory 1071 is respectively connected to the cache write module 1072 and the cache read module 1073; the packet transmission control module 108 is configured to receive an acknowledgement character command from the host computer 30, and control the buffer write module 1072 to write the first video packet after the first packet identifier into the internal memory 1071 according to a packet identifier sequence according to a first packet identifier in the acknowledgement character command; the packet transmission control module 108 is configured to receive a retransmission instruction from the host computer 30, determine a second packet identifier of a second video packet to be retransmitted according to the retransmission instruction, send the second packet identifier to the cache read module 1073, and the cache read module 1073 is configured to read the second video packet from the internal memory 1071 according to the second packet identifier, forward the second video packet to the data transmission protocol stack 102 through the interface protocol conversion cache module 1074, where the data transmission protocol stack 102 is configured to package the second video packet to obtain a sixth packet, and send the sixth packet to the host computer 30 through the ethernet interface IP core 101.

The built-in memory may be RAM (Random Access Memory ).

The packet transmission control module 108 calculates how many GVSP packets can be stored in the internal memory 1071, pulls the ready signal in the axi_stream2 bus high, and the video data Stream transmission module 106 transmits a corresponding number of packets to the retransmission module 107, where the packets are sequentially stored in the internal memory 1071 by the buffer write module 1072.

Wherein, each first video data packet corresponds to a data packet identifier, when the host computer 30 detects packet loss (the data packet identifiers of the plurality of first video data packets are discontinuous), a retransmission command may be sent to the programmable logic device 100, the ethernet interface IP core 101 of the programmable logic device 100 sends the received retransmission command to the data transmission protocol stack 102, and the data transmission protocol stack 102 forwards the retransmission command to the data packet transmission control module 108 through the protocol control module 103. After receiving the retransmission command, the packet transmission control module 108 controls the buffer write module 1072 to stop writing data into the built-in memory 1071, controls the buffer read module 1073 to determine the position of the second video packet in the built-in memory 1071 based on the second packet identifier in the retransmission command, and transmits the second video packet to the data transmission protocol stack 102 through the interface protocol conversion buffer module 1074, and the data transmission protocol stack 102 packages the second video packet to obtain a sixth packet and sends the sixth packet to the upper computer 30.

For example, the upper computer 30 receives a total of nine first video data packets with packet identifiers A0, A1, A2, A4, A5, A6, A7, A8, and A9, the upper computer 30 detects that the first video data packet with packet identifier A3 is absent, so the upper computer 30 may send a retransmission instruction to the programmable logic device 100, where the retransmission instruction includes an A3 packet identifier, the ethernet interface IP core 101 sends the received retransmission instruction to the data transmission protocol stack 102, the data transmission protocol stack 102 forwards the retransmission instruction to the data packet transmission control module 108 through the protocol control module 103, the data packet transmission control module 108 first controls the cache write module 1072 to stop writing data into the internal memory 1071, and sends the A3 packet identifier to the cache read module 1073, and controls the cache read module 1073 to locate the first video data packet corresponding to the A3 packet identifier in the internal memory 1071, that is, the second video data packet, and reads the second video data packet, the ethernet interface IP core 101 sends the received retransmission instruction to the data transmission protocol stack 102, and the data packet is transmitted by the interface IP core 105 to the second interface IP stack 102.

When no packet is lost, the upper computer 30 may send an ACK (acknowledgement character instruction) to the packet transmission control module 108, where the ACK includes the first packet identifier of the first video packet currently received by the upper computer 30, and the packet transmission control module 108 controls the buffer write module 1072 to write the packet after the first packet identifier in the ACK into the internal memory 1071 according to the packet identifier sequence.

For example, when the packet is not lost, the upper computer 30 currently receives the packet identifier a13 of the first video packet from the programmable logic device 100, the upper computer 30 may send an ACK instruction to the programmable logic device 100, where the ACK instruction includes the packet identifier a13, and after the packet transmission control module 108 receives the ACK instruction, it is calculated that 4 first video packets (GVSP packets) may be stored in the internal memory 1071, and then the packet transmission control module 108 controls the cache write module 1072 to write the first video packets with the packet identifiers a14, a15, a16, and a17 into the internal memory 1071.

It can be seen that, in this example, the retransmission module 107 may buffer the first video data packet and perform retransmission of the second video data packet through the data packet transmission control module 108, which is beneficial to improving the stability of the transmission data of the video data transmission system.

In one possible example, the second switching control module 104 is configured to acquire the first video data packet or the second video data packet from the interface protocol conversion buffer module 1074 and acquire the first return data or the second return data or the third return data from the first switching control module 1034 in a polling manner, and send the first return data or the second return data or the third return data or the first video data packet or the second video data packet to the conversion module 105.

The second switch control module 104 is AXI (Advanced eXtensible Interface) _interconnect IP core, and the second switch control module 104 is actually connected to the first switch control module 1034 and the interface protocol conversion buffer module 1074, respectively. The second handover control module 104 acquires axi_stream3 and axi_stream1 in a polling manner, for example: the second switch control module 104 acquires the return data in axi_stream1 first, and then acquires the first video data packet or the second video data packet in axi_stream3.

Alternatively, the second handover control module 104 may be set to obtain the priority of axi_stream3 and axi_stream1, for example: when the priority of obtaining axi_stream3 is greater than that of obtaining axi_stream1, and when both axi_stream3 and axi_stream1 have data to be transmitted, the second switch control module 104 obtains the first video data packet or the second video data packet in axi_stream3 first, and then obtains the return data in axi_stream1.

It can be seen that, in this example, the second switching control module 104 controls the order of acquiring data from the retransmission module 107 and the protocol control module 103, which is beneficial to improving the stability of data transmission of the video data transmission system.

In one possible example, the programmable logic device 100 includes a port control module 109, the port control module 109 being connected to the protocol control module 103 and the conversion module 105, respectively; the port control module 109 is configured to allocate a fifth port number of the data transmission protocol stack 102 for packing the first return data or the second return data or the third return data or the first video data packet or the second video data packet.

The fifth port number is a UDP port number, and the port control module 109 is configured to control the UDP port number given to the data transmission protocol stack 102 by the packet, so as to send different data to the upper computer through different UDP ports. For example: for the return data and the first video data packet, the return data and the first video data packet may be sent to the upper computer 30 through different UDP ports in the ethernet interface IP core 101, and for the different return data, for example, the first return data, the second return data and the third return data, the return data and the first video data packet may be sent to the upper computer 30 through the same or different UDP ports in the ethernet interface IP core 101. Different UDP ports correspond to different port numbers.

In this example, the port control module allocates the UDP port numbers used by the data transmission protocol stack 102 in a packing manner, so that different data can be sent to the upper computer through different UDP ports, the order of different data transmission of the video data transmission system can be ensured, and the efficiency and stability of data transmission of the video data transmission system can be improved.

Referring to fig. 4, fig. 4 is a schematic flow chart of a video data transmission method provided by an embodiment of the present application, which is applied to a video data transmission system, wherein the video data transmission system includes a target camera and an upper computer, the upper computer includes a network adapter, the target camera includes a programmable logic device and a physical layer transceiver, and the programmable logic device includes an ethernet interface IP core, a data transmission protocol stack, a protocol control module, a register, a second switching control module and a conversion module; the protocol control module comprises a camera detection module, a register writing module and a register reading module; the Ethernet interface IP core is respectively connected with the physical layer transceiver and the data transmission protocol stack, the data transmission protocol stack is respectively connected with the camera detection module, the register writing module, the register reading module and the conversion module, the second switching control module is respectively connected with the protocol control module and the conversion module, and the protocol control module is connected with the register;

the video data transmission method comprises the following steps:

Step S401, sending a first data packet to the network adapter through the upper computer, and forwarding the first data packet to the physical layer transceiver through the network adapter.

The first data packet comprises a first port number and command information, the command information comprises first command information, second command information and third command information, the first command information is used for acquiring camera state information of a target camera, the second command information is used for controlling the programmable logic device to write first register value data in a first register address of a register, and the third command information is used for controlling the programmable logic device to read second register value data in a second register address of the register;

Step S402, the first data packet is sent to the ethernet interface IP core through the physical layer transceiver, the first data packet is sent to the data transmission protocol stack through the ethernet interface IP core, and the first data packet is sent to the camera detection module, the register write module and the register read module through the data transmission protocol stack respectively.

Step S403, determining, by the camera detection module, the camera status information of the target camera according to the first command information when the first port number matches its second port number, and determining first return data, or writing, by the register write module, the first register value data in the first register address according to the second command information when the first port number matches its third port number, and determining second return data, or reading, by the register read module, the second register value data in the second register address according to the third command information when the first port number matches its fourth port number, and determining third return data.

Wherein the first return data includes camera status information and the second return data includes at least one of: the register write completion identification, the register write failure identification, the first register address and the first register value data, and the third return data includes at least one of: a register read completion identification, a register read failure identification, a second register address, and second register value data.

Step S404, receiving, by the second switching control module, the first return data or the second return data or the third return data from the protocol control module, sending, by the second switching control module, the first return data or the second return data or the third return data to the conversion module, and forwarding, by the conversion module, the first return data or the second return data or the third return data to the data transmission protocol stack;

Step S405, packaging the first return data through the data transmission protocol stack to obtain a second data packet or packaging the second return data to obtain a third data packet or packaging the third return data to obtain a fourth data packet, and sending the second data packet or sending the third data packet or sending the fourth data packet to the ethernet interface IP core;

Step S406, sending, by the ethernet interface IP core, a second data packet or the third data packet or the fourth data packet to the physical layer transceiver, and sending, by the physical layer transceiver, the second data packet or the third data packet or the fourth data packet to the upper computer.

It can be seen that, in the embodiment of the application, the video data transmission system adopts the ethernet interface to transmit video data, and transmits video data through the UDP protocol, so as to form the video data transmission system of the target camera and the upper computer, which is beneficial to improving video transmission efficiency between the FPGA chip and the upper computer in the camera, and does not need an additional video acquisition card, which is beneficial to saving cost, and meanwhile, the camera detection module, the register writing module and the register reading module in the FPGA chip respectively identify and execute commands issued by the upper computer, thereby realizing functions of camera searching, register writing and register reading.

Referring to fig. 5, fig. 5 is a schematic flow chart of another video data transmission method provided by the embodiment of the present application, where the programmable logic device includes a video data stream transmission module, a retransmission module and a data packet transmission control module, the retransmission module includes an internal memory, an interface protocol conversion buffer module, a buffer write module and a buffer read module, the video data stream transmission module is connected with the external memory of the target camera, the internal memory is respectively connected with the interface protocol conversion buffer module, the video data stream transmission module, the buffer read module and the buffer write module, the interface protocol conversion buffer module is connected with the second switching control module, and the data packet transmission control module is respectively connected with the protocol control module, the buffer read module and the buffer write module; the method further comprises the steps of:

step S501, receiving video data from the external memory through the video data stream transmission module, and packaging the video data to obtain a first video data packet, and sending the first video data packet to the internal memory;

Step S502, receiving a determined character instruction from the upper computer through the data packet transmission control module, controlling the buffer write module to write the first video data packet after the first data packet identifier into the built-in memory according to a data packet identifier sequence, forwarding the first video data packet to the data transmission protocol stack through the interface protocol conversion buffer module, packaging the first video data packet through the data transmission protocol stack to obtain a fifth data packet, sending the fifth data packet to the ethernet interface IP core, and sending the fifth data packet to the upper computer through the ethernet interface IP core;

Step S503, receiving, by the packet transmission control module, a retransmission instruction from the host computer, determining, according to the retransmission instruction, a second packet identifier of a second video packet to be retransmitted, and sending the second packet identifier to the cache read module, reading, by the cache read module, the second video packet from the internal memory according to the second packet identifier, sending, by the interface protocol conversion cache module, the second video packet to the data transmission protocol stack, packaging, by the data transmission protocol stack, the second video packet to obtain a sixth packet, sending, by the ethernet interface IP core, the sixth packet, and sending, by the ethernet interface IP core, the sixth packet to the host computer.

In one possible example, the conversion module is configured to determine first information required to package the first return data or determine second information required to package the second return data or determine third information required to package the third return data, and send the first information and the first return data or send the second information and the second return data or send the third information and the third return data to the data transmission protocol stack;

The data transmission protocol stack is configured to package the first return data according to the first information to obtain the second data packet or package the second return data according to the second information to obtain the third data packet or package the third return data according to the third information to obtain the fourth data packet.

In one possible example, the programmable logic device includes a port control module connected to the protocol control module and the conversion module, respectively; the port control module is configured to allocate a fifth port number of the data transmission protocol stack for packing the first return data, the second return data, the third return data, the first video data packet, or the second video data packet.

In one possible example, the physical layer transceiver is connected to the ethernet interface IP core through a target serial interface.

The foregoing description of the embodiments of the present application has been presented primarily in terms of a method-side implementation. It will be appreciated that the electronic device, in order to achieve the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application can divide the functional units of the electronic device according to the method example, for example, each functional unit can be divided corresponding to each function, and two or more functions can be integrated in one processing unit. The integrated units may be implemented in hardware or in software functional units. It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice.

The embodiment of the application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program makes a computer execute part or all of the steps of any one of the above method embodiments, and the computer includes an electronic device.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned method of the various embodiments of the present application. And the aforementioned memory includes: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and the program may be stored in a computer readable memory, which may include: flash disk, read-only memory, random access memory, magnetic or optical disk, etc.

The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims

1. A video data transmission system, comprising: the host computer comprises a network adapter, a target camera and a host computer, wherein,

2. The system of claim 1, wherein the translation module is configured to determine first information required to package the first return data or determine second information required to package the second return data or determine third information required to package the third return data, and send the first information and the first return data or the second information and the second return data or the third information and the third return data to the data transmission protocol stack;

3. The system according to claim 1 or 2, wherein the conversion module comprises a speed control module for controlling the speed at which the conversion module sends data packets to the data transmission protocol stack.

4. The system of claim 1, wherein the protocol control module comprises a first switching control module connected to the second switching control module, the camera detection module, the register write module, and the register read module, respectively;

The first switching control module is configured to acquire the first return data of the camera detection module, the second return data of the register write module, and the third return data of the register read module in a polling manner, and send the first return data or the second return data or the third return data to the second switching control module.

5. The system of claim 1, wherein the programmable logic device comprises a video data streaming module and a retransmission module, the retransmission module comprising an internal memory and an interface protocol conversion cache module, the video data streaming module being coupled to the external memory of the target camera, the internal memory being coupled to the interface protocol conversion cache module and the video data streaming module, the interface protocol conversion cache module being coupled to the second switch control module;

6. The system of claim 5, wherein the programmable logic device comprises a packet transmission control module, the retransmission module comprises a cache write module and a cache read module, the packet transmission control module is respectively connected with the protocol control module, the cache read module and the cache write module, and the built-in memory is respectively connected with the cache read module and the cache write module;

The data packet transmission control module is used for receiving an acknowledgement character instruction from the upper computer, and controlling the cache writing module to write the first video data packet after the first data packet identification into the built-in memory according to a data packet identification sequence according to a first data packet identification in the acknowledgement character instruction;

7. The system of claim 6, wherein the second switch control module is configured to acquire the first video data packet or the second video data packet from the interface protocol conversion buffer module and acquire the first return data or the second return data or the third return data from the first switch control module in a polling manner, and to send the first return data or the second return data or the third return data or the first video data packet or the second video data packet to the conversion module.

8. The system of claim 5, wherein the programmable logic device comprises a port control module, the port control module being coupled to the protocol control module and the translation module, respectively;

the port control module is configured to allocate a fifth port number of the data transmission protocol stack for packing the first return data, the second return data, the third return data, the first video data packet, or the second video data packet.

9. The video data transmission method is characterized by being applied to a video data transmission system, wherein the video data transmission system comprises a target camera and an upper computer, the upper computer comprises a network adapter, the target camera comprises a programmable logic device and a physical layer transceiver, and the programmable logic device comprises an Ethernet interface IP core, a data transmission protocol stack, a protocol control module, a register, a second switching control module and a conversion module; the protocol control module comprises a camera detection module, a register writing module and a register reading module; the Ethernet interface IP core is respectively connected with the physical layer transceiver and the data transmission protocol stack, the data transmission protocol stack is respectively connected with the camera detection module, the register writing module, the register reading module and the conversion module, the second switching control module is respectively connected with the protocol control module and the conversion module, the protocol control module is connected with the register, and the physical layer transceiver is connected with the network adapter;

the video data transmission method comprises the following steps:

10. The method of claim 9, wherein the programmable logic device comprises a video data stream transmission module, a retransmission module and a packet transmission control module, the retransmission module comprises an internal memory, an interface protocol conversion cache module, a cache write module and a cache read module, the video data stream transmission module is connected with the external memory of the target camera, the internal memory is respectively connected with the interface protocol conversion cache module, the video data stream transmission module, the cache read module and the cache write module, the interface protocol conversion cache module is connected with the second switching control module, and the packet transmission control module is respectively connected with the protocol control module, the cache read module and the cache write module; the method further comprises the steps of: