CN118157698A

CN118157698A - Receiver circuit, corresponding isolation driver device, electronic system and method of decoding differential signals into digital output signals

Info

Publication number: CN118157698A
Application number: CN202311655961.1A
Authority: CN
Inventors: C·卡里纳; V·本多蒂; N·德坎波; V·格纳里·圣托里
Original assignee: Italian Semiconductor International Co
Current assignee: Italian Semiconductor International Co
Priority date: 2022-12-07
Filing date: 2023-12-05
Publication date: 2024-06-07

Abstract

A receiver circuit receives a differential signal including positive and negative spikes and generates an output signal based on the differential signal. The first comparator generates an intermediate set signal comprising a pulse at each positive spike of the differential signal and the second comparator generates an intermediate reset signal comprising a pulse at each negative spike of the differential signal. The logic circuit detects whether the digital signal toggles between a first value and a second value and whether the intermediate reset signal and the intermediate set signal include pulses having a duration longer than a threshold value. The logic generates a set correction signal and a reset correction signal. The logic circuit generates a correction set signal and a correction reset signal. The output circuit generates an output signal based on the correction set signal and the correction reset signal.

Description

Receiver circuit, corresponding isolation driver device, electronic system and method of decoding differential signals into digital output signals

Cross Reference to Related Applications

The present application claims priority from italian patent application No. 102022000025200, entitled "RECEIVER CIRCUIT,CORRESPONDING ISOLATED DRIVER DEVICE,ELECTRONIC SYSTEM AND METHOD OF DECODING A DIFFERENTIAL SIGNAL INTO A DIGITAL OUTPUT SIGNAL", filed on 7, 12, 2022, which is incorporated herein by reference to the maximum extent allowed by law.

Technical Field

The present description relates to an isolated gate driver device applicable to traction inverters, DC/DC converters, on-board chargers (OBCs), and belt-driven starter generators (BSGs) for Electric Vehicles (EVs) and Hybrid Electric Vehicles (HEVs).

Background

Conventional isolated gate driver devices are system-on-chip devices for switching transistors (such as IGBTs, siC or Si MOSFETs) in high voltage motor control applications. Conventional isolated gate driver devices typically include two semiconductor die arranged in the same package: a low voltage die that exchanges signals with the microcontroller, and a high voltage die that includes a driver circuit. The low voltage die and the high voltage die are electrically isolated from each other by a galvanic isolation barrier, which typically includes one or more high voltage capacitors (HVCap) disposed between the two dies.

Fig. 1 is a circuit block diagram of an isolated gate driver device. Fig. 2 is a timing diagram including exemplary waveforms of signals in the device of fig. 1, illustrating possible operation of the device.

As shown in fig. 1, the isolated gate driver device 10 includes a low voltage semiconductor die 10a and a high voltage semiconductor die 10b arranged in the same package. A communication channel is provided in the device 10 such that a (single-ended) Pulse Width Modulated (PWM) input signal PWM _IN (also referred to as a low-voltage transmission signal, e.g., a PWM signal received from a microcontroller at a frequency between 15kHz and 5 MHz) received at the input pin 101 of the low-voltage die 10a may be propagated as a (single-ended) PWM output signal PWM _OUT (also referred to as a high-voltage reception signal) generated at the output pin 106 of the high-voltage die 10b. In some applications, the communication channel may be bi-directional such that a (single-ended) PWM input signal (also referred to as a high voltage transmit signal) received at an input pin of the high voltage die 10b that is not visible in fig. 1 may be propagated as a (single-ended) PWM output signal (also referred to as a low voltage receive signal) transmitted by an output pin of the low voltage die 10a that is also not visible in fig. 1.

In particular, low voltage die 10a includes a transmitter circuit 102, transmitter circuit 102 coupled to input pin 101 and configured to convert received single-ended signal PWM _IN to a pair of differential PWM signals OUT _P、OUT_N. For example, signal OUT _P may be generated at the output of a buffer circuit that receives signal PWM _IN at an input, and signal OUT _N may be generated at the output of another buffer circuit (e.g., an inverting buffer) that receives a complementary signal (e.g., an inverted copy) of signal PWM _IN at an input. The low voltage die 10a also includes a first high voltage capacitor 103P (e.g., an isolation capacitor) having a first terminal coupled to the first output of the transmitter circuit 102 to receive the signal OUT _P and a second high voltage capacitor 103N (e.g., an isolation capacitor) having a first terminal coupled to the second output of the transmitter circuit 102 to receive the signal OUT _N. The second terminals of capacitors 103P and 103N provide an output node of low voltage die 10a that is electrically connected (e.g., via a bond wire) to an input node of high voltage die 10b. The signal OUT _P、OUT_N is thus filtered by the isolation capacitors 103P, 103N (acting as high pass filters) so that the pulsed differential signal Vd reaches the high voltage die 10b. In addition, the transmitter circuit 102 may implement a "gate retry" mechanism: PWM input signal PWM _IN is clocked by a clock signal CLK available in low-voltage die 10a and having a frequency higher than the frequency of signal PWM _IN (e.g., five times higher, ten times higher, or higher) such that spikes are generated in differential signal Vd at each edge of clock signal CLK to facilitate recovery from possible pulse losses and to allow proper reconstruction of signal PWM _IN at the receiver side. Thus, the differential signal Vd comprises a series of temporary spikes (positive and negative) corresponding to the edges of the input signal PWM _IN and the edges of the clock signal CLK, wherein the sign of these spikes depends on the value of the input signal PWM _IN, as shown in fig. 2. In particular, when input signal PWM _IN has a high logic value (logic "1"), the spike of signal Vd is positive, and when input signal PWM _IN has a low logic value (logic "0"), the spike of signal Vd is negative.

The high voltage die 10b includes a receiver circuit 104, the receiver circuit 104 being coupled to an input node of the die 10b to receive the differential signal Vd and configured to generate a reconstructed PWM signal PWM _RX from the received differential signal Vd. For example, the receiver circuit 104 may be configured to set the signal PWM _RX to a high logic value (logic "1") as a result of positive pulses being detected in the differential signal Vd, and to set the signal PWM _RX to a low logic value ("0") as a result of negative pulses being detected in the differential signal Vd, as shown in fig. 2. Thus, the reconstructed signal PWM _RX may substantially correspond to a (slightly) delayed copy of the input signal PWM _IN. The high voltage die 10b may also include a driver stage 105, the driver stage 105 including a pre-driver circuit (e.g., buffers 1051, 1052, 1053) configured to receive the reconstruction signal PWM _RX and drive an output switching circuit (e.g., invert at the inverter 1051 and/or amplify the reconstruction signal PWM _RX at the buffers 1052, 1053) in accordance with the reconstruction signal PWM _RX. For example, the output switching circuit may include a half-bridge driver stage including a high-side switch (e.g., a transistor) and a low-side switch (e.g., a transistor) arranged in series between the high-voltage power supply pin VH and the high-voltage reference (or ground) pin VL of the gate driver device 10. The node between the high side switch and the low side switch may be electrically coupled to the output pin 106 of the gate driver device 10. The high-side and low-side switches are driven by pre-driver circuits 1051, 1052, 1053 such that an output switch signal PWM _OUT is generated at output pin 106 (e.g., the high-side switch is in a conducting state when PWM _RX = "1" and the low-side switch is in a conducting state when PWM _RX = "0").

In the present disclosure, reference is made to the case where the isolation capacitors 103P, 103N are implemented in the low voltage die 10 a. However, it should be understood that the isolation capacitor may alternatively be implemented in the high voltage die 10b, e.g., disposed between an input pin of the high voltage die 10b and an input terminal of the receiver circuit 104.

Fig. 3 is an exemplary circuit block diagram of a possible implementation of the receiver circuit 104, and fig. 4 is a time diagram of an exemplary waveform including signals in the receiver circuit 104 of fig. 3, illustrating a possible operation of the receiver circuit. The input terminals of the circuit 104, which may be referenced to a local (high voltage) ground GND _HV via respective resistors, receive the differential signal Vd and are coupled to the amplifier stage 40, the amplifier stage 40 producing an amplified copy of the differential signal Vd. The amplified differential signals are received at pairs of comparators 42, 44 having opposite input polarities (e.g., the positive output of amplifier 40 may be coupled to the negative input of comparator 42 and the positive input of comparator 44, and the negative output of amplifier 40 may be coupled to the positive input of comparator 42 and the negative input of comparator 44). Thus, comparator 42 generates a (digital) signal COMP _N (e.g., signal COMP _N is normally high and includes a low pulse, as shown in fig. 4) that includes pulses corresponding to positive spikes of signal Vd, and comparator 44 generates a (digital) signal COMP _P (e.g., signal COMP _P is normally high and includes a low pulse, as shown in fig. 4) that includes pulses corresponding to negative spikes of signal Vd. Signals COMP _N and COMP _P serve as set and reset signals for set-reset (S-R) flip-flop 46 of receiver 104. In particular, flip-flop 46 receives a bias voltage V _DD (e.g., 3.3V) at its data input terminal D, a signal COMP _N (possibly supplemented by an inverter stage) at its clock input terminal C _P, and a signal COMP _P at its reset input terminal C _D. Accordingly, the data output terminal Q of flip-flop 46 is set to a high logic value (logic "1") in response to a pulse of signal COMP _N (in particular, in response to a falling edge of signal COMP _N) and is set to a low logic level (logic "0") in response to a pulse of signal COMP _P (in particular, in response to a falling edge of signal COMP _P), thereby generating a reconstructed PWM signal PWM _RX that corresponds to the (delayed) copy of input PWM signal PWM _IN sent by low voltage die 10a of device 10 (as shown in fig. 4). The time interval between two consecutive peaks of the signal Vd (and thus between two consecutive pulses of the signal COMP _N or COMP _P) is equal to half (e.g., T _CLK/2) of the clock period T _CLK of the low voltage clock signal CLK.

As expected, the driver device 10 may be used in a motor control application, as shown in the circuit block diagram of fig. 5, which illustrates a driver portion of the device 10 with an output pin 106 (e.g., a center node or switching node of a half-bridge driver including a high-side switch HS and a low-side switch LS) coupled to an external load (such as a motor M). As shown in fig. 5, the low-side driver circuit 1053 may be powered between the supply voltage of die 10b available at pin VH and a local ground voltage GND _HV (which is available at pin VL), while the high-side driver circuit 1052 may be powered between the supply voltage of die 10b available at pin VH and the switch node 106 (i.e., which may be referenced to a floating ground GND _S). In such a scenario, during switching activity (SWITCHING ACTIVITY) of the half-bridge circuit, the switching node 106 that provides the high-side floating ground GND _S continuously switches between the local ground voltage GND _HV (e.g., 0V) and the supply voltage (which may be on the order of kilovolts) of the die 10b available at pin VH. Thus, the driver device 1052 may experience a fast slew rate voltage transition of the die 10a and 10b between GND and GND _S. These events may generate a burst current that generates a common mode voltage at the input terminals of the receiver circuit 104. The input terminals of the receiver 104 may be affected by mismatch (e.g., because the parasitic capacitor is towards a low voltage ground associated with the bond wire), and thus the common mode voltage may be converted to a spurious differential voltage that adds to the signal Vd.

The above scenario is illustrated in the circuit block diagram of fig. 6, which essentially replicates the circuit block diagram of fig. 3, but additionally indicates the common mode voltage V _CM applied to the input terminals of the amplifier 40. Fig. 7 is a timing diagram of exemplary waveforms comprising signals in the receiver circuit of fig. 6 when such common mode voltage V _CM affects the differential signal Vd. It should be appreciated that the voltage generator shown in fig. 6 is not an actual component implemented in the circuit, but merely indicates the effect of applying a common mode voltage to the input terminals of the receiver 104. In particular, the waveform of the common mode voltage V _CM generated between the low voltage ground GND _LV and the high voltage ground GND _HV during transient events may include a high slew rate ramp that follows the ringing phase (e.g., damped sinusoid) due to the effects of (external) parasitic components. As a result, due to the mismatch of the input terminals of the amplifier 40, the receiver 104 senses a differentially damped sinusoidal high frequency signal, the frequency of which may fall within the amplification band of the receiver chain (e.g., the band of the amplifier 40). Thus, the damped sinusoidal signal can be amplified and produce a series of spurious set and reset pulses (e.g., spurious pulses SP of signals COMP _N and COMP _P, as shown in fig. 7), which are then sensed by flip-flop 46 and produce an unwanted commutation of reconstructed signal PWM _RX (e.g., commutation UC of signal PWM _RX, as shown in fig. 7).

To mitigate the above-described spurious pulse problem in the reconstructed signal PWM _RX due to the common-mode ringing effect in the differential signal Vd, one possible approach is to implement isolation capacitors 103P, 103N in the high-voltage die 10 b. This implementation eliminates the effect of mismatch of bond wires between die 10a and die 10b, which mismatch would be dominated by the low equivalent impedance of the transmitter. However, this approach requires that the isolation capacitors 103P, 103N be implemented in the same technology of the high voltage die 10b, which can be cumbersome, expensive, and/or area consuming.

Accordingly, there is a need in the art to provide a receiver circuit with an improved architecture (e.g., for implementation in an isolated communication channel of a gate driver device) that solves the above-described problems, or in other words, to provide a receiver circuit with improved Common Mode Transient Immunity (CMTI).

Disclosure of Invention

Embodiments of the present disclosure help provide improved receiver circuits.

One or more embodiments may relate to corresponding isolated driver devices.

One or more embodiments may relate to a corresponding electronic system.

One or more embodiments may relate to a corresponding method of decoding a differential pulse signal transmitted across a galvanic isolation barrier to produce a pulse width modulated digital signal.

The claims are an integral part of the technical teaching provided herein regarding the embodiments.

According to one aspect of the present description, in a receiver circuit, a pair of input nodes is configured to receive a differential signal therebetween. The differential signal includes a spike of a first polarity (e.g., positive) and a spike of a second polarity (e.g., negative). The output node is configured to generate a digital output signal from the differential signal. The first comparator circuit is configured to receive the differential signal and to generate an intermediate set signal comprising pulses at each spike of the differential signal having a first polarity. The second comparator circuit is configured to receive the differential signal and to generate an intermediate reset signal comprising a pulse at each spike of the differential signal having a second polarity. The logic circuit is configured to receive an intermediate set signal, an intermediate reset signal, and a digital output signal. The logic circuit is further configured to:

detecting whether the digital output signal switches between a first logic value and a second logic value;

Detecting whether the intermediate reset signal includes pulses having a duration above a certain time interval (e.g., a threshold);

Generating a set correction signal comprising pulses when the digital output signal switches between a first logical value and a second logical value and while the intermediate reset signal comprises pulses having a duration above a certain time interval;

Generating a correction set signal comprising a pulse of the intermediate set signal and a pulse of the set correction signal;

Detecting whether the intermediate set signal includes pulses having a duration above a specified time interval;

generating a reset correction signal comprising pulses when the digital output signal switches between a first logical value and a second logical value and while the intermediate set signal comprises pulses having a duration above a certain time interval; and

A correction reset signal is generated comprising a pulse of the intermediate reset signal and a pulse of the reset correction signal.

The receiver circuit includes an output control circuit configured to receive the correction set signal and the correction reset signal and further configured to assert (also referred to as "activate") the digital output signal in response to detecting a pulse in the correction set signal and to de-assert (de-assert) the digital output signal in response to detecting a pulse in the correction reset signal.

Accordingly, one or more embodiments may provide a receiver circuit with improved robustness to common mode noise using simple logic circuitry.

Optionally, the logic circuit comprises:

A first asymmetric buffer circuit configured to receive the intermediate reset signal and generate a first detection signal by passing an active edge (e.g., a falling edge) of the intermediate reset signal with a delay equal to a particular time interval and passing an inactive edge (e.g., a rising edge) of the intermediate reset signal without substantial delay;

A first gating logic gate configured to pass the first detection signal when the digital output signal switches between the first logic value and the second logic value, and otherwise mask the first detection signal to generate a set correction signal;

A second asymmetric buffer circuit configured to receive the intermediate set signal and generate a second detection signal by passing an active edge (e.g., a falling edge) of the intermediate set signal with a delay equal to a particular time interval and passing an inactive edge (e.g., a rising edge) of the intermediate set signal without substantial delay; and

A second gating logic gate configured to pass the second detection signal when the digital output signal switches between the first logic value and the second logic value, and otherwise mask the second detection signal to generate a reset correction signal.

According to another aspect of the present description, an isolation driver device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes an input pin configured to receive a digital input signal. The first semiconductor die includes a transmitter circuit configured to receive a digital input signal and to generate a pair of complementary digital signals. A first one of the complementary digital signals is a copy of the digital input signal and is generated at a first output node of the transmitter circuit, and a second one of the complementary digital signals is a complement of the digital input signal and is generated at a second output node of the transmitter circuit. The first semiconductor die includes a galvanic isolation barrier including a first isolation capacitor having a first terminal coupled to a first output node of the transmitter circuit and a second isolation capacitor having a first terminal coupled to a second output node of the transmitter circuit. A differential signal is generated between the second terminal of the first isolation capacitor and the second terminal of the second isolation capacitor. The differential signal includes a spike of a first polarity at each rising edge of the digital input signal and a spike of a second polarity at each falling edge of the digital input signal. The second semiconductor die includes receiver circuitry in accordance with one or more embodiments. The first input node of the receiver circuit is electrically coupled to the second terminal of the first isolation capacitor and the second input node of the receiver circuit is electrically coupled to the second terminal of the second isolation capacitor to receive the differential signal.

According to another aspect of the present description, an electronic system includes a processing unit and an isolated driver device according to one or more embodiments. The processing unit is configured to generate a digital input signal received by the isolated driver device.

According to another aspect of the present description, a method of decoding a differential signal into a digital output signal includes:

Receiving a differential signal comprising a spike of a first polarity (e.g., positive) and a spike of a second polarity (e.g., negative);

generating an intermediate set signal comprising a pulse at each spike of the differential signal having a first polarity;

Generating an intermediate reset signal comprising a pulse at each spike of the differential signal having the second polarity;

generating a reset correction signal comprising pulses when the digital output signal switches between a first logical value and a second logical value and while the intermediate set signal comprises pulses having a duration above a certain time interval;

Generating a correction reset signal comprising a pulse of the intermediate reset signal and a pulse of the reset correction signal; and

The digital output signal is asserted in response to detecting a pulse in the correction set signal and deasserted in response to detecting a pulse in the correction reset signal.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

Fig. 1 to 7 have been described above;

FIG. 8 is a timing diagram of an exemplary waveform including signals in a conventional receiver circuit, for example, in an isolated communication channel for a driver device;

FIG. 9 is an exemplary circuit block diagram of a receiver circuit, e.g., for use in an isolated communication channel of a driver device, in accordance with one or more embodiments of the present disclosure;

FIG. 10 is an exemplary circuit block diagram of a gate level implementation of a portion of the receiver circuit of FIG. 9 in accordance with one or more embodiments of the present description; and

Fig. 11 is a timing diagram of exemplary waveforms including signals in the receiver circuit of fig. 9, according to one or more embodiments of the present disclosure.

Detailed Description

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of embodiments of the present description. Embodiments may be obtained without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

In the context of this specification, reference to "an embodiment" or "one embodiment" is intended to mean that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present at one or more locations in this specification do not necessarily refer to the same embodiment. Furthermore, the particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Headings/references used herein are for convenience only and thus do not limit the scope of protection or the embodiments.

In the drawings attached hereto, identical parts or elements are denoted by identical reference numerals unless the context indicates otherwise, and corresponding descriptions will not be repeated for the sake of brevity.

One or more embodiments relate to a receiver circuit configured to reject spurious pulses SP generated in set and reset signals COMP _N and COMP _P due to unwanted oscillations of differential signal Vd (e.g., ringing effects caused by common mode voltage transients applied at the input of the receiver circuit) to improve Common Mode Transient Immunity (CMTI). By introducing a detailed description of an exemplary embodiment, reference may first be made to fig. 8, which is a timing diagram including exemplary waveforms (substantially reproducing the content of fig. 7) of signals in a conventional receiver circuit 104. Here, it is shown that the duration T _r of pulses FP of the set signal COMP _N and reset signal COMP _P (e.g., pulses generated at the edges of the clock signal CLK and at the edges of the input signal PWM _IN) that are active for proper operation (e.g., proper signal decoding) of the set reset flip-flop 46 are typically within a certain range (e.g., between 1ns and 2 ns), while the duration T _s of spurious pulses SP of the set signal COMP _N and reset signal COMP _P due to common mode transients and ringing effects are longer, i.e., longer than the duration of the maximum duration of pulses FP (e.g., higher than 2ns, e.g., about 10 ns). Accordingly, one or more embodiments rely on an improved receiver architecture that includes logic configured to correct the value of the output signal PWM _RX generated by the flip-flop 46 by generating a correction set signal and a correction reset signal if:

i) The duration of the pulses generated at the outputs of comparators 42 and 44 (i.e., the pulses of signals COMP _N and COMP _P) is above a certain threshold, where the value of the threshold is above the maximum duration T _r allowed by the functional pulse FP (which indicates that the pulse is indeed a spurious pulse); and

Ii) commutation of the output signal PWM _RX is detected (which indicates that spurious pulses do have to be corrected, as otherwise it would force the output signal PWM _RX to the wrong value).

Accordingly, one or more embodiments may relate to a receiver circuit 104' as shown in the circuit block diagram of fig. 9, wherein components or elements similar to those described with reference to previous figures are denoted by the same or similar reference numerals and corresponding descriptions are not repeated for the sake of brevity. In particular, the receiver circuit 104' includes a logic circuit 90, the logic circuit 90 being disposed between the output terminals of the comparators 42, 44 and the input terminal of the set-reset flip-flop 46. Logic circuit 90 receives "raw" set signal COMP _N and reset signal COMP _P, which may be affected by spurious pulses, and reconstructed PWM signal PWM _RX generated by flip-flop 46. The logic circuit 90 is configured to generate a "correct" set signal COMP ' _N and a "correct" reset signal COMP ' _P, which are propagated to the flip-flop 46 (where the signal COMP ' _N may be supplemented as described above with reference to fig. 3), and to generate a reconstructed PWM signal PWM _RX, which may be free of spurious pulses, but suitable for properly driving the output switching stages 105, HS, LS such that the output PWM signal PWM _OUT is free of spurious pulses, as discussed further below. In particular, one or more embodiments rely on the fact that signal PWM _RX may include spurious pulses, but the duration of such spurious pulses is reduced to a value below propagation delay T _delay of the output switching stage, such that these pulses do not affect the value of output PWM signal PWM _OUT.

In particular, the logic circuit 90 is configured to:

Detecting the presence of spurious pulses in the signal COMP _N、COMP_P based on the duration of the pulses (e.g., selecting only pulses longer than the threshold T _count, where T _count is selected to be longer than the maximum duration of the functional pulses T _r);

Discarding spurious pulses that do not adversely affect the value of reconstructed PWM signal PWM _RX (e.g., in the examples considered herein, spurious pulses of signal COMP _N that occur while signal PWM _IN has a high logic value, and spurious pulses of signal COMP _P that occur while signal PWM _IN has a low logic value); and

In response to detecting a spurious pulse in one of the signals COMP _N、COMP_P and the spurious pulse not being discarded, a correction pulse is generated in the other of the signals COMP _N、COMP_P, producing a correction set signal COMP '_N and a correction reset signal COMP' _P to force the reconstructed PWM signal PWM _RX back to its correct value within a period of time T _count that is shorter than the propagation delay T _delay of the output switching stage, such that the value of the output PWM signal PWM _OUT does not switch to an erroneous value.

Fig. 10 is an exemplary circuit block diagram of a possible gate level implementation of logic circuit 90, and fig. 11 is a time diagram of an exemplary waveform including signals in receiver circuit 104', which illustrates possible operation of the receiver circuit.

The logic circuit 90 includes a first asymmetric buffer 91 _P configured to receive the "raw" reset signal COMP _P and to generate a first detection signal COMP _P,DLY. Signal COMP _P,DLY corresponds substantially to a replica of signal COMP _P, wherein the active edge of the signal (e.g., a falling edge in the example considered herein, wherein reset signal COMP _P is normally high) is delayed by an interval T _count that is higher than the expected duration T _r of the functional pulse FP. Thus, as shown in fig. 11, signal COMP _P,DLY indicates a spurious pulse SP of reset signal COMP _P, so long as pulses of duration above T _count are propagated with delayed active edges (e.g., falling edges) and with almost unaffected inactive edges (e.g., rising edges), and pulses of duration below T _count are not propagated from signal COMP _P to signal COMP _P,DLY (e.g., signal COMP _P,DLY remains at a high logic level during these pulses). In particular, in one or more embodiments, the first asymmetric buffer 91 _P may include a first inverter circuit including a pull-up transistor and a pull-down transistor arranged in series between the logic supply voltage V _DD and the logic reference voltage V _SS and driven by the signal COMP _P. The capacitor is coupled in parallel to the conduction channel of the pull-down transistor (e.g., between the output node of the inverter circuit and the logic reference voltage V _SS) to delay the active edge (e.g., the falling edge). The inactive edge (e.g., rising edge) remains fast to discharge the capacitor and prepare the buffer for the next detection action. The second inverter circuit is coupled to the output of the first inverter circuit, all to generate a signal COMP _P,DLY having the above characteristics.

Similarly, the logic circuit 90 includes a second asymmetric buffer 91 _N configured to receive the "raw" set signal COMP _N and to generate a second detection signal COMP _N,DLY. Signal COMP _N,DLY corresponds substantially to a replica of signal COMP _N, wherein the active edges of the signal (e.g., the falling edges in the examples considered herein, with set signal COMP _N being normally high) are delayed by interval T _count. Thus, as shown in fig. 11, signal COMP _N,DLY indicates a spurious pulse SP that sets signal COMP _N, so long as pulses of duration above T _count are propagated with delayed active edges (e.g., falling edges) and little affected inactive edges (e.g., rising edges), and pulses of duration below T _count do not propagate from signal COMP _N to signal COMP _N,DLY (e.g., signal COMP _N,DLY remains at a high logic level during these pulses). In particular, in one or more embodiments, the second asymmetric buffer 91 _N may include a first inverter circuit including a pull-up transistor and a pull-down transistor arranged in series between the logic supply voltage V _DD and the logic reference voltage V _SS and driven by the signal COMP _N. The capacitor is coupled in parallel to the conduction channel of the pull-down transistor (e.g., between the output node of the inverter circuit and the logic reference voltage V _SS) to delay the active edge (e.g., the falling edge). The inactive edge (e.g., rising edge) remains fast to discharge the capacitor and prepare the buffer for the next detection action. The second inverter circuit is coupled to the output of the first inverter circuit and thereby generates a signal COMP _N,DLY having the characteristics described above.

Further, the logic circuit 90 includes an edge detector circuit 92, the edge detector circuit 92 coupled to the output of the flip-flop 46 and configured to generate an edge detection signal ED that indicates a transition (e.g., an edge) of the reconstructed PWM signal PWM _RX, as shown in fig. 11. In particular, the edge detection signal ED may be normally high and may include a low pulse at each occurrence of a transition (e.g., edge) of the signal PWM _RX. The duration T _ED of such a low pulse may be longer than T _count. In particular, in one or more embodiments, edge detector circuit 92 may include a delay circuit block configured to generate a replica of signal PWM _RX delayed by interval T _ED, an exclusive-or logic gate configured to apply exclusive-or logic processing to signal PWM _RX and its delayed replica, and an inverter circuit coupled to the output of the exclusive-or logic gate to generate edge detection signal ED having the characteristics described above.

Furthermore, the logic circuit 90 comprises a first gating logic gate 93 _P, the first gating logic gate 93 _P being configured to combine the first detection signal COMP _P,DLY and the edge detection signal ED to discard spurious pulses of the signal COMP _P,DLY that do not correspond to transitions of the reconstructed PWM signal PWM _RX, thereby generating a set correction signal set _new, the set correction signal set _new indicating a corrective action that has to be implemented in the original set signal COMP _N to generate the correction set signal COMP' _N. In particular, set correction signal set _new may be normally high and may include a low pulse when both signals COMP _P,DLY and ED have a low pulse. Thus, in one or more embodiments, the first gating logic gate may include an or gate 93 _P configured to apply or logic processing to signals COMP _P,DLY and ED to produce signal set _new.

Similarly, the logic circuit 90 comprises a second gating logic gate 93 _N, the second gating logic gate 93 _N being configured to combine the second detection signal COMP _N,DLY and the edge detection signal ED to discard spurious pulses of the signal COMP _N,DLY that do not correspond to transitions of the reconstructed PWM signal PWM _RX, thereby generating a reset correction signal reset _new, which reset _new indicates a corrective action that has to be implemented in the original reset signal COMP _P to generate the correction reset signal COMP' _P. In particular, the reset correction signal reset _new may be normally high and may include a low pulse when both signals COMP _N,DLY and ED have a low pulse. Thus, in one or more embodiments, the second gating logic gate may include an or gate 93 _N configured to apply or logic processing to signals COMP _N,DLY and ED to produce signal reset _new.

Further, the logic circuit 90 comprises a first correction logic gate 94 _P, the first correction logic gate 94 _P being configured to combine the set correction signal set _new and the original set signal COMP _N to add to the signal COMP _N a correction pulse intended to restore the correct value of the signal PWM _RX after the spurious reset pulse, thereby generating the correction set signal COMP' _N. In particular, the correction set signal COMP' _N may be normally high and may include a low pulse corresponding to the pulses of signals COMP _N and set _new. Thus, in one or more embodiments, the first correction logic gate 94 _P may include an and gate 94 _P configured to apply and logic processing to the signals COMP _N and set _new to generate a signal COMP' _N.

Similarly, the logic circuit 90 includes a second correction logic gate 94 _N, the second correction logic gate 94 _N being configured to combine the reset correction signal reset _new and the original reset signal COMP _P to add to the signal COMP _P a correction pulse intended to restore the correct value of the signal PWM _RX after the spurious set pulse, thereby generating the correction reset signal COMP' _P. In particular, the correction reset signal COMP' _P may be normally high and may include a low pulse corresponding to the pulses of signals COMP _P and reset _new. Thus, in one or more embodiments, the second correction logic gate 94 _N may include an and gate 94 _N configured to apply and logic processing to the signals COMP _P and reset _new to generate the signal COMP' _P.

As shown in fig. 10, the correction signals COMP ' _N and COMP ' _P are then used as set and reset signals for the set-reset (S-R) flip-flop 46 of the receiver 104', as described with reference to fig. 3. Thus, flip-flop 46 receives signal COMP '_N (possibly supplemented by an inverter stage) at its clock input terminal C _P and signal COMP' _P at its reset input terminal C _D to generate the reconstructed PWM signal PWM _RX.

Optionally, the first gating logic gate 93 _P may also be configured to receive the signal COMP _P and combine it with the signals COMP _P,DLY and ED such that the inactive edges (e.g., rising edges) of the signal COMP _P propagate quickly to the set correction signal set _new. Indeed, as already discussed previously, the asymmetric buffer 91 _P is configured to substantially delay (e.g., at interval T _count) an active edge (e.g., a falling edge) of the signal COMP _P while passing an inactive edge (e.g., a rising edge) without substantial delay. However, if the signal COMP _P is not propagated directly to gate 93 _P, the inactive edge is propagated via the two cascaded inverter circuits of asymmetric buffer 91 _P. Alternatively, by propagating signal COMP _P directly to gate 93 _P, propagation delay of asymmetric buffer 91 _P can be avoided for inactive edges. Thus, in one or more embodiments, the first gating logic gate may include an or gate 93 _P, or gate 93 _P configured to apply or logic processing to signals COMP _P,DLY、COMP_P and ED to produce signal set _new. Similarly, optionally, second gating logic 93 _N may also be configured to receive signal COMP _N and combine it with signals COMP _N,DLY and ED such that the inactive edges (e.g., rising edges) of signal COMP _N propagate quickly to reset correction signal reset _new. Thus, in one or more embodiments, the second gating logic gate may include an or gate 93 _N, or gate 93 _N configured to apply or logic processing to signals COMP _N,DLY、COMP_N and ED to generate signal reset _new.

Fig. 11 is a timing diagram of exemplary waveforms comprising signals in the receiver circuit 104' of fig. 10, illustrating possible operation of the receiver circuit. Here, by way of example, spurious pulses SP1 of signal COMP _P are shown forcing reconstructed signal PWM _RX to a low logic value (while signal PWM _RX is expected to remain at a high logic value to replicate signal PWM _IN). The spurious pulse SP1 is detected by the signal COMP _P,DLY switching to a low logic value because of its duration longer than T _count. At the same time, the edge detection signal ED also switches to a low logic value, because the signal PWM _RX has switched due to spurious pulses. Since signal COMP _P,DLY indicates the presence of a spurious reset pulse and signal ED indicates that signal PWM _RX has changed its state, a correction set pulse CP1 is generated in signal set _new and propagates to correction set signal COMP' _N so that flip-flop 46 is set again and signal PWM _RX switches to its previous (correct) state again. The signal PWM _RX only holds the error value for an interval T _count that is much lower than the propagation delay T _delay of the pre-driver circuit 105, so that the output PWM _OUT of the pre-driver circuit has no time to switch and is unaffected. Furthermore, due to the gating effect of the signal ED, no correction reset pulse is generated even when the spurious pulse SP2 of the signal COMP _N is detected (see signal reset _new, which remains high logic value even during SP 2), since in this case the signal PWM _RX already has the correct value and the spurious pulse SP2 does not destroy it.

Thus, one or more embodiments may prove advantageous in that they provide a receiver circuit with an advanced robustness against common mode noise by using logic circuitry for correcting spurious signals generated by ringing (only) added in the decoding circuit. Thus, one or more embodiments rely on simple implementation compatible with conventional transmitter/receiver architectures (e.g., including only additional logic gates compared to conventional solutions).

Without affecting the basic principle, the details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without thereby departing from the scope of protection.

The scope of protection is determined by the appended claims.

A receiver circuit (104') may be summarized as including: a pair of input nodes configured to receive a differential signal (Vd) therebetween, the differential signal (Vd) comprising a spike of a first polarity and a spike of a second polarity; an output node configured to generate a digital output signal (PWM _RX) from the differential signal (Vd); -a first comparator circuit (42) configured to receive the differential signal (Vd) and to generate an intermediate set signal (COMP _N), the intermediate set signal (COMP _N) comprising a pulse at each spike of the differential signal (Vd) having the first polarity; a second comparator circuit (44) configured to receive the differential signal (Vd) and to generate an intermediate reset signal (COMP _P), the intermediate reset signal (COMP _P) comprising a pulse at each spike of the differential signal (Vd) having the second polarity; -logic circuitry (90) configured to receive the intermediate set signal (COMP _N), the intermediate reset signal (COMP _P) and the digital output signal (PWM _RX), and further configured to: detecting (92, ED) whether the digital output signal (PWM _RX) switches between a first logic value and a second logic value; -detecting (91 _P,COMP_P,DLY) whether said intermediate reset signal (COMP _P) comprises a pulse (SP 1, SP 3) having a duration higher than a certain time interval (T _count); -generating (93 _P) a set correction signal (set _new) comprising pulses (SP 1, SP 3) having a duration higher than said specific time interval (T _count) when said digital output signal (PWM _RX) switches between a first logic value and a second logic value and at the same time said intermediate reset signal (COMP _P) comprises pulses; -generating (94 _P) a correction set signal (COMP' _N) comprising a pulse of said intermediate set signal (COMP _N) and a pulse of said set correction signal (set _new); -detecting (91 _N,COMP_N,DLY) whether said intermediate set signal (COMP _N) comprises a pulse (SP 2) having a duration higher than said specific time interval (T _count); -generating (93 _N) a reset correction signal (reset _new) comprising pulses when the digital output signal (PWM _RX) switches between a first logic value and a second logic value and at the same time the intermediate set signal (COMP _N) comprises pulses (SP 2) having a duration higher than the specific time interval (T _count); and generating (94 _N) a correction reset signal (COMP' _P) comprising a pulse of the intermediate reset signal (COMP _P) and a pulse of the reset correction signal (reset _new); and an output control circuit (46) configured to receive the correction set signal (COMP '_N) and the correction reset signal (COMP' _P) and further configured to assert the digital output signal (PWM _RX) in response to detecting a pulse in the correction set signal (COMP '_N) and to de-assert the digital output signal (PWM _RX) in response to detecting a pulse in the correction reset signal (COMP' _P).

The logic circuit (90) may include: -a first asymmetric buffer circuit (91 _P) configured to receive the intermediate reset signal (COMP _P) and to generate a first detection signal (COMP _P,DLY) by passing an active edge of the intermediate reset signal (COMP _P) with a delay equal to the certain time interval (T _count) and passing an inactive edge of the intermediate reset signal (COMP _P) without substantial delay; -a first gating logic gate (93 _P) configured to pass the first detection signal (COMP _P,DLY) when the digital output signal (PWM _RX) switches between a first logic value and a second logic value, otherwise mask the first detection signal (COMP _P,DLY) to generate the set correction signal (set _new); -a second asymmetric buffer circuit (91 _N) configured to receive the intermediate set signal (COMP _N) and to generate a second detection signal (COMP _N,DLY) by passing an active edge of the intermediate set signal (COMP _N) with a delay equal to the specific time interval (T _count) and passing an inactive edge of the intermediate set signal (COMP _N) without substantial delay; and a second gating logic gate (93 _N) configured to pass the second detection signal (COMP _N,DLY) when the digital output signal (PWM _RX) switches between the first logic value and the second logic value, and to otherwise mask the second detection signal (COMP _N,DLY) to generate the reset correction signal (reset _new).

The first asymmetric buffer circuit (91 _P) may include: a first inverter circuit including a first pull-up transistor and a first pull-down transistor alternately driven by the intermediate reset signal (COMP _P); a first capacitor coupled in parallel to the first pull-down transistor; and a second inverter circuit coupled to the first inverter circuit to generate the first detection signal (COMP _P,DLY); and wherein the second asymmetric buffer circuit (91 _N) may include: a third inverter circuit including a second pull-up transistor and a second pull-down transistor alternately driven by the intermediate set signal (COMP _N); a second capacitor coupled in parallel to the second pull-down transistor; and a fourth inverter circuit coupled to the third inverter circuit to generate the second detection signal (COMP _N,DLY).

The logic circuit (90) may include: -a first correction logic gate (94 _P) configured to pass a pulse of said intermediate set signal (COMP _N) and a pulse of said set correction signal (set _new) to generate said corrected set signal (COMP' _N); and a second correction logic gate (94 _N) configured to pass a pulse of the intermediate reset signal (COMP _P) and a pulse of the reset correction signal (reset _new) to generate the correction reset signal (COMP' _P).

The logic circuit (90) may include an edge detector circuit (92), the edge detector circuit (92) configured to receive the digital output signal (PWM _RX) and to generate an edge detection signal (ED) that includes pulses at each commutation of the digital output signal (PWM _RX) between a first logic value and a second logic value, wherein the edge detector circuit (92) may include: a delay circuit block configured to receive the digital output signal (PWM _RX) and propagate the digital output signal (PWM _RX) with a corresponding delay (T _ED) to produce a delayed digital output signal; and an exclusive or gate configured to combine the digital output signal (PWM _RX) and the delayed digital output signal to produce the edge detection signal (ED), wherein the respective delay (T _ED) may be higher than the specific time interval (T _count).

The intermediate reset signal (COMP _P) and the first detection signal (COMP _P,DLY) may be normally high, the active edge of the intermediate reset signal (COMP _P) may be a falling edge, and the inactive edge of the intermediate reset signal (COMP _P) may be a rising edge; the intermediate set signal (COMP _N) and the second detection signal (COMP _N,DLY) may be normally high, the active edge of the intermediate set signal (COMP _N) may be a falling edge, and the inactive edge of the intermediate set signal (COMP _N) may be a rising edge; the edge detection signal (ED) may be normally high and include a low pulse at each commutation of the digital output signal (PWM _RX) between a first logic value and a second logic value; the first gating logic gate (93 _P) may comprise an or gate configured to apply an or logic process to the first detection signal (COMP _P,DLY) and the edge detection signal (ED) to generate the set correction signal (set _new); the second gating logic gate (93 _N) may include an or gate configured to apply or logic processing to the second detection signal (COMP _N,DLY) and the edge detection signal (ED) to generate the reset correction signal (reset _new); the first correction logic gate (94 _P) may include an and gate configured to apply an and logic process to the set correction signal (set _new) and the intermediate set signal (COMP _N) to produce the correction set signal (COMP' _N); and the second correction logic gate (94 _N) may include an and gate configured to apply and logic processing to the reset correction signal (reset _new) and the intermediate reset signal (COMP _P) to generate the correction reset signal (COMP' _P).

The first gating logic gate (93 _P) may also be configured to apply an or logic process to the intermediate reset signal (COMP _P) to produce the set correction signal (set _new), and the second gating logic gate (93 _N) may also be configured to apply an or logic process to the intermediate set signal (COMP _N) to produce the reset correction signal (reset _new).

The output control circuit may include a set-reset flip-flop (46), the set-reset flip-flop (46) having a clock input terminal (C _P) driven by the correction set signal (COMP '_N) and a reset input terminal (C _D) driven by the correction reset signal (COMP' _P) to generate the digital output signal (PWM _RX) at a data output terminal (Q) of the set-reset flip-flop (46).

The receiver circuit (104') may include an amplifier circuit (40), the amplifier circuit (40) being configured to receive the differential signal (Vd) and pass an amplified copy of the differential signal (Vd) to the first comparator circuit (42) and the second comparator circuit (44).

The receiver circuit (104') may include a driver circuit including a half-bridge circuit disposed between a positive supply voltage pin (VH) and a reference supply voltage pin (VL) and driven by the digital output signal (PWM _RX) to generate an output switching signal (PWM _OUT).

An isolated driver device (10) may be summarized as including a first semiconductor die (10 a) and a second semiconductor die (10 b), wherein the first semiconductor die (10 a) includes: an input pin (101) configured to receive a digital input signal (PWM _IN); -a transmitter circuit (102) configured to receive the digital input signal (PWM _IN) and to generate a pair of complementary digital signals (OUT _P,OUT_N), wherein a first one (OUT _P) of the complementary digital signals is a replica of the digital input signal (PWM _IN) and is generated at a first output node of the transmitter circuit (102), and a second one (OUT _N) of the complementary digital signals is a complementary one of the digital input signals (PWM _IN) and is generated at a second output node of the transmitter circuit (102); and a galvanic isolation barrier comprising a first isolation capacitor (103P) and a second isolation capacitor (103N), the first isolation capacitor (103P) having a first terminal coupled to the first output node of the transmitter circuit (102), the second isolation capacitor (103N) having a first terminal coupled to the second output node of the transmitter circuit (102), whereby a differential signal (Vd) is generated between a second terminal of the first isolation capacitor (103P) and a second terminal of the second isolation capacitor (103N), the differential signal (Vd) comprising a spike of a first polarity at each rising edge of the digital input signal (PWM _IN), And a spike of a second polarity at each falling edge of the digital input signal (PWM _IN); wherein the second semiconductor die (10 b) comprises a receiver circuit (104') according to any of the preceding claims; and wherein a first input node of the receiver circuit (104 ') is electrically coupled to a second terminal of the first isolation capacitor (103P), and a second input node of the receiver circuit (104') is electrically coupled to a second terminal of the second isolation capacitor (103N) to receive the differential signal (Vd).

An electronic system may be summarized as including a processing unit and an isolated driver device (10), the processing unit configured to generate the digital input signal (PWM _IN) received by the isolated driver device (10).

A method of decoding a differential signal (Vd) into a digital output signal (PWM _RX), the method may be summarized as comprising: receiving a differential signal (Vd) comprising peaks of a first polarity and peaks of a second polarity; generating an intermediate set signal (COMP _N), the intermediate set signal (COMP _N) comprising a pulse at each spike of the differential signal (Vd) having the first polarity; generating an intermediate reset signal (COMP _P), the intermediate reset signal (COMP _P) comprising a pulse at each spike of the differential signal (Vd) having the second polarity; detecting (92, ED) whether the digital output signal (PWM _RX) switches between a first logic value and a second logic value; -detecting (91 _P,COMP_P,DLY) whether said intermediate reset signal (COMP _P) comprises a pulse (SP 1, SP 3) having a duration higher than a certain time interval (T _count); -generating (93 _P) a set correction signal (set _new) comprising pulses (SP 1, SP 3) having a duration higher than said specific time interval (T _count) when said digital output signal (PWM _RX) switches between said first logic value and said second logic value and at the same time said intermediate reset signal (COMP _P) comprises pulses; -generating (94 _P) a correction set signal (COMP' _N) comprising a pulse of said intermediate set signal (COMP _N) and a pulse of said set correction signal (set _new); -detecting (91 _N,COMP_N,DLY) whether said intermediate set signal (COMP _N) comprises a pulse (SP 2) having a duration higher than said specific time interval (T _count); -generating (93 _N) a reset correction signal (reset _new) comprising pulses when the digital output signal (PWM _RX) switches between the first logical value and the second logical value and at the same time the intermediate set signal (COMP _N) comprises pulses (SP 2) having a duration higher than the specific time interval (T _count); -generating (94 _N) a correction reset signal (COMP' _P) comprising a pulse of said intermediate reset signal (COMP _P) and a pulse of said reset correction signal (reset _new); and asserting the digital output signal (PWM _RX) in response to detecting a pulse in the correction set signal (COMP '_N) and deasserting the digital output signal (PWM _RX) in response to detecting a pulse in the correction reset signal (COMP' _P).

These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A device of a receiver circuit, the receiver circuit comprising:

a pair of input nodes configured to receive a differential signal therebetween, the differential signal comprising a spike of a first polarity and a spike of a second polarity;

An output node configured to generate a digital output signal from the differential signal;

a first comparator circuit configured to receive the differential signal and to generate an intermediate set signal comprising a pulse at each spike of the differential signal having the first polarity;

a second comparator circuit configured to receive the differential signal and to generate an intermediate reset signal comprising a pulse at each spike of the differential signal having the second polarity;

Logic configured to receive the intermediate set signal, the intermediate reset signal, and the digital output signal, and to generate a correction set signal and a correction reset signal; and

An output control circuit configured to receive the correction set signal and the correction reset signal, and further configured to assert the digital output signal based on the correction set signal and the correction reset signal.

2. The device circuit of claim 1, wherein the output circuit is configured to assert the digital output signal in response to detecting a pulse in the correction set signal and to de-assert the digital output signal in response to detecting a pulse in the correction reset signal.

3. The device of claim 2, wherein the logic circuit is configured to:

detecting whether the intermediate reset signal comprises a pulse having a duration above a certain time interval;

Generating a set correction signal comprising pulses when the digital output signal switches between a first logic value and a second logic value and while the intermediate reset signal comprises pulses of duration above the particular time interval;

detecting whether the intermediate set signal includes pulses having a duration greater than the particular time interval;

Generating a reset correction signal comprising pulses when said digital output signal switches between a first logic value and a second logic value and while said intermediate set signal comprises pulses of duration above said specific time interval; and

Generating a correction reset signal comprising a pulse of said intermediate reset signal and a pulse of said reset correction signal.

4. The device of claim 3, wherein the logic circuit comprises:

A first asymmetric buffer circuit configured to receive the intermediate reset signal and to generate a first detection signal by passing an active edge of the intermediate reset signal with a delay equal to the particular time interval and passing an inactive edge of the intermediate reset signal without substantial delay;

a first gating logic gate configured to pass the first detection signal when the digital output signal switches between a first logic value and a second logic value, and otherwise mask the first detection signal to generate the set correction signal;

A second asymmetric buffer circuit configured to receive the intermediate set signal and to generate a second detection signal by passing active edges of the intermediate set signal with a delay equal to the particular time interval and passing inactive edges of the intermediate set signal without substantial delay; and

A second gating logic gate configured to pass the second detection signal when the digital output signal switches between a first logic value and a second logic value, and otherwise mask the second detection signal to generate the reset correction signal.

5. The device of claim 4, wherein the first asymmetric buffer circuit comprises:

A first inverter circuit including a first pull-up transistor and a first pull-down transistor alternately driven by the intermediate reset signal;

A first capacitor coupled in parallel to the first pull-down transistor; and

A second inverter circuit coupled to the first inverter circuit to generate the first detection signal;

and wherein the second asymmetric buffer circuit comprises:

A third inverter circuit including a second pull-up transistor and a second pull-down transistor alternately driven by the intermediate set signal;

A second capacitor coupled in parallel to the second pull-down transistor; and

A fourth inverter circuit coupled to the third inverter circuit to generate the second detection signal.

6. The device of claim 4, wherein the logic circuit comprises:

a first correction logic gate configured to pass pulses of the intermediate set signal and pulses of the set correction signal to generate the corrected set signal; and

A second correction logic gate configured to pass pulses of the intermediate reset signal and pulses of the reset correction signal to generate the correction reset signal.

7. The device of claim 6, wherein the logic circuit comprises an edge detector circuit configured to receive the digital output signal and to generate an edge detection signal comprising pulses at each commutation of the digital output signal between a first logical value and a second logical value, wherein the edge detector circuit comprises:

A delay circuit block configured to receive the digital output signal and propagate the digital output signal with a corresponding delay to produce a delayed digital output signal; and

An exclusive or gate configured to combine the digital output signal and the delayed digital output signal to generate the edge detection signal,

Wherein the respective delay is higher than the particular time interval.

8. The device of claim 7, wherein:

the intermediate reset signal and the first detection signal are normally high, an active edge of the intermediate reset signal is a falling edge, and an inactive edge of the intermediate reset signal is a rising edge;

the intermediate set signal and the second detection signal are normally high, an active edge of the intermediate set signal is a falling edge, and an inactive edge of the intermediate set signal is a rising edge;

The edge detection signal is normally high and comprises a low pulse at each commutation of the digital output signal between a first logic value and a second logic value;

the first gating logic gate includes an or gate configured to apply an or logic process to the first detection signal and the edge detection signal to generate the set correction signal;

the second gating logic gate includes an or gate configured to apply an or logic process to the second detection signal and the edge detection signal to generate the reset correction signal;

The first correction logic gate includes an and gate configured to apply an and logic process to the set correction signal and the intermediate set signal to generate the correction set signal; and

The second correction logic gate includes an and gate configured to apply an and logic process to the reset correction signal and the intermediate reset signal to generate the correction reset signal.

9. The device of claim 8, wherein

The first gating logic gate is further configured to apply OR logic processing to the intermediate reset signal to generate the set correction signal, and

The second gating logic gate is further configured to apply an OR logic process to the intermediate set signal to generate the reset correction signal.

10. The device of claim 3, wherein the output control circuit comprises a set-reset flip-flop having a clock input terminal driven by the correction set signal and a reset input terminal driven by the correction reset signal to generate the digital output signal at a data output terminal of the set-reset flip-flop.

11. A device according to claim 3, comprising an amplifier circuit configured to receive the differential signal and pass an amplified copy of the differential signal to the first and second comparator circuits.

12. A device according to claim 3, comprising a driver circuit comprising a half-bridge circuit arranged between a positive supply voltage pin and a reference supply voltage pin and driven by the digital output signal to generate an output switching signal.

13. The device of claim 1, comprising an isolation driver device, the isolation driver device comprising:

a first semiconductor die, comprising:

an input pin configured to receive a digital input signal;

A transmitter circuit configured to receive the digital input signal and:

Generating a first complementary digital signal at a first output node, the first complementary digital signal being a copy of the digital input signal; and

Generating a second complementary digital signal at a second output node, the second complementary digital signal being a complement of the digital input signal;

A galvanic isolation barrier comprising a first isolation capacitor having a first terminal coupled to the first output node of the transmitter circuit and a second isolation capacitor having a first terminal coupled to the second output node of the transmitter circuit such that a differential signal is generated between the second terminal of the first isolation capacitor and the second terminal of the second isolation capacitor, the differential signal comprising a spike of a first polarity at each rising edge of the digital input signal and a spike of a second polarity at each falling edge of the digital input signal; and

A second semiconductor die comprising the receiver circuit, wherein a first input node of the receiver circuit is electrically coupled to a second terminal of the first isolation capacitor, and a second input node of the receiver circuit is electrically coupled to a second terminal of the second isolation capacitor to receive the differential signal.

14. The device of claim 13, comprising a processing unit configured to generate the digital input signal received by the isolation driver device.

15. A method of decoding a differential signal into a digital output signal, the method comprising:

Receiving the differential signal;

generating an intermediate set signal based on the differential signal;

Generating an intermediate reset signal based on the differential signal;

Generating a set correction signal based on the digital output signal and the intermediate reset signal;

Generating a correction set signal based on the intermediate set signal and the set correction signal;

generating a reset correction signal based on the digital output signal and the intermediate set signal;

generating a corrected reset signal based on the intermediate reset signal and the reset correction signal; and

Generating the digital output signal based on the correction set signal and the correction reset signal; the digital output signal is asserted in response to detecting a pulse in the correction set signal and deasserted in response to detecting a pulse in the correction reset signal.

16. The method of claim 15, wherein the differential signal comprises a spike of a first polarity and a spike of a second polarity, the method comprising:

generating the intermediate set signal having pulses at each spike of the differential signal having the first polarity; and

The intermediate reset signal is generated with pulses at each spike of the differential signal with the second polarity.

17. The method of claim 16, comprising:

Generating said set correction signal comprising pulses when said digital output signal toggles between a first logic value and a second logic value and while said intermediate reset signal comprises pulses having a duration above said certain time interval;

Generating the correction set signal comprising a pulse of the intermediate set signal and a pulse of the set correction signal;

Generating said reset correction signal having pulses when said digital output signal toggles between a first logic value and a second logic value and while said intermediate set signal includes pulses having a duration above said specific time interval;

generating the correction reset signal comprising a pulse of the intermediate reset signal and a pulse of the reset correction signal; and

18. A receiver circuit, comprising:

A differential input comprising a first input node and a second input node;

A first comparator circuit having an inverting input coupled to the first input node and a non-inverting input coupled to the second input node;

a second comparator circuit having an inverting input coupled to the second input node and a non-inverting input coupled to the first input node;

Logic circuitry having a first input coupled to an output of the first comparator and a second input coupled to an output of the second comparator; and

A flip-flop having a first input coupled to a first output of the logic circuit, a second input coupled to a second output of the logic circuit, and an output terminal, wherein the logic circuit includes a third input coupled to an output of the flip-flop.

19. The receiver circuit of claim 18, wherein the logic circuit comprises:

a first inverter;

A second inverter;

A first or gate comprising a first input coupled to a first input of the logic circuit, a second input coupled to a third input of the logic circuit, and a third input coupled to an output of the first inverter; and

A second or gate comprising a first input coupled to the second input of the logic circuit, a second input coupled to the third input of the logic circuit, and a third input coupled to the output of the second inverter.

20. The receiver circuit of claim 19, wherein the logic circuit comprises:

a first AND gate having a first input coupled to an output of the first OR gate, a second input coupled to a second input of the logic circuit, and an output corresponding to the first output of the logic circuit; and

A second and gate having a first input coupled to an output of the second or gate, a second input coupled to the first input of the logic circuit, and an output corresponding to the second output of the logic circuit.