CN118133735B - Verification method, verification device, electronic equipment and readable storage medium - Google Patents
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Abstract
The embodiment of the invention provides a verification method, a verification device, electronic equipment and a readable storage medium, wherein the verification method comprises the following steps: modifying a chip code of a to-be-designed so as to access data transmitted by each data interface of the to-be-designed into a top layer module of the to-be-designed; burning the design to be tested into a programmable logic area of a programmable logic chip according to the modified chip code; generating a dynamic link library in the verification platform; after each instruction is executed by the design to be tested, collecting a first state value of the design to be tested, and calling a dynamic link library to control the dynamic link library to execute the instruction and output a second state value; and under the condition that the first state value is not matched with the second state value, determining that the design to be tested runs wrong. The embodiment of the invention increases the detail visibility of the design to be tested, can report errors in time when the design to be tested runs wrong, ensures the validity of verification, and is beneficial to debugging and checking the design to be tested in time.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a verification method, a verification device, an electronic device, and a readable storage medium.
Background
In the increasingly complex hardware design nowadays, verification occupies a larger part of time in the whole chip development process, and is a bottleneck in the whole processor development process. To alleviate the verification bottleneck, verification needs to meet two requirements, namely validity and efficiency.
Traditionally, software simulation is the most convenient and most commonly used platform in the verification process. The software simulator accesses the internal state of the design under test (Design Under Test, DUT) by various methods, naturally transitioning to the processor verification domain. The differential Test technique in hardware verification, namely Diff Test, has been widely adopted as a agile verification technique. Diff Test compares the critical signals of the DUT in the software simulator with the instruction set simulator (Instruction Set Simulators, ISS). ISS is a high-level of abstraction implementation of the instruction set architecture (Instruction Set Architecture, ISA), which is the golden reference model. Therefore, diff Test can detect almost all ISA violations in the design.
Although Diff Test is very effective, the slow speed of software emulation prevents its efficiency. Due to the concurrency of the circuits and the requirement on cycle accuracy, software emulation almost cannot fully utilize the parallelism of the multi-core processor. The software simulator is typically run at a speed of 1kHz to 100kHz, which may take hours or days to complete a benchmarking on a real processor for only a few seconds. To improve verification efficiency, hardware emulators and FPGA prototypes are typically used. However, the hardware simulation cost is high, and the signal visibility of the FPGA is poor, so that the verification process is very complicated, and the verification effect of the traditional FPGA prototype verification method is poor.
Disclosure of Invention
The embodiment of the invention provides a verification method, a verification device, electronic equipment and a readable storage medium, which can solve the problems of low verification efficiency and poor verification effect in the related technology.
In order to solve the problems, the embodiment of the invention discloses a verification method which is applied to a verification system, wherein the verification system comprises a programmable logic chip and a verification platform; the method comprises the following steps:
modifying a chip code of a to-be-tested design so as to access data transmitted by each data interface of the to-be-tested design to a top layer module of the to-be-tested design;
burning the design to be tested into a programmable logic area of a programmable logic chip according to the modified chip code;
Generating a dynamic link library in the verification platform; the dynamic link library is used for simulating the operation process of the design to be tested and generating reference data;
After each instruction is executed by the design to be tested, collecting a first state value of the design to be tested, and calling the dynamic link library to control the dynamic link library to execute the instruction and output a second state value;
Comparing the first state value with the second state value;
Under the condition that the first state value is matched with the second state value, controlling the design to be tested to continuously execute the next instruction, and continuously calling the dynamic link library;
and under the condition that the first state value is not matched with the second state value, determining that the design to be tested runs wrong.
Optionally, the first state value and the second state value comprise values of a general purpose register, a control and state register, and a program counter; the comparing the first state value with the second state value includes:
comparing all data contained in the first state value and the second state value under the condition that a preset granularity interval is met;
And under the condition that the preset granularity interval is not met, comparing the value of the general register in the first state value with the value of the general register in the second state value.
Optionally, the programmable logic chip and the verification platform share the same memory module; before comparing the first state value with the second state value, the method further comprises:
Packaging the first state value by taking an instruction as granularity; each data packet comprises a group of first state values corresponding to the design to be tested after executing an instruction;
transmitting the data packet to the storage module;
the comparing the first state value with the second state value includes:
reading the data packet from the storage module, and updating a first structure body according to a first state value in the data packet;
synchronously updating the second state value output by the dynamic link library into a second structure body according to the data packet;
and comparing the first state value recorded in the first structure body with the second state value recorded in the second structure body.
Optionally, the packaging the first state value with the instruction as granularity includes:
after the design to be tested executes an instruction, interrupting the operation of the design to be tested, and collecting a first state value of the design to be tested;
And packaging the acquired first state value, sending a data packet to the storage module, and recovering the operation of the design to be tested so that the design to be tested can continuously execute the next instruction.
Optionally, the programmable logic chip further comprises an interrupt control module; the method further comprises the steps of:
setting the value of the first signal to be a first preset value under the condition that the storage module is full; the first preset value is used for indicating the interrupt control module to interrupt the operation of the design to be tested and the transmission of the data packet;
Setting the value of the first signal to a second preset value under the condition that the last data packet in the storage module is read; the second preset value is used for indicating the interrupt control module to resume the operation of the design to be tested and the transmission of the data packet.
Optionally, the method further comprises:
Under the condition that a target event occurs in the design to be tested, acquiring a third state value of the design to be tested after the design to be tested executes the target event; the target event comprises an event which cannot be simulated by the dynamic link library;
under the condition that the third state value meets the preset condition, determining that the design to be tested runs normally;
and under the condition that the third state value does not meet the preset condition, determining that the design to be tested runs wrong.
On the other hand, the embodiment of the invention discloses a verification device which is applied to a verification system, wherein the verification system comprises a programmable logic chip and a verification platform; the device comprises:
The code modification module is used for modifying the chip code of the to-be-designed so as to access the data transmitted by each data interface of the to-be-designed into the top layer module of the to-be-designed;
the programming module is used for programming the design to be tested to a programmable logic area of a programmable logic chip according to the modified chip code;
the generation module is used for generating a dynamic link library in the verification platform; the dynamic link library is used for simulating the operation process of the design to be tested and generating reference data;
the state value acquisition module is used for acquiring a first state value of the design to be tested after each instruction is executed by the design to be tested, and calling the dynamic link library to control the dynamic link library to execute one instruction and output a second state value;
The comparison module is used for comparing the first state value with the second state value;
The control module is used for controlling the design to be tested to continuously execute the next instruction and continuously call the dynamic link library under the condition that the first state value is matched with the second state value;
And the first determining module is used for determining that the design to be tested runs wrong under the condition that the first state value is not matched with the second state value.
In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions that cause the processor to perform the verification method described above.
The embodiment of the invention also discloses a readable storage medium, which enables the electronic device to execute the verification method when the instructions in the readable storage medium are executed by the processor of the electronic device.
The embodiment of the invention has the following advantages:
In summary, the embodiment of the invention provides a verification method, which modifies the chip code of the design to be tested, accesses the data transmitted by each data interface of the design to be tested to the top layer module of the design to be tested, and burns the design to be tested to the PL area of the FPGA chip according to the modified chip code. In addition, the embodiment of the invention compares the first state value with the second state value once after each instruction is executed by the design to be tested and the dynamic link library, can report errors in time when the design to be tested runs wrong, ensures the validity of verification, can rapidly position the wrong position of the design to be tested according to the comparison result of the first state value and the second state value, and is favorable for debugging and checking the fine granularity of the design to be tested in time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of an embodiment of a verification method of the present invention;
FIG. 2 is a schematic diagram of a verification system of the present invention;
FIG. 3 is a block diagram of a verification device of the present invention;
Fig. 4 is a block diagram of an electronic device according to an example of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Method embodiment
Referring to fig. 1, there is shown a flow chart of steps of an embodiment of a verification method of the present invention, which may include the steps of:
step 101, modifying a chip code of a to-be-designed to access data transmitted by each data interface of the to-be-designed to a top module of the to-be-designed;
Step 102, burning the design to be tested into a programmable logic area of a programmable logic chip according to the modified chip code;
step 103, generating a dynamic link library in the verification platform; the dynamic link library is used for simulating the operation process of the design to be tested and generating reference data;
Step 104, after each instruction is executed by the design to be tested, collecting a first state value of the design to be tested, and calling the dynamic link library to control the dynamic link library to execute one instruction and output a second state value;
step 105, comparing the first state value with the second state value;
Step 106, under the condition that the first state value is matched with the second state value, controlling the design to be tested to continuously execute the next instruction, and continuously calling the dynamic link library;
and 107, determining that the design to be tested runs wrong under the condition that the first state value is not matched with the second state value.
The verification method provided by the embodiment of the invention can be applied to a verification system to verify the design to be tested. Wherein the design under test (Design Under Test, DUT) refers to a circuit design or implementation to be tested in prototype verification. The design under test may be a register conversion stage (REGISTER TRANSFER LEVEL, RTL) circuit, for example, or other hardware designs. It should be noted that the RTL circuit is a common hardware description level circuit. RTL circuits describe the behavior and structure of digital circuits and use a register transfer level of abstraction. RTL circuit descriptions are typically written using Hardware Description Languages (HDL), such as VHDL (VHSIC HARDWARE Description Language), verilog HDL, system Verilog HDL. The designer may use the RTL level description to define and implement the desired digital circuit functions and then use an integration tool to convert the RTL level description to a physical implementation in a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA). In the field of FPGA, chip design and verification, RTL level description is very important for design, verification and debugging. It provides a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and to use appropriate tools for simulation, verification and synthesis, ultimately generating bit stream (bitstream) files that can be configured into FPGA chips to implement specific digital circuit functions.
The verification system of the embodiment of the invention comprises a programmable logic chip and a verification platform. Wherein the programmable logic chip, i.e. the FPGA chip (or the FPGA system-on-chip), not only comprises a programmable gate array circuit, but also comprises one or more on-chip processors. Programmable gate array circuits are commonly referred to as programmable logic (Programmable Logic, PL); the on-chip processor is typically an ARM processor, referred to as a processing system (Processing System, PS). The verification system of the invention can be divided into two parts of hardware and software, wherein the programmable logic chip is used for deploying the hardware part, and the verification platform is used for carrying the software part. For example, the design under test may be burned into a programmable logic chip, with the dynamic link library deployed on the verification platform.
Further, the verification platform in the present invention may be mounted on the PS end of the FPGA chip, or may be mounted in an electronic device, where the electronic device may include, but is not limited to: intelligent terminals, computers, personal digital assistants (Personal DIGITAL ASSISTANT, PDA), tablet computers, and the like. Communication between the programmable logic chip and the verification platform is via a data interface, such as a high-speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIE) interface, a general purpose input output (General Purpose Input Output, GPIO), and so on.
It should be noted that, because the intermediate data generated during the operation of the design to be tested and some signal values or state values to be verified are usually invisible, if verification is performed only according to the final output result of the design to be tested, errors cannot be timely reported, and the error position is difficult to be located, which is not beneficial to debugging the design to be tested. In the embodiment of the invention, the chip code of the design to be tested can be modified before the design to be tested is burnt into the FPGA chip, and the data transmitted by each data interface of the design to be tested is accessed into the top layer module of the design to be tested so as to collect the intermediate data of the design to be tested and the state value in the running process. Specifically, the chip code of the design to be tested can be analyzed, and a data transmission path pointing to the top layer module is added for each data interface of the design to be tested, so that the data transmitted by each data interface of the design to be tested is accessed to the top layer module on the basis of not changing the original running logic of the design to be tested, and the external module or component of the design to be tested can be conveniently obtained. The top module is a module containing all other modules in the design to be tested, and the top module is not instantiated in any other module. After the data in the design to be tested is accessed to the top layer module, the data to be verified can be led out from the top layer module and accessed to the verification system, so that the data can be conveniently analyzed and verified.
Compared with the traditional FPGA prototype verification method, the method and the device have the advantages that the chip codes of the to-be-tested design are modified, the data transmitted by each data interface of the to-be-tested design are accessed to the top layer module of the to-be-tested design, the to-be-tested design is burnt to the PL area of the FPGA chip according to the modified chip codes, the acquisition and analysis of intermediate data and state values generated in the running process of the to-be-tested design are facilitated, and the detail visibility of the to-be-tested design is improved.
The dynamic link library is used for simulating the operation process of the design to be tested and generating reference data. A dynamic link library is a module that contains functions and data that can be used by other modules (applications or DLLs). The dynamic link library contains functions that are called by an executable program or other DLL to accomplish a job, and may not run directly nor receive messages. The dynamically linked library typically contains two files, an import library file (.lib) and a dynamically linked library file (.dll). The leading-in library file contains symbol names of functions and variables contained in the dynamic link library, and the dynamic link library file contains actual functions and data of the dynamic link library. In the compiling and linking stage, only the links are needed to be led into the library file, the functions and data in the dynamic link library are not copied into the program, and the functions in the dynamic link library file are accessed in the running stage.
The dynamic link library can be generated by a NEMU and other software simulators, and in the verification process of the design to be tested, the data generated when the dynamic link library is called can be considered to be correct and used as reference data to be compared with the data generated by the design to be tested. It can be appreciated that the data that needs to be configured when generating the dynamic link library is different for different designs under test. In addition, when different software simulators are used for generating the dynamic link library, the data required to be configured are different.
In the verification process, each time the design to be tested executes an instruction, a first state value of the design to be tested is acquired, and a dynamic link library is called to execute the instruction and output a second state value. It will be appreciated that the instructions executed by the design under test and the dynamic link library may be instructions contained in a benchmark test program. The benchmark test program is used for testing the performance or correctness of the design under test. And the design to be tested and the dynamic link library respectively execute the same reference test program. In the embodiment of the invention, after each instruction is executed by the design to be tested, the operation of the design to be tested is interrupted, then the first state value of the design to be tested is collected, and the same number of instructions are waited for being executed by the dynamic link library. As one example, the number of instructions executed by the dynamically linked library may be controlled by an execute () function.
Because the reference test program executed by the design to be tested and the dynamic link library are the same, the instruction sequences executed by the design to be tested and the dynamic link library are the same, and under the condition that the design to be tested and the dynamic link library execute one instruction each time, the same instruction can be ensured to be executed by the design to be tested and the dynamic link library, so that the first state value and the second state value are ensured to be synchronous, inaccurate verification results caused by the fact that the first state value and the second state value are not synchronous are avoided, and the accuracy of the verification results is ensured.
The contents of the first state value and the second state value may be determined according to data to be verified in the design to be tested, for example, the first state value and the second state value may include a value of a general purpose register, a value of a control and status register, a value of a program counter, an instruction commit event, and the like. In practical application, specific contents of the first state value and the second state value can be specified according to practical situations and specific verification requirements.
Comparing the first state value of the design to be tested with the second state value generated by the dynamic link library, if the first state value is matched with the second state value, for example, the first state value is the same as the second state value, or the value of the first state value falls into the value range of the second state value, and the like, the design to be tested can be considered to have no error, at the moment, the design to be tested can be controlled to continuously execute the next instruction, the newly generated first state value of the design to be tested is collected, and the dynamic link library is called to continuously execute the next instruction, so that the new second state value is generated.
If the first state value does not match the second state value, for example, the first state value is not the same as the second state value, or the first state value does not fall within the range of values of the second state value, or the like, the design under test may be considered to be in error. Under the condition, the whole verification system can be snapshot, the state information of the programmable logic chip and the verification platform is saved, the saved data is imported into simulation software, and fine-grained debugging is carried out on the design to be tested by the simulation software.
According to the embodiment of the invention, the first state value and the second state value are compared once after each instruction is executed by the design to be tested and the dynamic link library, so that errors can be timely reported when the design to be tested is in error operation, and the verification effectiveness is ensured. In addition, in the embodiment of the invention, the error position of the design to be tested can be rapidly positioned according to the comparison result of the first state value and the second state value, and the fine granularity debugging and inspection of the design to be tested can be facilitated in time.
Furthermore, the embodiment of the invention burns the design to be tested on the FPGA chip to run, extracts data from the design to the verification platform to verify, and improves the verification efficiency compared with software simulation.
Optionally, the first state value and the second state value comprise values of a general purpose register, a control and state register, and a program counter; the comparing 105 the first state value with the second state value includes:
Step S11, comparing all data contained in the first state value and the second state value under the condition that a preset granularity interval is met;
And step S12, comparing the value of the general register in the first state value with the value of the general register in the second state value under the condition that the preset granularity interval is not met.
The preset granularity interval is used for indicating an interval for comprehensively comparing the first state value and the second state value. Illustratively, the preset granularity interval may be an entry (instruction number), for example, when the preset granularity interval is 1, indicating that a full comparison is made every time 1 instruction is executed; when the preset granularity interval is 10, it indicates that a full comparison is made every 10 instructions are executed.
In the embodiment of the present invention, if the preset granularity interval is currently satisfied, the comparison may be performed on all data included in the first state value and the second state value, which may specifically include: the values of all general purpose registers (General Purpose Registers, GPR), control and status registers (Control and Status Register, CSR), and Program Counter (PC). Taking a RISC-V processor as an example, the full comparison may be performed on 32 GPR registers, 18 CSR registers, and PC values. If the preset granularity interval is not currently met, only the values of the general purpose registers may be compared.
As an example, assuming a preset granularity interval of 10, a full comparison is made for each 10 instructions executed by the design under test and the dynamic link library; if the distance is fully compared last time, the number of instructions executed by the design to be tested and the dynamic link library is less than 10, and then a partial comparison is performed. For example, after the design under test and the dynamic link library respectively execute the 1 st instruction, only the values of the general registers in the first state value and the second state value are compared. And after the design to be tested and the dynamic link library respectively execute the 10 th instruction, comparing all contents in the first state value and the second state value. After the design to be tested and the dynamic link library execute the 11 th instruction respectively, only the values of the general registers in the first state value and the second state value are compared. And so on until the design to be tested runs wrong or the program is executed.
Further, when the first state value is not matched with the second state value, determining that the design to be tested runs wrong, generating error reporting information, and reporting the number and the name of a register with errors in the design to be tested, and the current first state value and the second state value to a tester or simulation software so as to debug the design to be tested.
In an alternative embodiment of the present invention, the programmable logic chip shares the same memory module with the verification platform; before comparing the first state value with the second state value, the method further comprises:
s21, packaging the first state value by taking the instruction as granularity; each data packet comprises a group of first state values corresponding to the design to be tested after executing an instruction;
step S22, the data packet is sent to the storage module;
the comparing 105 the first state value with the second state value includes:
Step S23, reading the data packet from the storage module, and updating a first structure body according to a first state value in the data packet;
step S24, synchronously updating the second state value output by the dynamic link library into a second structure body according to the data packet;
And S25, comparing the first state value recorded in the first structure with the second state value recorded in the second structure.
In the verification system provided by the embodiment of the invention, the FPGA chip and the verification platform share the same storage module, and the FPGA chip can write the acquired first state value of the design to be tested into the storage module for the verification platform to acquire the first state value from the storage module and compare with the second state value generated by the dynamic link library.
Specifically, after the first state value of the design to be tested is collected, the first state value can be packaged with the instruction as granularity, that is, a group of first state values after the design to be tested executes an instruction is placed in a data packet. And the FPGA chip sends the packed data packet to the storage module. When the verification platform verifies the to-be-tested design, the data packet is read from the storage module, and the first structural body is updated according to a first state value in the data packet. The initial value of the first structure may be a default value, and after the verification platform reads the first state value, the value of the first structure may be updated to the first state value. And simultaneously, the verification platform synchronously updates a second state value generated by the dynamic link library into a second structural body. It can be understood that in the embodiment of the present invention, after each instruction is executed by the design to be tested and the dynamic link library, the first state value and the second state value are compared once, and the updating of the first structure body and the updating of the second structure body are synchronous, that is, the first state value recorded in the first structure body and the second state value recorded in the second structure body correspond to the same instruction, so that the accuracy of the verification result is ensured.
Optionally, the packaging the first state value with the instruction as granularity includes:
Step S31, after the design to be tested executes an instruction, interrupting the operation of the design to be tested, and collecting a first state value of the design to be tested;
And S32, packaging the acquired first state value, sending a data packet to the storage module, and recovering the operation of the design to be tested so that the design to be tested can continuously execute the next instruction.
In the embodiment of the invention, after the design to be tested finishes executing an instruction and collecting the first state value, the operation of the design to be tested is interrupted, the collected first state value is packed, and after the data packet is transmitted to the storage module, the operation of the design to be tested is recovered, so that the design to be tested continues to execute the next instruction.
For example, the data packets may be stored in the storage module in order of instruction execution, or the time stamp corresponding to each data packet may be recorded. The verification platform reads the data packets from the storage module according to the sequence of instruction execution, calls the dynamic link library to execute an instruction when one data packet is read, and compares the first state value in the data packet with the second state value generated by the dynamic link library.
Optionally, the programmable logic chip further comprises an interrupt control module; the method further comprises the steps of:
Step S41, setting the value of the first signal to be a first preset value under the condition that the storage module is full; the first preset value is used for indicating the interrupt control module to interrupt the operation of the design to be tested and the transmission of the data packet;
Step S42, setting the value of the first signal to be a second preset value under the condition that the last data packet in the storage module is read; the second preset value is used for indicating the interrupt control module to resume the operation of the design to be tested and the transmission of the data packet.
In the embodiment of the invention, an interrupt control module is also arranged in the FPGA chip and is used for controlling the operation of the design to be tested. Specifically, the verification platform may set the value of the first signal to a first preset value when the storage module is full. And the interrupt control module interrupts the operation of the design to be tested and the transmission of the data packet under the condition that the value of the first signal is monitored to be a first preset value.
When the verification platform reads the last data packet in the storage module, the verification platform sets the value of the first signal to a second preset value to instruct the interrupt control module to resume the operation of the design to be tested and the transmission of the data packet.
The interrupt control module is used for continuously reading the first signal after interrupting the operation of the design to be tested and the transmission of the data packet, and continuing to interrupt if the value of the first signal is still a first preset value; if the value of the first signal is the second preset value, the operation of the design to be tested and the transmission of the data packet can be restored. The FPGA chip packages the newly generated first state value of the design to be tested and sends the first state value to the storage module, and the new data packet can cover the old data packet in the storage module.
In addition, in the embodiment of the invention, the verification platform determines that the first state value of the design to be tested is not matched with the second state value generated by the dynamic link library, and can set the value of the first signal as the first preset value, instruct the interrupt control module to interrupt the operation of the design to be tested and the transmission of the data packet, wait for the test personnel to debug and recover the design to be tested, and continue the operation of the design to be tested and the transmission of the data packet after the debugging is finished.
Optionally, the method further comprises:
step S51, under the condition that a target event occurs in the design to be tested, acquiring a third state value of the design to be tested after the design to be tested executes the target event; the target event comprises an event which cannot be simulated by the dynamic link library;
step S52, determining that the design to be tested runs normally when the third state value meets a preset condition;
step S53, determining that the design to be tested is in error when the third state value does not meet the preset condition.
It should be noted that, the target event in the embodiment of the present invention refers to an event that cannot be simulated by the dynamic link library, for example ARCH EVENT, TRAP EVENT, and so on. If the target event occurs in the design to be tested, whether the design to be tested runs wrong can be judged according to whether the third state value after the design to be tested completes the execution of the target event meets the preset condition. If the third state value meets the preset condition, the design to be tested can be considered to run normally; otherwise, if the third state value does not meet the preset condition, the design to be tested can be considered to be in error.
Illustratively, when ARCH EVENT and TRAP EVENT occur in the design under test, the value of EVENTVALID, TRAPVALID in the data packet is 1, and the verification platform determines whether ARCH EVENT and TRAP EVENT occur in the design under test according to the value of EVENTVALID, TRAPVALID after parsing the data packet.
ARCH EVENT can be categorized into interrupt (interrupt) and exception (exception). For interrupts, whether to update a mode (mode) value and a PC value corresponding to a dynamic link library may be determined according to the type of the interrupt and the values of an interrupt delegate register (mideleg) and an exception delegate register (medeleg), and specifically may include the following steps:
1. It is determined whether the bitwise and operation result of the inter Numbers (NO) and 1ULL < <63 are non-zero. If the operation result is non-zero, storing a mideleg value in a second structure corresponding to the dynamic link library in a deleg variable; otherwise, the value of medeleg is stored in the deleg variable.
NO &0xf is then used to preserve the lower four bits of the anomaly number. Then (1 < < (NO &0 xf)) deleg, if the corresponding bit in deleg is 1, the result will be a non-zero value, otherwise the result will be 0. It is then checked whether the result is 0, i.e. whether the corresponding bit is set. If the corresponding bit is set, the result will be true, otherwise false.
Checking whether the MODE of the dynamic link library is smaller than MODE_M, if so, the result is true, otherwise, false.
Finally, the two obtained result phases are subjected to result assignment to delegs.
The code is as follows: word_ t deleg = (exceptionNO & INTR_BIT mideleg- > val: medeleg- > val);
bool delegS = ((deleg&(1<<(exceptionNO&0xf))) != 0)&&(cpu.mode<MODE_M);
return delegS
2. If delegs is true, the value scause is assigned NO, sepc is assigned the PC value at interrupt, while mstatus- > spp is assigned the mode value of cpu, mstatus- > spie is assigned mstatus- > si. mstatus- > si is assigned a value of 0 and the value of stval- > val is set to 0 (here the values of htval and stval according to the value of NO and the different updates of the design under test can be written, since the different designs under test are different values).
3. Cpu=mode_s, i.e., the MODE of the CPU is set to the Supervisor MODE, and then the state of the memory management unit (Memory Management Unit, MMU) is updated.
And finally, returning the address of the exception handler, namely the corresponding PC value, and updating the PC value in the second structural body corresponding to the dynamic link library into the returned PC value.
After the updating operation is carried out, comparing the first structural body corresponding to the design to be tested with the second structural body corresponding to the dynamic link library, and if the values of the first structural body and the second structural body are matched, indicating that the design to be tested is normal in operation; and if the design to be tested is not matched, indicating that the design to be tested is in error operation.
For exceptions, the third state Value of the design under test may include the values of mtval (MACHINE TRAP Value) and stval (Supervisor Trap Value Register) registers. Wherein mtval holds the attachment information of the trap (trap), for example: the value of mtval is 0 for other exceptions, such as access to address information at the time of address error, the instruction itself at the time of execution of an illegal instruction, and the like. stval registers are used to store other information related to the trap. In the embodiment of the invention, if an exception occurs in the design to be tested, the values of mtval and stval of the design to be tested can be updated into the first structure body and the second structure body, and the dynamic link library is controlled to execute an instruction backwards.
For TRAP EVENT, after TRAP EVENT occurs in the design under test, if trapvalid in the data packet is true, it represents that the program is running to end, after the verification platform updates the data of the first structure and the second structure at this time, trapcode is checked according to trapvalid before executing the command, if trapcode is 0, i.e. state_ GOODTRAP, it represents that the program is ending to exit, and if other values, it represents that the program is executing an error in the design under test.
Referring to fig. 2, a schematic structural diagram of a verification system according to an embodiment of the present invention is shown. As shown in fig. 2, the verification system includes an FPGA chip and a verification platform. The FPGA chip comprises a design to be tested, a data packaging module, a data transmission module and an interrupt control module. The verification platform comprises a storage module, a dynamic link library, a data updating module and a checker. The data packaging module is used for collecting and packaging a first state value of the design to be tested. The data transmission module is used for transmitting the data packet to the storage module. The interrupt control module is used for controlling the operation of the design to be tested and the data transmission process of the data transmission module. The data updating module is used for reading the data packet from the storage module and updating the first structural body corresponding to the design to be tested. The checker is used for comparing the first structural body with the second structural body corresponding to the dynamic link library so as to check whether the design to be tested runs wrong or not.
The verification method provided by the embodiment of the present invention is illustrated in the following with reference to the verification system shown in fig. 2.
In the embodiment of the invention, each time the design to be tested executes an instruction, the data packaging module acquires a group of first state values and packages the first state values, and one data packet corresponds to one instruction. At this time, the interrupt control module interrupts the operation of the design to be tested until the data transmission module sends the data packet to the storage module, and then the interrupt control module resumes the operation of the design to be tested, so that the next instruction is continuously executed.
The data updating module of the verification platform reads the data packet from the storage module according to the instruction execution sequence and analyzes the data packet, and updates the first state value in the data packet into the first structure body. And the verification platform can call the dynamic link library to execute an instruction and update the second state value generated by the dynamic link library into the second structural body. Then, the checker compares the data recorded in the first structural body and the second structural body, if the two structural bodies are not matched, the running error of the design to be tested is indicated, and in this case, the whole verification system can be subjected to snapshot storage so as to debug the design to be tested. And if the two are matched, the design to be tested is normally operated.
In summary, the embodiment of the invention provides a verification method, which comprises the steps of modifying a chip code of a to-be-tested design to access data transmitted by each data interface of the to-be-tested design to a top layer module of the to-be-tested design, and then burning the to-be-tested design to a programmable logic area of a programmable logic chip according to the modified chip code, and generating a dynamic link library in a verification platform. After each instruction is executed by the design to be tested, a first state value of the design to be tested is collected, the dynamic link library is called, the dynamic link library is controlled to execute one instruction and output a second state value, if the first state value is matched with the second state value, the design to be tested is controlled to continue to execute the next instruction, and the dynamic link library is continuously called; and if the first state value is not matched with the second state value, determining that the design to be tested runs wrong. Compared with the traditional FPGA prototype verification method, the method and the device have the advantages that the chip codes of the to-be-tested design are modified, the data transmitted by each data interface of the to-be-tested design are accessed to the top layer module of the to-be-tested design, the to-be-tested design is burnt to the PL area of the FPGA chip according to the modified chip codes, the acquisition and analysis of intermediate data and state values generated in the running process of the to-be-tested design are facilitated, and the detail visibility of the to-be-tested design is improved. In addition, the embodiment of the invention compares the first state value with the second state value once after each instruction is executed by the design to be tested and the dynamic link library, can report errors in time when the design to be tested runs wrong, ensures the validity of verification, can rapidly position the wrong position of the design to be tested according to the comparison result of the first state value and the second state value, and is favorable for debugging and checking the fine granularity of the design to be tested in time.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Device embodiment
Referring to fig. 3, there is shown a block diagram of a verification device of the present invention, the system may specifically include:
The code modification module 301 is configured to modify a chip code of a to-be-designed, so as to access data transmitted by each data interface of the to-be-designed to a top module of the to-be-designed;
The burning module 302 is configured to burn the design to be tested into a programmable logic area of a programmable logic chip according to the modified chip code;
a generating module 303, configured to generate a dynamic link library in the verification platform; the dynamic link library is used for simulating the operation process of the design to be tested and generating reference data;
The state value obtaining module 304 is configured to collect a first state value of the to-be-tested design after each instruction is executed by the to-be-tested design, and call the dynamic link library to control the dynamic link library to execute one instruction and output a second state value;
A comparison module 305, configured to compare the first state value with the second state value;
The control module 306 is configured to control the design to be tested to continue to execute a next instruction and to continue to call the dynamic link library if the first state value matches the second state value;
A first determining module 307, configured to determine that the design under test operates in error if the first state value does not match the second state value.
Optionally, the first state value and the second state value comprise values of a general purpose register, a control and state register, and a program counter; the comparison module comprises:
The first comparison sub-module is used for comparing all data contained in the first state value and the second state value under the condition that a preset granularity interval is met;
And the second comparison sub-module is used for comparing the value of the general register in the first state value with the value of the general register in the second state value under the condition that the preset granularity interval is not met.
Optionally, the programmable logic chip and the verification platform share the same memory module; the apparatus further comprises:
the packing module is used for packing the first state value by taking the instruction as granularity; each data packet comprises a group of first state values corresponding to the design to be tested after executing an instruction;
the transmission module is used for sending the data packet to the storage module;
the comparison module comprises:
the first updating sub-module is used for reading the data packet from the storage module and updating the first structure body according to a first state value in the data packet;
the second updating sub-module is used for synchronously updating the second state value output by the dynamic link library into a second structure body according to the data packet;
And the third comparison sub-module is used for comparing the first state value recorded in the first structure body with the second state value recorded in the second structure body.
Optionally, the packaging module includes:
The interrupt submodule is used for interrupting the operation of the design to be tested after the design to be tested executes an instruction and collecting a first state value of the design to be tested;
and the packing sub-module is used for packing the acquired first state value, sending the data packet to the storage module, and recovering the operation of the design to be tested so as to enable the design to be tested to continuously execute the next instruction.
Optionally, the programmable logic chip further comprises an interrupt control module; the apparatus further comprises:
The first setting module is used for setting the value of the first signal to be a first preset value under the condition that the storage module is full; the first preset value is used for indicating the interrupt control module to interrupt the operation of the design to be tested and the transmission of the data packet;
The second setting module is used for setting the value of the first signal to a second preset value under the condition that the last data packet in the storage module is read; the second preset value is used for indicating the interrupt control module to resume the operation of the design to be tested and the transmission of the data packet.
Optionally, the apparatus further comprises:
The acquisition module is used for acquiring a third state value of the design to be tested after executing the target event under the condition that the target event occurs in the design to be tested; the target event comprises an event which cannot be simulated by the dynamic link library;
the second determining module is used for determining that the design to be tested runs normally under the condition that the third state value meets the preset condition;
and the third determining module is used for determining that the design to be tested runs wrong under the condition that the third state value does not meet the preset condition.
In summary, an embodiment of the present invention provides a verification device, which may modify a chip code of a to-be-tested design, access data transmitted by each data interface of the to-be-tested design to a top module of the to-be-tested design, and then burn the to-be-tested design into a programmable logic area of a programmable logic chip according to the modified chip code, and generate a dynamic link library in the verification platform. After each instruction is executed by the design to be tested, a first state value of the design to be tested is collected, the dynamic link library is called, the dynamic link library is controlled to execute one instruction and output a second state value, if the first state value is matched with the second state value, the design to be tested is controlled to continue to execute the next instruction, and the dynamic link library is continuously called; and if the first state value is not matched with the second state value, determining that the design to be tested runs wrong. Compared with the traditional FPGA prototype verification method, the method and the device have the advantages that the chip codes of the to-be-tested design are modified, the data transmitted by each data interface of the to-be-tested design are accessed to the top layer module of the to-be-tested design, the to-be-tested design is burnt to the PL area of the FPGA chip according to the modified chip codes, the acquisition and analysis of intermediate data and state values generated in the running process of the to-be-tested design are facilitated, and the detail visibility of the to-be-tested design is improved. In addition, the embodiment of the invention compares the first state value with the second state value once after each instruction is executed by the design to be tested and the dynamic link library, can report errors in time when the design to be tested runs wrong, ensures the validity of verification, can rapidly position the wrong position of the design to be tested according to the comparison result of the first state value and the second state value, and is favorable for debugging and checking the fine granularity of the design to be tested in time.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform the operations in relation to the processor of the above-described embodiments have been described in detail in relation to the embodiments of the method and will not be described in detail herein.
Referring to fig. 4, a block diagram of an electronic device for authentication according to an embodiment of the present invention is provided. As shown in fig. 4, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions that cause the processor to perform the authentication method of the foregoing embodiment.
The Processor may be a CPU (Central Processing Unit ), general purpose Processor, DSP (DIGITAL SIGNAL Processor ), ASIC (Application SPECIFIC INTEGRATED Circuit), FPGA (Field Programmable GATE ARRAY ) or other editable device, transistor logic device, hardware component, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.
The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (PERIPHERAL COMPONENT INTERCONNECT, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.
The Memory may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory ) or other type of dynamic storage device that can store information and instructions, an EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY ), a CD-ROM (Compact Disc Read Only Memory, compact disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Embodiments of the present invention also provide a non-transitory computer-readable storage medium that, when executed by a processor of an electronic device (server or terminal), enables the processor to perform the authentication method shown in fig. 1.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems) and computer program products according to embodiments of the invention. It will be understood that each flowchart and/or block of the flowchart illustrations and/or block diagrams, and combinations of flowcharts and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The foregoing has described in detail a verification method, apparatus, electronic device and readable storage medium according to the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. The verification method is characterized by being applied to a verification system, wherein the verification system comprises a programmable logic chip and a verification platform; the method comprises the following steps:
modifying a chip code of a to-be-tested design so as to access data transmitted by each data interface of the to-be-tested design to a top layer module of the to-be-tested design;
burning the design to be tested into a programmable logic area of a programmable logic chip according to the modified chip code;
Generating a dynamic link library in the verification platform; the dynamic link library is used for simulating the operation process of the design to be tested and generating reference data;
After each instruction is executed by the design to be tested, collecting a first state value of the design to be tested, and calling the dynamic link library to control the dynamic link library to execute the instruction and output a second state value;
Comparing the first state value with the second state value;
Under the condition that the first state value is matched with the second state value, controlling the design to be tested to continuously execute the next instruction, and continuously calling the dynamic link library;
and under the condition that the first state value is not matched with the second state value, determining that the design to be tested runs wrong.
2. The method of claim 1, wherein the first state value and the second state value comprise values of general purpose registers, control and state registers, and program counters; the comparing the first state value with the second state value includes:
comparing all data contained in the first state value and the second state value under the condition that a preset granularity interval is met;
And under the condition that the preset granularity interval is not met, comparing the value of the general register in the first state value with the value of the general register in the second state value.
3. The method of claim 1, wherein the programmable logic chip shares the same memory module with the verification platform; before comparing the first state value with the second state value, the method further comprises:
Packaging the first state value by taking an instruction as granularity; each data packet comprises a group of first state values corresponding to the design to be tested after executing an instruction;
transmitting the data packet to the storage module;
the comparing the first state value with the second state value includes:
reading the data packet from the storage module, and updating a first structure body according to a first state value in the data packet;
synchronously updating the second state value output by the dynamic link library into a second structure body according to the data packet;
and comparing the first state value recorded in the first structure body with the second state value recorded in the second structure body.
4. The method of claim 3, wherein said packing said first state value at instruction granularity comprises:
after the design to be tested executes an instruction, interrupting the operation of the design to be tested, and collecting a first state value of the design to be tested;
And packaging the acquired first state value, sending a data packet to the storage module, and recovering the operation of the design to be tested so that the design to be tested can continuously execute the next instruction.
5. The method of claim 3, further comprising an interrupt control module in the programmable logic chip; the method further comprises the steps of:
setting the value of the first signal to be a first preset value under the condition that the storage module is full; the first preset value is used for indicating the interrupt control module to interrupt the operation of the design to be tested and the transmission of the data packet;
Setting the value of the first signal to a second preset value under the condition that the last data packet in the storage module is read; the second preset value is used for indicating the interrupt control module to resume the operation of the design to be tested and the transmission of the data packet.
6. The method according to claim 1, wherein the method further comprises:
Under the condition that a target event occurs in the design to be tested, acquiring a third state value of the design to be tested after the design to be tested executes the target event; the target event comprises an event which cannot be simulated by the dynamic link library;
under the condition that the third state value meets the preset condition, determining that the design to be tested runs normally;
and under the condition that the third state value does not meet the preset condition, determining that the design to be tested runs wrong.
7. The verification device is characterized by being applied to a verification system, wherein the verification system comprises a programmable logic chip and a verification platform; the device comprises:
The code modification module is used for modifying the chip code of the to-be-designed so as to access the data transmitted by each data interface of the to-be-designed into the top layer module of the to-be-designed;
the programming module is used for programming the design to be tested to a programmable logic area of a programmable logic chip according to the modified chip code;
the generation module is used for generating a dynamic link library in the verification platform; the dynamic link library is used for simulating the operation process of the design to be tested and generating reference data;
the state value acquisition module is used for acquiring a first state value of the design to be tested after each instruction is executed by the design to be tested, and calling the dynamic link library to control the dynamic link library to execute one instruction and output a second state value;
The comparison module is used for comparing the first state value with the second state value;
The control module is used for controlling the design to be tested to continuously execute the next instruction and continuously call the dynamic link library under the condition that the first state value is matched with the second state value;
And the first determining module is used for determining that the design to be tested runs wrong under the condition that the first state value is not matched with the second state value.
8. The apparatus of claim 7, wherein the first state value and the second state value comprise values of general purpose registers, values of control and status registers, and values of program counters; the comparison module comprises:
The first comparison sub-module is used for comparing all data contained in the first state value and the second state value under the condition that a preset granularity interval is met;
And the second comparison sub-module is used for comparing the value of the general register in the first state value with the value of the general register in the second state value under the condition that the preset granularity interval is not met.
9. An electronic device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is configured to store executable instructions that cause the processor to perform the authentication method of any one of claims 1 to 6.
10. A readable storage medium, characterized in that instructions in the readable storage medium, when executed by a processor of an electronic device, enable the processor to perform the authentication method of any one of claims 1 to 6.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826050A (en) * | 2010-02-03 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Random verification method and device for verifying processor chip after manufacturing |
| CN116306413A (en) * | 2023-04-28 | 2023-06-23 | 绿盟科技集团股份有限公司 | FPGA simulation verification method and device, electronic equipment and storage medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160032529A (en) * | 2014-09-16 | 2016-03-24 | 삼성전자주식회사 | SYSTEM ON CHIP(SoC), AND DYNAMIC VOLTAGE FREQUENCY SCALING(DVFS) VERIFICATION METHOD THEREOF |
| US10546081B2 (en) * | 2017-09-20 | 2020-01-28 | Mentor Graphics Corporation | Full memory logical erase for circuit verification |
| CN116302721A (en) * | 2021-12-20 | 2023-06-23 | 瑞昱半导体股份有限公司 | Chip design verification system and method and computer readable recording medium |
| WO2024025863A1 (en) * | 2022-07-25 | 2024-02-01 | Strong Force TX Portfolio 2018, LLC | Systems and methods for providing process automation and artificial intelligence, market aggregation, and embedded marketplaces for a transactions platform |
| CN117094269B (en) * | 2023-10-17 | 2024-02-02 | 北京开源芯片研究院 | Verification method, verification device, electronic equipment and readable storage medium |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826050A (en) * | 2010-02-03 | 2010-09-08 | 北京龙芯中科技术服务中心有限公司 | Random verification method and device for verifying processor chip after manufacturing |
| CN116306413A (en) * | 2023-04-28 | 2023-06-23 | 绿盟科技集团股份有限公司 | FPGA simulation verification method and device, electronic equipment and storage medium |
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