CN118132469B - Tester communication system, communication method and tester - Google Patents
Tester communication system, communication method and tester Download PDFInfo
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- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The application relates to a tester communication system, a communication method and a tester, wherein the tester communication system comprises an upper computer and a communication board card, and the communication board card comprises a DMA operation module, a PIO operation module and an interrupt module; the PIO operation module caches the register data packets, and controls the interrupt module to send out a first interrupt request command when the number of the register read commands configured by the upper computer is the same as the number of the register data packets; when the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the DMA operation module writes the register data packets into the memory of the upper computer and controls the interrupt module to send out a second interrupt request command; the upper computer responds to the first interrupt request command and initiates a PIO read command; the PIO operation module analyzes the PIO read command and writes the register data packet into the upper computer; or the upper computer responds to the second interrupt request command and reads out the register data packet from the memory of the upper computer. The batch register data reading operation is completed by one interruption, and the communication efficiency is improved.
Description
Technical Field
The present application relates to the field of semiconductor testing technologies, and in particular, to a communication system, a communication method, and a testing machine for a testing machine.
Background
The automatic semiconductor test refers to that various parameter indexes of a tested device (Device Under Test, DUT) are detected by automatic test equipment (Automatic Test Equipment, ATE) and defective products are removed to control the factory quality of the semiconductor device. In practical application, the upper computer can continuously perform data interaction with the data board of the testing machine to read the data of the register. When a certain register needs to be read, the upper computer directly initiates a read command, after the communication board card receives the response data of the resource board card once, an interrupt command needs to be initiated to the upper computer once, and the upper computer initiates the next read command again, so that the time delay is long, and the defect of low communication efficiency exists.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a tester communication system, a communication method, and a tester that can improve communication efficiency.
The first aspect of the application provides a communication system of a testing machine, which comprises an upper computer and a communication board card, wherein the communication board card comprises a DMA operation module, a PIO operation module and an interrupt module; the interrupt module is respectively connected with the DMA operation module, the PIO operation module and the upper computer, and the upper computer is connected with the DMA operation module and the PIO operation module;
The PIO operation module caches the register data packets, and controls the interrupt module to send out a first interrupt request command when the number of the register read commands configured by the upper computer is the same as the number of the register data packets; the register data packet is obtained by responding N register read request commands issued synchronously by the upper computer by each resource board card, reading the register values of each resource board card and packing;
When the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the DMA operation module writes the register data packets into the upper computer memory and controls the interrupt module to send out a second interrupt request command;
The upper computer responds to the first interrupt request command and initiates a PIO read command; the PIO operation module analyzes the PIO read command and writes the register data packet into the upper computer; or the upper computer responds to the second interrupt request command and reads out the register data packet from the upper computer memory.
In one embodiment, the communication board further includes: and the arbitration module is connected with the PIO operation module, the DMA operation module and the resource board cards, caches the N register data packets and arbitrates the N register data packets to the PIO operation module or the DMA operation module.
In one embodiment, the upper computer is internally provided with a driver;
the driver responds to N register read request commands issued by the upper computer and judges whether the total data amount of N register data packets to be read exceeds a preset data amount;
If the total data amount is greater than or equal to the preset data amount, the driving configuration enabling signal is used for controlling the arbitration module to arbitrate the register data packet to the DMA operation module;
And if the total data amount is smaller than the preset data amount, the drive control arbitration module arbitrates the register data packet to the PIO operation module.
In one embodiment, the communication board further includes:
And the Aurora IP core is connected with the arbitration module through an AXI interface, and is also connected with each resource board card through optical fibers, and the register data packet of each resource board card is uploaded to the arbitration module.
In one embodiment, the communication board further includes:
And the PCIE IP core is connected with the driver of the upper computer through a PCIE bus, is also connected with the PIO operation module, the DMA operation module and the interrupt module, and is used for issuing N register read request commands, uploading the first interrupt request command or the second interrupt request command and issuing the PIO read command.
In one embodiment, the upper computer is further configured to, after obtaining the register data packet, sort, splice and combine the register data packet according to the sending sequence of the register read request command, obtain a sorted data packet, remove a data header of the sorted data packet, and output the sorted data packet to a user API function.
A second aspect of the present application provides a test machine communication method, including:
The PIO operation module caches the register data packets, and controls the interrupt module to send out a first interrupt request command when the number of the register read commands configured by the upper computer is the same as the number of the register data packets; the register data packet is obtained by responding N register read request commands issued synchronously by the upper computer by each resource board card, reading the register values of each resource board card and packing;
When the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the DMA operation module writes the register data packets into the upper computer memory and controls the interrupt module to send out a second interrupt request command;
The upper computer responds to the first interrupt request command and initiates a PIO read command, and the PIO operation module analyzes the PIO read command and writes the register data packet into the upper computer; or, the upper computer responds to the second interrupt request command and reads the register data packet from the upper computer memory.
In one embodiment, the method further comprises:
the driver responds to N register read request commands issued by the upper computer, and judges whether the total data amount of N register data packets to be read exceeds a preset data amount;
If the total data amount is greater than or equal to the preset data amount, the driving configuration enabling signal is used for controlling the arbitration module to arbitrate the register data packet to the DMA operation module;
and if the total data amount is smaller than the preset data amount, the drive control arbitration module arbitrates the register data packet to the PIO operation module.
A third aspect of the present application provides a testing machine comprising a testing machine communication system as described above.
In one embodiment, the testing machine further comprises a plurality of resource boards, and each resource board is connected with the communication system; and each resource board reads the value of the corresponding register according to the register read request command issued by the upper computer and packs the value to obtain a register data packet, and the register data packet is sent to the communication system.
According to the testing machine communication system, the communication method and the testing machine, after the resource boards respond to N register read request commands synchronously issued by the upper computer, the values of the registers of the resource boards are read and packed to obtain the register data packets, the register data packets are cached through the PIO operation module of the testing machine communication system, and when the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the interrupt module is controlled to send out a first interrupt request command, or when the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the register data packets are written into the memory of the upper computer by the DMA operation module, and the interrupt module is controlled to send out a second interrupt request command. The upper computer responds to the first interrupt request command to initiate a PIO read command, the PIO operation module analyzes the PIO read command, and writes the register data packet into the upper computer, or the upper computer responds to the second interrupt request command to read the register data packet from the memory of the upper computer. The method can support the host computer to carry out batch register data reading operation on the resource board card, and carry out interrupt request in a corresponding mode through the PIO operation module or the DMA operation module, so that batch register data reading operation is completed through one interrupt, interrupt response time is saved, read data delay is reduced, and communication efficiency is improved.
Drawings
FIG. 1 is a block diagram of a tester communication system in one embodiment;
FIG. 2 is a block diagram of another embodiment of a tester communication system;
FIG. 3 is a flow chart of a method of tester communication in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In one embodiment, as shown in fig. 1, there is provided a tester communication system, including a host computer 100 and a communication board 200, the communication board 200 including a PIO (programmable input output) operation module 210, a DMA (direct memory access) operation module 220, and an interrupt module 230; the interrupt module 230 is connected to the DMA operation module 220, the PIO operation module 210, and the host computer 100, respectively, and the host computer 100 is connected to the DMA operation module 220 and the PIO operation module 210.
The upper computer 100 may be various personal computers, notebook computers, smartphones, tablet computers, and portable wearable devices, and the portable wearable devices may be smart watches, smart bracelets, headsets, etc., and the communication board 200 may specifically be an FPGA (Field-Programmable gate array) or the like. The PIO operation module 210 caches the register data packets, and controls the interrupt module 230 to issue a first interrupt request command when the number of register read commands configured by the host computer 100 is the same as the number of register data packets. The register data packet is obtained by reading and packing the values of the registers 400 of each resource board 300 in response to N register read request commands issued synchronously by the upper computer 100, and the value of N is not unique and can be set according to actual needs. When the number of the register read commands configured by the upper computer 100 is the same as the number of the register data packets, the DMA operation module 220 writes the register data packets into the memory of the upper computer 100, and controls the interrupt module 230 to issue a second interrupt request command. The upper computer 100 responds to the first interrupt request command and initiates a PIO read command; the PIO operation module 210 parses the PIO read command and writes the register packet into the host 100; or the host computer 100 responds to the second interrupt request command to read the register data packet from the memory of the host computer 100.
One register read command reads a corresponding register, one register can buffer M data volumes, and M data volumes in one register are combined into a register data packet, wherein the total data volume of N register data packets to be read is M times N data volumes.
Specifically, the plurality of resource boards 300 are all connected to the communication board 200, and each resource board 300 is connected to a corresponding register 400. The specific value of the number of the register read commands is not unique and can be selected according to actual needs. The number of register read commands is configured to the PIO operation module 210 and the DMA operation module 220 by the upper computer 110, thereby adjusting interrupt trigger conditions of the PIO operation module 210 and the DMA operation module 220. The N register read request commands issued synchronously by the upper computer 110 may be resource boards 300 issued to corresponding slots through the communication board 200. The resource board 300 parses the received register read request command, reads the value of the corresponding register 400, packages the value to obtain a register data packet, and returns the register data packet to the communication board 200. Wherein N is an integer, and N is not less than 1.
The PIO operation module 210/DMA operation module 220 in the communication board 200 detects the number of the received register data packets, and when the number of the received register data packets reaches the number of the configured register read commands, the PIO operation module 210/DMA operation module 220 sends out a corresponding interrupt request command to the upper computer 100 through the interrupt module 230. When the batch register data is read, the communication board 200 only needs to perform one interrupt operation, namely, a first interrupt request command or a second interrupt request command is sent once, so that interrupt response time is saved, read data delay is reduced, and communication efficiency is improved.
The PIO operation module 210 reads a plurality of register data packets, and when the amount of each read register data packet is small, the efficiency can be improved well, and when the amount of each read register data packet is large, the DMA operation module 220 reads a plurality of register data packets, and the purpose of improving the efficiency can be achieved. It can be understood that, in actual use, according to the actual register data amount, the PIO operation module 210 or the DMA operation module 220 is set by the upper computer 100 to perform data reading, so that batch register data reading can be completed by one interrupt operation, interrupt response time can be achieved, and communication efficiency can be improved.
In one embodiment, as shown in fig. 2, the communication board 200 further includes an arbitration module 240, where the arbitration module 240 connects the PIO operation module 210, the DMA operation module 220, and each resource board 300, caches N register data packets, and arbitrates to the PIO operation module 210 or the DMA operation module 220. The arbitration module 240 may specifically connect the PIO operation module 210 and the DMA operation module 220 through an AXI (Advanced eXtensible Interface ) interface, and after the arbitration module 240 receives the register data packet returned by each resource board 300 and stores the register data packet in the internal buffer, the arbitration module may perform alternative arbitration on the register data packet in the buffer according to the sequence of the requests of the resource board 300, and send the register data packet to the buffer in the PIO operation module 210 or the buffer in the DMA operation module 220. After the number of the register data packets stored in the local buffer reaches the number of the configured register read commands, the PIO operation module 210 or the DMA operation module 220 sends out a corresponding interrupt request command to the upper computer 100 through the interrupt module 230. The buffer may be a FIFO (First Input First Output, first-in first-out queue) unit, or may be another type of buffer.
Further, the upper computer 100 is provided with a driver, and the driver responds to the N register read request commands issued by the upper computer 100 to determine whether the total data amount of N register data packets to be read exceeds a preset data amount; if the total data amount of the N register data packets to be read is greater than or equal to the preset data amount, driving the configuration enable signal to control the arbitration module 240 to arbitrate the N register data packets to the DMA operation module 220; if the total data amount of the N register data packets to be read is smaller than the preset data amount, the driving control arbitration module 240 arbitrates the N register data packets to the PIO operation module 210.
The specific value of the preset data amount is not unique, and can be set according to actual needs. The host computer 100 may estimate in advance the total amount of data of the register data packet to be read according to the number of register read request commands and the type of data to be read. If the total data amount of the N register data packets to be read is greater than or equal to the preset data amount, the arbitration module 240 arbitrates the N register data packets to the buffer in the DMA operation module 220; if the total data amount of the N register data packets to be read is smaller than the preset data amount, the driving control arbitration module 240 of the upper computer 100 arbitrates the register data packets to the buffer in the PIO operation module 210. When the number of N register data packets in the local buffer reaches the number of configured register read commands, the PIO operation module 210 sends a first interrupt request command to the upper computer 100 through the control interrupt module 230, analyzes the PIO read command returned by the upper computer 100, reads out the N register data packets in the local buffer, and sequentially sends the N register data packets to the upper computer 100. When the number of the register data packets in the local buffer reaches the configured number of the register read commands, the DMA operation module 220 writes N register data packets into the memory of the host computer 100, and sends a second interrupt request command to the host computer 100 through the interrupt module 230 to notify the host computer 100 to read the register data packets from the memory.
Further, the communication board 200 further includes an Aurora IP core 250, where the Aurora IP core 250 is connected to the arbitration module 240 through an AXI interface, and further connected to each resource board 300 through an optical fiber, and uploads a register data packet corresponding to each resource board 300 to the arbitration module 240. After each resource board 300 receives the corresponding register read request command, the values of the registers are read and packed to obtain register data packets corresponding to each resource board, the N register data packets are sequentially sent to the Aurora IP core 250 through the optical fiber, and the Aurora IP core 250 stores the N register data packets into the buffer of the arbitration module 240 through the AXI interface.
In addition, the communication board 200 may further include a PCIE IP core 260, where the PCIE IP core 260 is connected to a driver of the host computer 100 through a PCIE bus, and is further connected to the PIO operation module 210, the DMA operation module 220, and the interrupt module 230, issues N register read request commands, uploads a first interrupt request command or a second interrupt request command, and is further used to issue a PIO read command. The PCIE IP core 260 receives N register read request commands issued by the host computer 100, and forwards the N register read request commands to the corresponding resource board 300. When the number of the configured register read commands is the same as the number of the register data packets in the local buffer, the PIO operation module 210 controls the interrupt module 230 to output a first interrupt request command, and the first interrupt request command is uploaded from the host 100 through the PCIE IP core 260. The PIO read command issued by the upper computer 100 is transmitted to the PIO operation module 210 through the PCIE IP core 260, and after the PIO operation module 210 parses the PIO read command, N register data packets are written into the upper computer through the PCIE IP core 260. Or when the number of the configured register read commands is the same as the number of the register data packets in the local buffer, the DMA operation module 220 writes N register data packets into the upper computer memory through the PCIE IP core 260, and controls the interrupt module 230 to output a second interrupt request command, where the second interrupt request command is uploaded to the upper computer 100 through the PCIE IP core 260, so that the upper computer 100 responds to the second interrupt request command and reads the register data packets from the upper computer memory.
In one embodiment, the upper computer 100 is further configured to, after acquiring N register data packets, sort, splice and combine the register data packets according to a sending sequence of a register read request command, obtain a sorted data packet, remove a data header of the sorted data packet, and output the sorted data packet to a user API (user application program interface) function.
Specifically, since the respective resource boards 300 are independent of each other, the order of the N register packets received by the communication board 200 is different from the order of the packets actually to be requested. The host computer 100 may record the transmission order of the register read request command when transmitting the register read request command. After the upper computer 100 receives the register data packets returned by the corresponding N register read request commands, it can know, according to the information carried by the register data packets, which register read request command corresponds to the response data of each register data packet, and the upper computer 100 performs one-to-one correspondence with the sequence of sending the register read request commands, so as to know the ordering sequence of the register data packets. After the host computer 100 sorts the register data packets, the data header of each data packet is taken out, the remaining bare data is the register data, and the register data is output to the user API function so as to perform the next data analysis processing.
In one embodiment, as shown in fig. 3, there is also provided a test machine communication method, including:
Step S110: the PIO operation module caches the register data packets, and controls the interrupt module to send out a first interrupt request command when the number of the register read commands configured by the upper computer is the same as the number of the register data packets; the register data packet is obtained by responding N register read request commands issued synchronously by the upper computer by each resource board card, reading the register values of each resource board card and grouping.
Step S120: and when the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the DMA operation module writes the register data packets into the memory of the upper computer and controls the interrupt module to send out a second interrupt request command.
Step S130: the upper computer responds to the first interrupt request command and initiates a PIO read command, and the PIO operation module analyzes the PIO read command and writes a register data packet into the upper computer; or, the upper computer responds to the second interrupt request command and reads out the register data packet from the memory of the upper computer.
It should be noted that, in step S110 and step S130, "the upper computer responds to the first interrupt request command and initiates the PIO read command, the PIO operation module parses the PIO read command, and writes the register data packet into the upper computer" is an uplink transmission process; in step S120 and step S130, "the host computer reads the register packet from the host computer memory in response to the second interrupt request command" is another uplink transmission procedure. Wherein N is an integer, and N is not less than 1.
In one embodiment, the method further comprises: the arbitration module caches the N register data packets and arbitrates the N register data packets to the PIO operation module or the DMA operation module.
In one embodiment, a driver is arranged in the upper computer; the method further comprises the steps of: the drive responds to N register read request commands issued by the upper computer, and judges whether the total data amount of N register data packets to be read exceeds a preset data amount; if the total data amount is greater than or equal to the preset data amount, driving a configuration enabling signal to control an arbitration module to arbitrate the register data packet to a DMA operation module; if the total data amount is smaller than the preset data amount, the drive control arbitration module arbitrates the register data packet to the PIO operation module.
In one embodiment, the method further comprises: the Aurora IP core receives the register data packet of each resource board through the optical fiber and uploads the register data packet to the arbitration module through the AXI interface.
In one embodiment, the method further comprises: the upper computer synchronously transmits N register read request commands to each resource board card.
It can be appreciated that the specific implementation manner of the communication method of the testing machine is explained in detail in the communication system of the testing machine, and will not be described in detail herein.
In one embodiment, a testing machine is also provided, including the testing machine communication system described above. Further, the testing machine also comprises a plurality of resource boards, and each resource board is connected with the communication system; and each resource board reads the value of the corresponding register according to the register read request command issued by the upper computer, and packs the value to obtain a register data packet, and sends the register data packet to the communication system.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. The communication system of the tester is characterized by comprising an upper computer and a communication board card, wherein the communication board card comprises a DMA operation module, a PIO operation module and an interrupt module; the interrupt module is respectively connected with the DMA operation module, the PIO operation module and the upper computer, and the upper computer is connected with the DMA operation module and the PIO operation module;
The PIO operation module caches the register data packets, and controls the interrupt module to send out a first interrupt request command when the number of the register read commands configured by the upper computer is the same as the number of the register data packets; the register data packet is obtained by responding N register read request commands issued synchronously by the upper computer by each resource board card, reading the register values of each resource board card and packing;
When the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the DMA operation module writes the register data packets into the upper computer memory and controls the interrupt module to send out a second interrupt request command;
the upper computer responds to the first interrupt request command and initiates a PIO read command; the PIO operation module analyzes the PIO read command and writes the register data packet into the upper computer; or the upper computer responds to the second interrupt request command and reads the register data packet from the upper computer memory;
the communication board card further includes: and the arbitration module is connected with the PIO operation module, the DMA operation module and each resource board card, and after storing N register data packets into an internal buffer, the arbitration module performs alternative arbitration on the register data packets in the buffer according to the sequence of the resource board card requests and arbitrates the register data packets to the PIO operation module or the DMA operation module.
2. The tester communication system of claim 1 wherein the arbitration module arbitrates the register packets to a buffer in the PIO operation module or a buffer in the DMA operation module.
3. The tester communication system according to claim 2, wherein the host computer has a driver therein;
the driver responds to N register read request commands issued by the upper computer and judges whether the total data amount of N register data packets to be read exceeds a preset data amount;
If the total data amount is greater than or equal to the preset data amount, the driving configuration enabling signal is used for controlling the arbitration module to arbitrate the register data packet to the DMA operation module;
And if the total data amount is smaller than the preset data amount, the drive control arbitration module arbitrates the register data packet to the PIO operation module.
4. The tester communication system of claim 2 wherein the communication board further comprises:
And the Aurora IP core is connected with the arbitration module through an AXI interface, and is also connected with each resource board card through optical fibers, and the register data packet of each resource board card is uploaded to the arbitration module.
5. The tester communication system of claim 2 wherein the communication board further comprises:
And the PCIE IP core is connected with the driver of the upper computer through a PCIE bus, is also connected with the PIO operation module, the DMA operation module and the interrupt module, and is used for issuing N register read request commands, uploading the first interrupt request command or the second interrupt request command and issuing the PIO read command.
6. The communication system of any one of claims 1 to 5, wherein the upper computer is further configured to, after obtaining the register data packet, perform sorting, splicing and combining on the register data packet according to the sending sequence of the register read request command, obtain a sorted data packet, remove a header of the sorted data packet, and output the sorted data packet to a user API function.
7. A method of tester communication, comprising:
after the arbitration module stores N register data packets into an internal buffer, performing alternative arbitration on the register data packets in the buffer according to the sequence of the resource board requests, and arbitrating to the PIO operation module or the DMA operation module;
The PIO operation module caches the register data packets, and controls the interrupt module to send out a first interrupt request command when the number of the register read commands configured by the upper computer is the same as the number of the register data packets; the register data packet is obtained by responding N register read request commands issued synchronously by the upper computer by each resource board card, reading the register values of each resource board card and packing;
When the number of the register read commands configured by the upper computer is the same as the number of the register data packets, the DMA operation module writes the register data packets into the upper computer memory and controls the interrupt module to send out a second interrupt request command;
The upper computer responds to the first interrupt request command and initiates a PIO read command, and the PIO operation module analyzes the PIO read command and writes the register data packet into the upper computer; or, the upper computer responds to the second interrupt request command and reads the register data packet from the upper computer memory.
8. The method as recited in claim 7, further comprising:
the driver responds to N register read request commands issued by the upper computer, and judges whether the total data amount of N register data packets to be read exceeds a preset data amount;
If the total data amount is greater than or equal to the preset data amount, the driving configuration enabling signal is used for controlling the arbitration module to arbitrate the register data packet to the DMA operation module;
and if the total data amount is smaller than the preset data amount, the drive control arbitration module arbitrates the register data packet to the PIO operation module.
9. A test machine comprising a test machine communication system as claimed in any one of claims 1 to 6.
10. The tester of claim 9 further comprising a plurality of resource boards, each resource board being connected to the communication system; and each resource board reads the value of the corresponding register according to the register read request command issued by the upper computer and packs the value to obtain a register data packet, and the register data packet is sent to the communication system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| US5822568A (en) * | 1996-05-20 | 1998-10-13 | Advanced Micro Devices, Inc. | System for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller |
| US5794072A (en) * | 1996-05-23 | 1998-08-11 | Vlsi Technology, Inc. | Timing method and apparatus for interleaving PIO and DMA data transfers |
| CN103077140B (en) * | 2013-02-05 | 2015-08-05 | 北京配天技术有限公司 | The communication means of a kind of Motion Control Board and host computer and communicator |
| CN106951388B (en) * | 2017-03-16 | 2020-06-30 | 湖南博匠信息科技有限公司 | PCIe-based DMA data transmission method and system |
| CN114443529B (en) * | 2022-04-02 | 2022-07-05 | 苏州浪潮智能科技有限公司 | Direct memory access architecture, system, method, electronic device and medium |
| CN117591300B (en) * | 2024-01-17 | 2024-05-17 | 杭州长川科技股份有限公司 | Multi-thread communication method and device for testing machine and testing machine |
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| 基于PCIe的多路传输系统的DMA控制器设计;李胜蓝等;计算机应用;20170310;第37卷(第3期);摘要、第2、3章 * |
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