CN118112397A - Circuit architecture for testing integrated circuit and integrated circuit testing method - Google Patents
Circuit architecture for testing integrated circuit and integrated circuit testing method Download PDFInfo
- Publication number
- CN118112397A CN118112397A CN202410533603.1A CN202410533603A CN118112397A CN 118112397 A CN118112397 A CN 118112397A CN 202410533603 A CN202410533603 A CN 202410533603A CN 118112397 A CN118112397 A CN 118112397A
- Authority
- CN
- China
- Prior art keywords
- switch
- chip
- capacitor
- tested
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 134
- 239000003990 capacitor Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000002093 peripheral effect Effects 0.000 claims abstract description 10
- 238000011990 functional testing Methods 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007488 abnormal function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 inductors Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/20—Modifications of basic electric elements for use in electric measuring instruments; Structural combinations of such elements with such instruments
- G01R1/206—Switches for connection of measuring instruments or electric motors to measuring loads
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
- G01R15/04—Voltage dividers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present application relates to the field of integrated circuit testing technology, and in particular, to a circuit architecture for testing an integrated circuit and an integrated circuit testing method, where the circuit architecture includes: a first switch, a capacitor and a second switch; the first end of the first switch is an input end of the circuit architecture, and the input end is electrically connected with the chip to be tested and the tester; the second end of the first switch is electrically connected with the positive electrode end of the capacitor, and the negative electrode end of the capacitor is electrically connected with the first grounding end; the positive terminal of the capacitor is also connected with the first terminal of the second switch, and the second terminal of the second switch is electrically connected with the second grounding terminal. The circuit architecture for testing the integrated circuit provided by the application is characterized in that the corresponding circuit is conducted in a way that the first switch and the second switch are conducted, so that no other peripheral devices are arranged between the tester and the chip to be tested in the testing process, the charge and discharge time of the waiting capacitor is reduced, the testing period of the integrated circuit is shortened, and the testing efficiency of the integrated circuit is further improved.
Description
Technical Field
The present invention relates to the field of integrated circuit testing technology, and in particular, to a circuit architecture for testing an integrated circuit and an integrated circuit testing method.
Background
Currently, when testing integrated circuits, it is common to place the integrated circuits on the power pins or LDs of the chip. The output pin is connected with the electrolytic capacitor to serve as a bypass capacitor so as to improve the stability of voltage. When the open-short circuit test is carried out, the tester sends a test current to the chip to be tested, and whether the test result is qualified is determined by measuring the current or the voltage received by pins on the chip to be tested.
However, since the chip is externally connected with the electrolytic capacitor, the electrolytic capacitor is charged after the tester sends out a current or a standby instruction, and a certain delay is needed to obtain a test result, so that the test period is long and the test efficiency is not ideal.
Disclosure of Invention
The present invention provides a circuit architecture for testing an integrated circuit and an integrated circuit testing method.
In a first aspect, embodiments of the present invention provide a circuit architecture for testing an integrated circuit, the circuit architecture comprising: a first switch, a capacitor and a second switch;
the first end of the first switch is an input end of the circuit architecture, and the input end is electrically connected with the chip to be tested and the tester;
The second end of the first switch is electrically connected with the positive electrode end of the capacitor, and the negative electrode end of the capacitor is electrically connected with the first grounding end;
The positive electrode end of the capacitor is also connected with the first end of the second switch, and the second end of the second switch is electrically connected with the second grounding end;
The first switch and the second switch are turned on.
In combination with the first aspect, when the first switch is opened and the second switch is closed, the testing machine sends a testing current to the chip to be tested, and an open-short circuit testing circuit between the chip to be tested and the testing machine is formed.
In combination with the first aspect, when the first switch is closed and the second switch is opened, the chip to be tested, the first switch and the capacitor are communicated to form a functional test circuit.
In combination with the first aspect, when the first switch is opened and the second switch is closed, the testing machine sends a standby instruction to the chip to be tested to form a standby testing circuit between the chip to be tested and the testing machine.
In combination with the first aspect, the tester is provided with a plurality of points, the chip to be tested is provided with a plurality of pins, and the plurality of points are electrically connected with the plurality of pins in a one-to-one correspondence manner.
In combination with the first aspect, the testing machine, the first switch and the second switch are respectively electrically connected with the relay control board.
In a second aspect, the present application provides an integrated circuit testing method, applied to the above circuit architecture for testing an integrated circuit, the method comprising:
opening the first switch, and closing the second switch to electrically connect the tester with pins of the chip to be tested and block the isolated peripheral capacitor;
Controlling the tester to send test current to the chip to be tested;
and determining the current voltage of the pin as an open-short circuit test result.
With reference to the second aspect, the test current was 100uA.
With reference to the second aspect, after the step of determining the current voltage of the pin as the open-short test result, the method further includes:
Closing the first switch, opening the second switch, and conducting the connection lines of the chip, the capacitor and the first grounding end to charge the capacitor;
aiming at each function of the chip, carrying out functional test on the chip by a tester to obtain a test result corresponding to the function;
And determining the functional test result of the chip to be tested based on all the test results.
With reference to the second aspect, after the step of determining the functional test result of the chip based on all the test results, the method further includes:
closing the second switch, opening the first switch, and conducting the connection lines of the capacitor, the second switch and the second grounding end so as to discharge the capacitor;
The control testing machine sends a standby instruction to the chip to be tested;
And determining the current of the chip to be tested as the standby current of the chip to be tested.
The embodiment of the application has the following beneficial effects: the application provides a circuit architecture for testing an integrated circuit and an integrated circuit testing method, wherein the circuit architecture comprises a first end of a first switch which is an input end of the circuit architecture, and the input end is electrically connected with a chip to be tested and a tester; the second end of the first switch is electrically connected with the positive electrode end of the capacitor, and the negative electrode end of the capacitor is electrically connected with the second grounding end; the positive electrode end of the capacitor is also connected with the first end of the second switch, and the second end of the second switch is electrically connected with the second grounding end; the first switch and the second switch are turned on.
The circuit architecture for testing the integrated circuit provided by the application is characterized in that the corresponding circuit is conducted in a way that the first switch and the second switch are conducted, so that no other peripheral devices are arranged between the tester and the chip to be tested in the testing process, the charge and discharge time of the waiting capacitor is reduced, the testing period of the integrated circuit is shortened, and the testing efficiency of the integrated circuit is further improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a circuit architecture for testing an integrated circuit according to an embodiment of the present invention;
fig. 2 is a flowchart of an integrated circuit testing method according to an embodiment of the present invention.
Reference numerals:
1-first switch, 2-electric capacity, 3-second switch, 4-chip to be tested, 5-test machine, 6-first ground, 7-second ground.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to facilitate understanding of the present embodiment, technical terms designed by the present application will be briefly described below.
An integrated circuit (INTEGRATED CIRCUIT) is a microelectronic device or component, which is fabricated by interconnecting the required transistors, resistors, capacitors, inductors, and other components and wiring in a circuit together using a process on a small or several small semiconductor die or dielectric substrate, and then packaged in a package to form a microstructure having the required circuit functions.
The chip refers to a silicon chip containing an integrated circuit, has a small volume, and is commonly used as a part of a computer or other electronic equipment.
After technical terms related to the application are introduced, application scenes and design ideas of the embodiment of the application are briefly introduced.
In the existing integrated circuit testing method, a capacitor is externally connected with a chip, and in the open-short circuit testing and standby current testing processes, the capacitor is charged and then the pin voltage of the chip is tested, so that the time delay exists in the testing process, and the testing efficiency is required to be improved.
The embodiment of the application provides a circuit architecture for testing an integrated circuit and an integrated circuit testing method.
Example 1
The present application provides a circuit architecture for testing an integrated circuit, as shown in connection with fig. 1, the circuit architecture comprising: a first switch 1, a capacitor 2 and a second switch 3.
The first end of the first switch 1 is an input end of a circuit architecture, and the input end is electrically connected with the chip 4 to be tested and the testing machine 5;
the second end of the first switch 1 is electrically connected with the positive electrode end of the capacitor 2, and the negative electrode end of the capacitor 2 is electrically connected with the first grounding end 6;
The positive electrode end of the capacitor 2 is also connected with the first end of the second switch 3, and the second end of the second switch 3 is electrically connected with the second grounding end 7;
wherein the first switch 1 and the second switch 3 are turned on.
By conducting the first switch 1 and the second switch 3, when the integrated circuit on the chip 4 to be tested is subjected to open-short circuit test and standby test, the chip 4 to be tested and the testing machine 5 are not externally connected with the capacitor 2, and the time for the testing machine 5 to obtain the pin voltage and standby current is shortened, so that the testing period is shortened, and the testing efficiency of the integrated circuit is improved.
In combination with the first aspect, when the first switch 1 is opened and the second switch 3 is closed, the tester 5 sends a test current to the pin of the chip 4 to be tested, so as to form an open-short circuit test circuit between the chip 4 to be tested and the tester 5.
Under the condition that the first switch 1 is disconnected, the circuit among the chip 4 to be tested, the testing machine 5 and the capacitor 2 is blocked, and at the moment, only the circuit among the chip 4 to be tested and the testing machine 5 is connected; that is, the chip 4 to be tested and the tester 5 are not connected to the peripheral capacitor 2. At this time, the tester 5 sends a test current to the chip 4 to be tested, and determines whether the on-off state of the integrated circuit on the chip 4 to be tested is good by obtaining the pin voltage on the chip 4 to be tested. In this process, since the chip 4 to be tested and the tester 5 are not connected to the peripheral capacitor 2, the pin voltage on the chip 4 to be tested can be measured by the tester 5 within about 1 ms.
In this embodiment, the test current is 1000uA, and the measured pin voltage on the chip 4 to be tested is: -0.6V.
In combination with the first aspect, when the first switch 1 is closed and the second switch 3 is opened, the chip 4 to be tested, the first switch 1 and the capacitor 2 are communicated to form a functional test circuit.
When the first switch 1 is closed, the circuit connection between the chip to be tested 4 and the capacitor 2 is conducted, the chip to be tested 4 is also connected with the testing machine 5, and the circuit connection between the chip to be tested 4 and the second grounding terminal 7 is blocked because the second switch 3 is opened, so that a functional testing circuit is formed. The tester 5 tests instructions for the chip 4 to be tested to test specific modules of the integrated circuit on the chip 4 to be tested.
It can be understood that the integrated circuit may be formed by connecting a plurality of module circuits, and in order to test each module, a plurality of test instructions may be set, and the test machine 5 sequentially sends the test instructions to the chip 4 to be tested, so as to perform a functional test on the corresponding module in the integrated circuit.
Further, the tester 5 includes a memory, and a list is stored in the memory, and the list sequentially lists test instructions corresponding to each functional module, and the tester 5 sequentially sends the test instructions to the chip 4 to be tested according to the table sequence, so that the functional test of the corresponding module is realized.
In addition, the chip to be tested 4 is electrically connected with the capacitor 2, so that the capacitor 2 is charged to keep the voltage of the functional test circuit stable.
In combination with the first aspect, when the first switch 1 is opened and the second switch 3 is closed, the testing machine 5 sends a standby instruction to the chip to be tested 4, so as to form a standby testing circuit between the chip to be tested 4 and the testing machine 5.
After the capacitor 2 is charged or the capacitor 2 has a voltage, the first switch 1 is opened again and the second switch 3 is closed, so that the capacitor 2 is discharged. At this time, only the chip to be tested 4 is electrically connected to the testing machine 5, and the testing machine 5 sends a standby command to the chip to be tested 4 to make the chip to be tested enter the standby mode. At this time, since the chip 4 to be tested and the testing machine 5 have no external capacitor 2, compared with the case of external capacitor 2 in the prior art, the time for charging the capacitor 2 is saved, so that the testing machine 5 can measure the standby current of the chip 4 to be tested in a shorter time.
In combination with the first aspect, the tester 5 has a plurality of points, and the chip 4 to be tested has a plurality of pins, where the plurality of points are electrically connected to the plurality of pins in a one-to-one correspondence manner.
It can be understood that the pins of the chip 4 to be tested are electrically connected with the points of the tester 5 in a one-to-one correspondence manner, each pin corresponds to one module of the integrated circuit, and the test result of the corresponding module can be obtained by measuring the pin voltage.
In combination with the first aspect, the testing machine 5, the first switch 1 and the second switch 3 are electrically connected with the relay control board, respectively.
Like this, control test machine 5, first switch 1 and second switch 3 through the relay control panel to replace the manual work to close, break the switch and control test machine 5 to await measuring chip 4 send instruction, test current for integrated circuit test process is smooth, reduces manual intervention and manual work amount of labour.
In a second aspect, the present application provides an integrated circuit testing method applied to the circuit architecture for testing an integrated circuit as described above, and as shown in fig. 2, the method includes:
S110, the first switch is opened, and the second switch is closed, so that the tester is electrically connected with pins of the chip to be tested and blocks the isolated peripheral capacitor.
S120, the control tester sends test current to the chip to be tested.
S130, determining the current voltage of the pin as an open-short circuit test result.
With reference to the first aspect, the test current in step S120 is 100uA.
In this embodiment, the second switch 3 is turned on and the first switch 1 is turned off, so that the circuit connection between the chip 4 to be tested and the capacitor 2 is blocked, so that the chip 4 to be tested and the tester 5 do not have peripheral capacitors, after the tester 5 sends test current to the chip 4 to be tested, the capacitor 2 on the periphery does not need to be charged, one or more pin voltage values on the chip 4 to be tested can be measured in about 1ms, and the voltage values are determined as the open-short circuit test result of the module of the integrated circuit corresponding to the pin.
The pin voltage of the chip 4 to be tested measured in this embodiment is-0.6V.
With reference to the first aspect, after the step of determining the current voltage of the pin as the open-short test result in S130, the method further includes:
S140, closing the first switch, opening the second switch, and conducting the connection lines of the chip, the capacitor and the first grounding end to charge the capacitor;
s150, aiming at each function of the chip, performing functional test on the chip by a tester to obtain a test result corresponding to the function;
S160, determining the functional test result of the chip based on all the test results.
After the open-short circuit test is finished, the first switch 1 is closed, the second switch 3 is opened, at the moment, the circuit connection between the chip 4 to be tested and the peripheral capacitor 2 is conducted, and at the moment, the capacitor 2 is charged so as to keep the circuit voltage stable. At this time, the control tester 5 sends a test instruction to the chip 4 to be tested to perform a functional test on a certain module in the integrated circuit integrated in the chip 4 to be tested.
Since one or more modules are included in an integrated circuit, the test results should be in a one-to-one correspondence with the modules. When there are a plurality of modules in the integrated circuit, that is, there are a plurality of test results, the functional test results of the chip 4 to be tested are determined in combination with all the test results. That is, when any one of the test results is abnormal, the abnormal function of the chip 4 to be tested is characterized. At this time, according to the corresponding relation between the pins and the modules in the integrated circuit, which module is abnormal can be determined.
With reference to the second aspect, after the step of determining the functional test result of the chip based on all the test results in S160, the method further includes:
S170, closing the second switch, and opening the first switch to conduct the connection lines of the capacitor, the second switch and the second grounding end so as to discharge the capacitor.
S180, the control tester sends a standby instruction to the chip.
And S190, determining the current of the chip as the standby current of the chip.
After the chip 4 to be tested is subjected to functional test, the first switch 1 is opened again, the second switch 3 is closed, at this time, the circuit connection between the capacitor 2 and the second switch 3 and the circuit connection between the capacitor 2 and the second ground terminal 7 are conducted, so that the capacitor 2 can be discharged, and meanwhile, the chip 4 to be tested and the testing machine 5 are not connected with the peripheral capacitor 2.
The control tester 5 sends a standby instruction to the chip 4 to be tested so that the chip 4 to be tested enters a standby mode, and the tester 5 obtains the current after the chip 4 to be tested enters the standby mode and takes the current as the standby current of the chip to be tested.
Because the chip to be tested 4 and the testing machine 5 have no external capacitor 2 in the process, the testing machine 5 can measure the standby current of the chip to be tested 4 less than 1uA in a shorter time (such as 10 ms).
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood by those skilled in the art in specific cases.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention for illustrating the technical solution of the present invention, but not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the foregoing examples, it will be understood by those skilled in the art that the present invention is not limited thereto: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. A circuit architecture for testing an integrated circuit, the circuit architecture comprising: a first switch, a capacitor and a second switch;
the first end of the first switch is an input end of the circuit architecture, and the input end is electrically connected with the chip to be tested and the tester;
The second end of the first switch is electrically connected with the positive electrode end of the capacitor, and the negative electrode end of the capacitor is electrically connected with the first grounding end;
the positive electrode end of the capacitor is also connected with the first end of the second switch, and the second end of the second switch is electrically connected with the second grounding end;
The first switch and the second switch are conducted.
2. The circuit architecture of claim 1, wherein when the first switch is opened and the second switch is closed, the tester sends a test current to the chip under test, forming an open-short test circuit between the chip under test and the tester.
3. The circuit architecture of claim 1, wherein the chip under test, the first switch, and the capacitor are connected to form a functional test circuit when the first switch is closed and the second switch is open.
4. The circuit architecture of claim 1, wherein when the first switch is turned off and the second switch is turned on, the tester sends a standby instruction to the chip under test to form a standby test circuit between the chip under test and the tester.
5. The circuit architecture of claim 1, wherein the tester has a plurality of sites, the chip to be tested has a plurality of pins, and the sites are electrically connected to the pins in a one-to-one correspondence.
6. The circuit architecture of claim 1, wherein the tester, the first switch, and the second switch are each electrically connected to a relay control board.
7. An integrated circuit testing method applied to the circuit architecture for testing an integrated circuit according to any of claims 1-6, the method comprising:
opening the first switch, and closing the second switch to electrically connect the tester with pins of the chip to be tested and block the isolated peripheral capacitor;
controlling the tester to send test current to the chip to be tested;
And determining the current voltage of the pin as an open-short circuit test result.
8. The method of claim 7, wherein the test current is 100uA.
9. The method of claim 7, further comprising, after the step of determining the current voltage of the pin as an open-short test result:
closing the first switch, opening the second switch, and conducting the connection lines of the chip, the capacitor and the first grounding end to charge the capacitor;
aiming at each function of a chip, carrying out functional test on the chip by a tester to obtain a test result corresponding to the function;
And determining the functional test result of the chip to be tested based on all the test results.
10. The method of claim 7, further comprising, after the step of determining functional test results for the chip based on all of the test results:
Closing the second switch, opening the first switch, and conducting the connection lines of the capacitor, the second switch and the second grounding end so as to discharge the capacitor;
the control testing machine sends a standby instruction to the chip to be tested;
and determining the current of the chip to be tested as the standby current of the chip to be tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410533603.1A CN118112397A (en) | 2024-04-30 | 2024-04-30 | Circuit architecture for testing integrated circuit and integrated circuit testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410533603.1A CN118112397A (en) | 2024-04-30 | 2024-04-30 | Circuit architecture for testing integrated circuit and integrated circuit testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118112397A true CN118112397A (en) | 2024-05-31 |
Family
ID=91214008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410533603.1A Pending CN118112397A (en) | 2024-04-30 | 2024-04-30 | Circuit architecture for testing integrated circuit and integrated circuit testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118112397A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6383678A (en) * | 1986-09-29 | 1988-04-14 | Matsushita Electronics Corp | Testing method for integrated circuit element |
| JPH02213778A (en) * | 1989-02-15 | 1990-08-24 | Matsushita Electron Corp | Inspecting device for integrated circuit device |
| US6051968A (en) * | 1996-08-03 | 2000-04-18 | Samsung Electroincs Co., Ltd. | Test board provided with a capacitor charging circuit and related test method |
| CN103063975A (en) * | 2012-12-26 | 2013-04-24 | 成都市中州半导体科技有限公司 | Open circuit and short circuit testing system and method |
| CN117310450A (en) * | 2023-10-25 | 2023-12-29 | 合芯科技有限公司 | Power management chip test system |
-
2024
- 2024-04-30 CN CN202410533603.1A patent/CN118112397A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6383678A (en) * | 1986-09-29 | 1988-04-14 | Matsushita Electronics Corp | Testing method for integrated circuit element |
| JPH02213778A (en) * | 1989-02-15 | 1990-08-24 | Matsushita Electron Corp | Inspecting device for integrated circuit device |
| US6051968A (en) * | 1996-08-03 | 2000-04-18 | Samsung Electroincs Co., Ltd. | Test board provided with a capacitor charging circuit and related test method |
| CN103063975A (en) * | 2012-12-26 | 2013-04-24 | 成都市中州半导体科技有限公司 | Open circuit and short circuit testing system and method |
| CN117310450A (en) * | 2023-10-25 | 2023-12-29 | 合芯科技有限公司 | Power management chip test system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220146589A1 (en) | Method and device for predicting state of health and remaining lifetime for used electric vehicle batteries | |
| US8242749B2 (en) | Battery testing apparatus | |
| CN110736917A (en) | Short circuit test circuit, tester and method for negative electrode protection type lithium battery protection board | |
| CN118112397A (en) | Circuit architecture for testing integrated circuit and integrated circuit testing method | |
| CN115065125A (en) | Energy storage system | |
| KR100504925B1 (en) | apparatus and method for auto-checking battery protection circuit modules | |
| JP2008541687A (en) | Battery power management in overdischarged state | |
| CN109738746B (en) | Automobile electrical appliance grounding failure test system based on electronic control switch | |
| KR101580823B1 (en) | Method of reducing charge and discharge measurement time in rechargeable battery manufacturing process and apparatus thereof | |
| JP2018132487A (en) | Deterioration determination method of secondary battery and deterioration determination device of secondary battery | |
| CN117092477A (en) | High-temperature reverse bias aging test method for three-level power module | |
| CN212364535U (en) | Automatic discharging device and ATE (automatic test equipment) tester after power supply filter capacitor test is finished | |
| CN208477033U (en) | Alternating-current charging stake field test equipment | |
| CN219997263U (en) | Power module test fixture | |
| WO2021073723A1 (en) | Multiple batteries for optimized charging and cold use | |
| CN117406112B (en) | Battery self-discharge screening method | |
| CN218240102U (en) | Short circuit tool box is prevented to battery package finished product tester load end | |
| CN214150987U (en) | Battery cell aging cabinet | |
| CN117741410B (en) | High-power hybrid integrated circuit aging system | |
| CN219179488U (en) | High-voltage acquisition and insulation parameter detection device and insulation detection device | |
| CN117471224B (en) | Testing device for simulating hot plug of power battery | |
| CN117706392B (en) | Battery testing method, system, equipment and medium | |
| TWI818593B (en) | Discharge balancing method for battery equipment | |
| CN220752264U (en) | BMS battery protection board test equipment | |
| CN112751384B (en) | Electronic equipment control method and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: Room F1066, 1st Floor, Building 1 (South), No. 368 Liuhe Road, Puyan Street, Binjiang District, Hangzhou City, Zhejiang Province Applicant after: Hangzhou Xinyun Semiconductor Group Co.,Ltd. Address before: Room F1066, 1st Floor, Building 1 (South), No. 368 Liuhe Road, Puyan Street, Binjiang District, Hangzhou City, Zhejiang Province Applicant before: Hangzhou Xinyun Semiconductor Technology Co.,Ltd. Country or region before: China |
|
| CB02 | Change of applicant information |