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CN118101481B - Ethernet bandwidth expansion method, device and chip based on multi-core heterogeneous SOC - Google Patents

Ethernet bandwidth expansion method, device and chip based on multi-core heterogeneous SOC Download PDF

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Publication number
CN118101481B
CN118101481B CN202410525488.3A CN202410525488A CN118101481B CN 118101481 B CN118101481 B CN 118101481B CN 202410525488 A CN202410525488 A CN 202410525488A CN 118101481 B CN118101481 B CN 118101481B
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data frame
ethernet data
mtl
target
ethernet
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CN118101481A (en
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吴贤海
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Beijing Xinchi Semiconductor Technology Co ltd
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Beijing Xinchi Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/14—Multichannel or multilink protocols

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  • Theoretical Computer Science (AREA)
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Abstract

Ethernet bandwidth expansion method, device and chip based on multi-core heterogeneous SOC, wherein the method comprises the following steps: in response to receiving the first ethernet data frame, the MAC transmits the first ethernet data frame to a corresponding target MTL unit based on a target application domain core to which the first ethernet data frame is to be received; a DMA unit corresponding to the target MTL unit, and transferring the first Ethernet data frame from the target MTL unit to a target memory area of the shared memory of the multi-core heterogeneous SOC; the target memory area is a memory area which is configured in one-to-one correspondence with the target application domain core in the shared memory; the target application domain core reads the first ethernet data frame from the target memory region. Therefore, a plurality of systems which expand the bandwidth of the Ethernet to a plurality of domains of the multi-core heterogeneous SOC are realized, the network communication of the multi-system vehicle-mounted device can be simplified, the cost is saved, and the extra load of the CPU is effectively reduced through the function of a hardware end.

Description

Ethernet bandwidth expansion method, device and chip based on multi-core heterogeneous SOC
Technical Field
The application relates to the technical field of network data transmission, in particular to an Ethernet bandwidth expansion method, device and chip based on multi-core heterogeneous SOC.
Background
With the development of vehicle technology, the current vehicle system generally adopts schemes such as IVI (In-Vehicle Infotainment, in-vehicle infotainment system) central control instrument, intelligent driving, cabin and the like, and a plurality of systems such as Android, QNX, linux and the like need to be loaded. Because of the need for intelligent driving or AI (ARTIFICIAL INTELLIGENCE ) cabins, each system involved needs to communicate over a network.
In the related art, there are an ethernet device and a phy (physical transceiver) module for each system. The mode is high in cost, the equipment is a high-frequency device generally, a plurality of equipment share a power supply through a large number of wires on the same main board, high-frequency radiation is easy to cause mutual interference, and communication quality is affected.
Some of the network devices are not matched with Ethernet devices, but an Ethernet module and a virtual Ethernet card are adopted, and the network is realized through internal bus forwarding. Because the ethernet needs to be frequently applied and released, the load of the CPU (Central Processing Unit ) is greatly increased, and the ethernet bandwidth is affected.
Disclosure of Invention
In order to solve at least one problem in the prior art, the application aims to provide an Ethernet bandwidth expansion method, device and chip based on multi-core heterogeneous SOC, which can realize a plurality of systems for expanding the bandwidth of Ethernet to a plurality of domains of multi-core heterogeneous SOC by fully utilizing the advantages of multi-core heterogeneous architecture and combining specific Ethernet device multi-channel and shared memory configuration, thereby simplifying the network communication of a plurality of systems vehicle and machine, saving the cost, realizing the multi-channel forwarding of Ethernet data frames by a small system in a safe domain core through a hardware end function, effectively reducing the extra load of CPU and having high safety.
In order to achieve the above object, the present application provides an ethernet bandwidth extension method based on a multi-core heterogeneous SOC, where the multi-core heterogeneous SOC is configured with a security domain core and at least two application domain cores, and the security domain core is configured with an ethernet control device; the Ethernet control device is configured with a Media Access Controller (MAC), a Direct Memory Access (DMA) unit and at least two media access control layer (MTL) units which are configured in one-to-one correspondence with the at least two application domain cores; the method may include the steps of,
In response to receiving a first ethernet data frame, the MAC transmits the first ethernet data frame to a corresponding target MTL unit based on a target application domain core to which the first ethernet data frame is to be received;
A DMA unit corresponding to the target MTL unit, for transferring the first ethernet data frame from the target MTL unit to a target memory area of the shared memory of the multi-core heterogeneous SOC; the target memory area is a memory area which is configured in one-to-one correspondence with the target application domain core in the shared memory;
The target application domain core reads the first ethernet data frame from the target memory area.
Further, the step of the MAC transmitting the first ethernet data frame to a corresponding target MTL unit based on a target application domain core to which the first ethernet data frame is to be received, comprises,
The MAC identifies the destination address type of the first Ethernet data frame according to the target application domain core of the first Ethernet data frame;
In response to determining that the first ethernet data frame is a broadcast packet, the MAC determines each MTL unit in the ethernet control device as the target MTL unit;
and the MAC copies the Ethernet data frame and respectively sends the first Ethernet data frame to each MTL unit.
Still further, the method further comprises,
In response to determining that the first ethernet data frame is a multicast packet, the MAC determines at least two corresponding target MTL units according to an application domain core to which the first ethernet data frame is to be received;
And the MAC copies the Ethernet data frame and respectively sends the first Ethernet data frame to the at least two target MTL units.
Further, the method also comprises the steps of,
In response to determining that the first ethernet data frame is a unicast packet, the MAC determines a corresponding one of the target MTL units according to an application domain core to which the first ethernet data frame is to be received;
The MAC obtains a priority of the first ethernet data frame and routes the first ethernet data frame to the target MTL unit based on the priority.
Further, the method also comprises the steps of,
After the first ethernet data frame is transmitted to the target memory area of the shared memory, the security domain core triggers the target application domain core to interrupt, so that the target application domain core reads the first ethernet data frame from the target memory area.
Further, the method also comprises the steps of,
In response to receiving an Ethernet data sending instruction, the application domain core packages data to be sent, generates a second Ethernet data frame and transmits the second Ethernet data frame to a corresponding memory area in the shared memory;
the corresponding DMA unit conveys the second Ethernet data frame from the corresponding memory area to the corresponding MTL unit;
The corresponding MTL unit sends the second Ethernet data frame to the MAC so that the MAC can send the second Ethernet data frame out.
Still further, the step of the corresponding MTL unit transmitting the second ethernet data frame to the MAC includes,
And acquiring the priority of the second Ethernet data frame, and based on the priority, the corresponding DMA unit sends the second Ethernet data frame to the corresponding MTL unit.
Further, before transmitting the ethernet data frame, the method further comprises performing a pre-association configuration between the DMA unit and the MTL unit; wherein,
The number of the DMA units is the same as that of the MTL units in the Ethernet control device, and the DMA units are in one-to-one correspondence with the MTL units in the Ethernet control device; or alternatively, the first and second heat exchangers may be,
And the DMA unit is dynamically bound and configured with an MTL unit in the Ethernet control device.
In order to achieve the above object, the present application further provides an ethernet control device based on a multi-core heterogeneous SOC configured with a security domain core and at least two application domain cores; the ethernet control device is configured in the security domain core, the device comprising,
A Media Access Controller (MAC), in response to receiving a first Ethernet data frame, transmitting the first Ethernet data frame to a corresponding target MTL unit based on a target application domain core to be received;
the at least two media access control layer (MTL) units are configured in one-to-one correspondence with the at least two application domain cores and are used for correspondingly receiving the first Ethernet data frame sent by the MAC;
A direct memory access DMA unit, configured to be corresponding to an MTL unit in the ethernet control device, and configured to carry the first ethernet data frame from the target MTL unit to a target memory area of a shared memory of the multi-core heterogeneous SOC, so that the target application domain core reads the first ethernet data frame from the target memory area; the target memory area is a memory area which is configured in the shared memory in one-to-one correspondence with the target application domain core.
In order to achieve the above object, the present application further provides a chip, which is a multi-core heterogeneous SOC configured with a security domain core and at least two application domain cores; the security domain core is configured with an ethernet control device as described above.
According to the Ethernet bandwidth expansion method, the Ethernet bandwidth expansion device and the Ethernet bandwidth expansion chip based on the multi-core heterogeneous SOC, a first Ethernet data frame is received through MAC in response to the first Ethernet data frame, and the first Ethernet data frame is transmitted to a corresponding target MTL unit based on a target application domain core to be received; and the first Ethernet data frame is carried from the target MTL unit to a target memory area of the shared memory of the multi-core heterogeneous SOC through a DMA unit corresponding to the target MTL unit; and reading the first Ethernet data frame from the target memory area through the target application domain core. Therefore, the advantages of the multi-core heterogeneous architecture can be fully utilized, the bandwidth of the Ethernet is expanded to a plurality of systems of a plurality of domains of the multi-core heterogeneous SOC by combining the multi-channel and shared memory configuration of a specific Ethernet device, the network communication of a multi-system vehicle can be simplified, the cost is saved, and the multi-channel forwarding of the Ethernet data frame is realized by a small system in a safety domain core through a hardware end function, so that the extra load of the CPU is effectively reduced, and the safety is high.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and do not limit the application. In the drawings:
FIG. 1 is a block diagram of a multi-core heterogeneous SOC according to an embodiment of the application;
FIG. 2 is a flow chart of a method of Ethernet bandwidth expansion based on multi-core heterogeneous SOC according to an embodiment of the present application;
FIG. 3 is a flow chart of a method of Ethernet bandwidth extension based on multi-core heterogeneous SOC according to another embodiment of the present application;
Fig. 4 is a schematic diagram of an encapsulation structure of an ethernet data frame according to an embodiment of the present application;
FIG. 5 is a block diagram of a multi-core heterogeneous SOC according to another embodiment of the application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, units, or data and not for limiting the order or interdependence of the functions performed by such devices, modules, units, or data.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Firstly, it should be noted that the method for expanding the ethernet bandwidth provided by the embodiment of the present application is applied to a multi-core heterogeneous SOC (System On Chip). As shown in fig. 1, the multi-core heterogeneous SOC 100 is configured with a security domain core 110 and at least two application domain cores 120.
Wherein the application domain core 120 is configured with an application system. The security domain core 110 is configured with an ethernet control device 130. The ethernet control device 130 is configured with a media access Controller MAC (MEDIA ACCESS Controller) 131, a direct memory access DMA (Direct Memory Access) unit 133, and at least two media access control layer MTL units 132 configured in one-to-one correspondence with the at least two application domain cores 120.
In a particular example, multicore heterogeneous SOC 100 is configured with N application domain cores 120 (N.gtoreq.2), with each application domain core 120 configured with one application system. The ethernet control device 130 is configured with N MTL units 132, and is configured in one-to-one correspondence with the N application domain cores 120.
In addition, the multi-core heterogeneous SOC 100 is further configured to a shared memory 140, which may be specifically a DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory) or other types of applicable memories, which is not limited in this aspect of the present application. The shared memory 140 is defined with N shared memory areas 141 corresponding to the N application domain cores 120 one by one, for data transmission of the application domain cores 120.
In a specific example, the MAC 131 is configured to send and receive data to and from an external Phy device or Switch, and preferably, GMAC (Gigabit MEDIA ACCESS Controller ) is used. The MTL unit 132 is configured with a FIFO Controller (First Input First Output Controller, first-in first-out Controller) for buffering ethernet data frames. The DMA unit 133 is configured to transfer data between the corresponding associated MTL unit 132 and the shared memory area of the corresponding associated application domain core.
In the embodiment of the application, before the ethernet data frame is transmitted, the method further comprises pre-association configuration between the DMA unit and the MTL unit.
Specifically, as an example, the number of the DMA units is the same as that of the MTL units in the ethernet control device, and the DMA units are configured in a one-to-one correspondence static binding manner, so that the development complexity is reduced, and the development convenience is improved.
As another example, the DMA unit is configured dynamically bound to the MTL unit in the ethernet control device to accommodate complex functional requirements.
It should be further noted that, the heterogeneous SOC includes a plurality of hardware resources, where the hardware resources include computing type hardware resources, for example, CPU core, GPU core, etc., storage type hardware resources, such as memory, etc., control type hardware resources, such as power supply controller, clock controller, interrupt controller, etc., and communication type hardware resources, such as bus, etc. The plurality of hardware resources are configured as a plurality of hardware sets, each hardware set configured to run a different operating system, each hardware set not responsive to data access requests of other hardware sets, nor to scheduling of other operating systems other than the operating system configured on the present hardware set. The system chip is also provided with hardware resources supporting communication between different hardware sets, namely an inter-core communication channel, wherein the hardware resources are configured to support data transmission or reading requests of hardware in the different hardware sets so as to support establishment of data communication links between different operating systems, realize data transmission across the hardware resources and information communication across the operating systems.
Fig. 2 is a flowchart of an ethernet bandwidth extension method based on a multi-core heterogeneous SOC according to an embodiment of the present application, and the ethernet bandwidth extension method based on a multi-core heterogeneous SOC of the present application will be described in detail with reference to fig. 2.
In response to receiving the first ethernet data frame, the MAC transmits the first ethernet data frame to the corresponding target MTL unit based on the target application domain core to which the first ethernet data frame is to be received, step 201.
That is, after the MAC of the ethernet control device receives the first ethernet data frame, the MAC determines a target application domain core to receive the data frame according to the target address of the data frame, and then transmits the data frame to a target MTL unit corresponding to the target application domain core.
It should be noted that, the first ethernet data frame herein refers to an ethernet data frame received by the multi-core heterogeneous SOC, so as to distinguish a second ethernet data frame to be sent out by the multi-core heterogeneous SOC.
In an embodiment of the present application, as shown in fig. 3, step 201 includes the following sub-steps:
in step 2011, the mac identifies a destination address type of the first ethernet data frame according to the destination application domain core of the first ethernet data frame.
Specifically, the MAC of the ethernet control device may be configured with a packet filter to identify that the destination address type of the first ethernet data frame is a unicast packet (unicasting packet), a multicast packet (multicasting packet), or a broadcast packet (broadcasting packet).
In response to determining that the first ethernet data frame is a broadcast packet, the MAC determines each MTL unit in the ethernet control device as a target MTL unit, step 2012.
In step 2013, the mac copies the ethernet data frame and sends the first ethernet data frame to each MTL unit, respectively.
Further, step 201 may further comprise the sub-steps of:
In step 2014, in response to determining that the first ethernet data frame is a multicast packet, the MAC determines at least two corresponding target MTL units according to an application domain core to which the first ethernet data frame is to be received.
In step 2015, the mac copies the ethernet data frame and sends the first ethernet data frame to at least two target MTL units, respectively.
In an embodiment of the present application, step 201 may further include the following sub-steps:
In response to determining that the first ethernet data frame is a unicast packet, the MAC determines a corresponding one of the target MTL units according to the application domain core from which the first ethernet data frame is to be received, step 2016.
In step 2017, the mac obtains the priority of the first ethernet data frame and routes the first ethernet data frame to the target MTL unit based on the priority.
Specifically, the MAC of the ethernet control device may be further configured with a priority filter for unicast packet transmission to route the unicast packet to the target MTL unit corresponding to the priority based on the priority of the unicast packet.
In a specific example, as shown in fig. 4, the ethernet data frame is encapsulated to include: destination address (Destination address), source address (Source address), VLAN Tag (VLAN Tag), length/Type (Length/Type), data (Data), and frame tail (FCS). Wherein the VLAN tag may comprise: a Tag Protocol Identifier (TPID), a Priority (PRI), a standard format indicator bit (CFI), and a VLAN number (VID). The MAC may determine the priority of the first ethernet data frame from the VLAN tag of the first ethernet data frame based on the priority tag.
That is, after the MAC of the ethernet control device receives the first ethernet data frame, filtering is performed according to the destination address type of the data frame. If the first Ethernet data frame is a broadcast packet, the MAC copies the data and sends the data to all MTL units respectively; if the data is multicast packet, the MAC copies the data and respectively sends the data to at least two MTL units corresponding to the target address of the first Ethernet data frame; if the packet is unicast, the MAC determines the data transmission order based on the priority of the data frame.
In step 202, a DMA unit corresponding to a target MTL unit transfers a first ethernet data frame from the target MTL unit to a target memory area of a shared memory of a multi-core heterogeneous SOC.
The target memory area is a memory area which is configured in a one-to-one correspondence with the target application domain core in the shared memory.
In step 203, the target application domain core reads the first ethernet data frame from the target memory area.
In the embodiment of the application, the method further comprises the following steps: after the first ethernet data frame is transmitted to the target memory area of the shared memory, the security domain core triggers the target application domain core to interrupt, so that the target application domain core reads the first ethernet data frame from the target memory area. Therefore, by interrupting the response, delay is reduced, and response speed is improved.
According to the Ethernet bandwidth expansion method based on the multi-core heterogeneous SOC, in response to receiving a first Ethernet data frame, the first Ethernet data frame is transmitted to a corresponding target MTL unit through MAC based on a target application domain core to be received with the first Ethernet data frame; and the first Ethernet data frame is transported from the target MTL unit to a target memory area of the shared memory of the multi-core heterogeneous SOC through a DMA unit corresponding to the target MTL unit; and reading the first Ethernet data frame from the target memory area through the target application domain core. Therefore, the advantages of the multi-core heterogeneous architecture can be fully utilized, the bandwidth of the Ethernet is expanded to a plurality of systems of a plurality of domains of the multi-core heterogeneous SOC by combining the multi-channel and shared memory configuration of a specific Ethernet device, the network communication of a multi-system vehicle can be simplified, the cost is saved, and the multi-channel forwarding of the Ethernet data frame is realized by a small system in a safety domain core through a hardware end function, so that the extra load of the CPU is effectively reduced, and the safety is high.
In the embodiment of the application, the method further comprises the following steps:
in step 204, in response to receiving the ethernet data transmission instruction, the application domain core packages the data to be transmitted, generates a second ethernet data frame, and transmits the second ethernet data frame to the corresponding memory area in the shared memory.
In step 205, the corresponding DMA unit transfers the second ethernet data frame from the corresponding memory area to the corresponding MTL unit.
In step 206, the corresponding MTL unit sends the second ethernet data frame to the MAC, so that the MAC sends the second ethernet data frame out.
Specifically, the application domain core that receives the ethernet data sending instruction may package the sent data through the corresponding ethernet protocol layer to generate a second ethernet data frame, transmit the second ethernet data frame to the shared memory area corresponding to the application domain core one to one, and then trigger the enable bit of the DMA unit corresponding to the application domain core. In response to the enable bit being triggered, the corresponding DMA unit carries the second ethernet data frame from the corresponding memory region to the corresponding MTL unit.
Further, step 206 may specifically be: and acquiring the priority of the second Ethernet data frame, and based on the priority, the corresponding DMA unit sends the second Ethernet data frame to the corresponding MTL unit.
It will be appreciated that the corresponding DMA unit may also send the second ethernet data frame to the corresponding MTL unit based on the size of the number of the second ethernet data frame to be received. The present application is not particularly limited thereto.
In a specific example, the priority of the second ethernet data frame is the same as the priority of the application domain core from which the second ethernet data frame originated.
In a specific example, before transmitting the ethernet data frame, the method may further include: and configuring the Ethernet data transmission priority of the application domain core in the multi-core heterogeneous SOC through the CPU.
The application will be further illustrated and described by means of a specific example.
Fig. 5 is a block diagram of a multi-core heterogeneous SOC-based structure according to the embodiment, and referring to fig. 5, the multi-core heterogeneous SOC is configured with a security domain core and four application domain cores (application domain core 0-application domain core 3), the security domain core is configured with an ethernet control device; the ethernet control device is configured with a media access controller MAC, four direct memory access DMA units (DMA 0-DMA 3), and four media access control layer MTL units (MTL 0-MTL 3) configured in one-to-one correspondence with the application domain core 0-application domain core 3.
The MAC receives the first Ethernet data frame from the outside through the MAC end, and identifies the destination address type of the first Ethernet data frame according to the target application domain core of the first Ethernet data frame through the packet filter.
If it is determined that the first ethernet data frame is a broadcast packet, the MAC determines each of MTL units (MTL 0-MTL 3) in the ethernet control device as a target MTL unit; the MAC copies the Ethernet data frames to obtain four Ethernet data frames, so as to respectively send a first Ethernet data frame to the MTL0-MTL 3. And then, the DMA unit (DMA 0-DMA 3) carries the first Ethernet data frames from the corresponding MTL0-MTL3 to the memory area 0-memory area 3 in a one-to-one correspondence mode. The security domain core triggers the interruption of the application domain core 0-3 so that the application domain core 0-3 reads the first ethernet data frame from the memory area 0-3 in a one-to-one correspondence.
If the first Ethernet data frame is determined to be a multicast packet, the MAC determines two corresponding target MTL units (MTL 0 and MTL 1) according to two application domain cores (application domain core 0 and application domain core 1) of the first Ethernet data frame to be received; the MAC copies the Ethernet data frames to obtain two Ethernet data frames, so as to respectively send a first Ethernet data frame to MTL0 and MTL 1. Then, the DMA unit (DMA 0, DMA 1) transfers the first ethernet data frame from the MTL0, MTL1 to the memory area 0,1 of the shared memory in one-to-one correspondence, respectively. The security domain core triggers the interruption of the application domain core 0 and the application domain core 1, so that the application domain core 0 and the application domain core 1 read the first Ethernet data frame from the memory area 0 and the memory area 1 in a one-to-one correspondence.
If it is determined that the first ethernet data frame is a unicast packet, the MAC determines a corresponding one of the target MTL units (MTL 1) according to the application domain core (application domain core 1) to which the first ethernet data frame is to be received. The MAC acquires the priority of the first ethernet data frame (priority 1) and based on the priority, the MAC transmits the first ethernet data frame to the MTL 1. Then, the corresponding DMA1 transfers the first ethernet data frame from the MTL1 to the memory area 1 of the shared memory. The security domain core triggers the application domain core 1 to interrupt, and the application domain core 1 reads the first ethernet data frame from the corresponding memory area 1.
If an Ethernet data sending instruction is received, the application domain core 2 packages the data to be sent, generates a second Ethernet data frame and transmits the second Ethernet data frame to the memory area 2 in the shared memory; the corresponding DMA2 carries the second ethernet data frame from the memory area 2 to the MTL2. Then, the priority (priority 2) of the second ethernet data frame is acquired, and the second ethernet data frame is transmitted to the corresponding MTL2 based on the priority 2, dma2.
In summary, according to the ethernet bandwidth extension method based on the multi-core heterogeneous SOC of the embodiment of the present application, in response to receiving the first ethernet data frame, the first ethernet data frame is transmitted to the corresponding target MTL unit through the MAC based on the target application domain core to which the first ethernet data frame is to be received; and the first Ethernet data frame is transported from the target MTL unit to a target memory area of the shared memory of the multi-core heterogeneous SOC through a DMA unit corresponding to the target MTL unit; and reading the first Ethernet data frame from the target memory area through the target application domain core. Therefore, the advantages of the multi-core heterogeneous architecture can be fully utilized, the bandwidth of the Ethernet is expanded to a plurality of systems of a plurality of domains of the multi-core heterogeneous SOC by combining the multi-channel and shared memory configuration of a specific Ethernet device, the network communication of a multi-system vehicle can be simplified, the cost is saved, and the multi-channel forwarding of the Ethernet data frame is realized by a small system in a safety domain core through a hardware end function, so that the extra load of the CPU is effectively reduced, and the safety is high.
The embodiment of the application also provides an Ethernet control device based on the multi-core heterogeneous SOC. As shown in fig. 1, the ethernet control device 130 based on the multi-core heterogeneous SOC 100 includes a media access controller MAC 131, at least two media access control layer MTL units 132, and a direct memory access DMA unit 133.
Wherein, in response to receiving the first ethernet data frame, the MAC 131 transmits the first ethernet data frame to the corresponding target MTL unit 132 based on the target application domain core to which the first ethernet data frame is to be received.
At least two MTL units 132, configured in one-to-one correspondence with at least two application domain cores, are configured to correspondingly receive the first ethernet data frame sent by the MAC 131.
A DMA unit 133, configured to be corresponding to the MTL unit 132 in the ethernet control device 130, and configured to transfer the first ethernet data frame from the target MTL unit 132 to a target memory area of the shared memory of the multi-core heterogeneous SOC, so that the target application domain core reads the first ethernet data frame from the target memory area; the target memory area is a memory area which is configured in one-to-one correspondence with the target application domain core in the shared memory.
In the embodiment of the present application, the MAC 131 is specifically configured to: identifying a destination address type of the first Ethernet data frame according to a target application domain core of the first Ethernet data frame; in response to determining that the first ethernet data frame is a broadcast packet, determining each MTL unit 132 in the ethernet control device 130 as a target MTL unit 132; the ethernet data frames are copied and the first ethernet data frames are sent to each MTL unit 132 separately.
Further, the MAC 131 is also configured to: in response to determining that the first ethernet data frame is a multicast packet, determining corresponding at least two target MTL units 132 according to an application domain core to which the first ethernet data frame is to be received; the ethernet data frames are copied and the first ethernet data frame is sent to at least two target MTL units 132, respectively.
In the embodiment of the present application, the MAC 131 is further configured to: in response to determining that the first ethernet data frame is a unicast packet, the MAC 131 determines a corresponding one of the target MTL units 132 according to an application domain core to which the first ethernet data frame is to be received; and acquiring the priority of the first Ethernet data frame, and routing the first Ethernet data frame to the target MTL unit based on the priority.
In the embodiment of the present application, the security domain core 110 configured by the ethernet control device 130 is configured to: after the first ethernet data frame is transferred to the target memory area of the shared memory 140, the security domain core 110 triggers the target application domain core interrupt to cause the target application domain core to read the first ethernet data frame from the target memory area.
In the embodiment of the present application, the application domain core of the multi-core heterogeneous SOC configured by the ethernet control device 130 is used for 120: in response to receiving the ethernet data transmission instruction, the application domain core 120 packages the data to be transmitted, generates a second ethernet data frame, and transmits the second ethernet data frame to the corresponding memory area in the shared memory 140.
The corresponding DMA unit 133 is configured to: the second ethernet data frame is carried from the corresponding memory region to the corresponding MTL unit 132.
The corresponding MTL unit 132 is for: the second ethernet data frame is sent to MAC 131 so that MAC 131 outsources the second ethernet data frame.
Further, the DMA unit 133 is configured to: the priority of the second ethernet data frame is acquired, and based on the priority, the corresponding DMA unit 133 transmits the second ethernet data frame to the corresponding MTL unit 132.
In the embodiment of the present application, the CPU of the multi-core heterogeneous SOC 100 is configured to: the pre-association configuration between the DMA unit 133 and the MTL unit 132 is performed before the ethernet data frame is transmitted. The number of the DMA units 133 is the same as that of the MTL units 132 in the ethernet control device 130, and the DMA units are configured in a one-to-one correspondence manner; or, the DMA unit 133 dynamically binds the configuration with the MTL unit 132 in the ethernet control device 130.
It should be noted that, the explanation of the ethernet bandwidth extension method based on the multi-core heterogeneous SOC in the above embodiment is also applicable to the ethernet control device based on the multi-core heterogeneous SOC in the above embodiment, which is not repeated here.
The embodiment of the application also provides a chip, which is a multi-core heterogeneous SOC, as shown in FIG. 1, wherein the multi-core heterogeneous SOC 100 is configured with a security domain core 110 and at least two application domain cores 120; the security domain core 110 is configured with the ethernet control device 130 in the above embodiment.
In a specific example, the multi-core heterogeneous SOC may be a vehicle-mounted chip.
Those of ordinary skill in the art will appreciate that: the above is only a preferred embodiment of the present application, and the present application is not limited thereto, but it is to be understood that the present application is described in detail with reference to the foregoing embodiments, and modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (8)

1. An Ethernet bandwidth expansion method based on multi-core heterogeneous SOC is characterized in that the multi-core heterogeneous SOC is configured with a security domain core and at least two application domain cores, and the security domain core is configured with an Ethernet control device; the Ethernet control device is configured with a Media Access Controller (MAC), a Direct Memory Access (DMA) unit and at least two media access control layer (MTL) units which are configured in one-to-one correspondence with the at least two application domain cores; the method may include the steps of,
In response to receiving a first ethernet data frame, the MAC transmits the first ethernet data frame to a corresponding target MTL unit based on a target application domain core to which the first ethernet data frame is to be received;
A DMA unit corresponding to the target MTL unit, for transferring the first ethernet data frame from the target MTL unit to a target memory area of the shared memory of the multi-core heterogeneous SOC; the target memory area is a memory area which is configured in one-to-one correspondence with the target application domain core in the shared memory;
After the first ethernet data frame is transmitted to the target memory area of the shared memory, the security domain core triggers the target application domain core to interrupt, so that the target application domain core reads the first ethernet data frame from the target memory area;
In response to receiving an Ethernet data sending instruction, the application domain core packages data to be sent, generates a second Ethernet data frame and transmits the second Ethernet data frame to a corresponding memory area in the shared memory;
the corresponding DMA unit conveys the second Ethernet data frame from the corresponding memory area to the corresponding MTL unit;
The corresponding MTL unit sends the second Ethernet data frame to the MAC so that the MAC can send the second Ethernet data frame out.
2. The method of claim 1, wherein the step of the MAC transmitting the first Ethernet data frame to the corresponding target MTL unit based on the target application domain core to which the first Ethernet data frame is to be received comprises,
The MAC identifies the destination address type of the first Ethernet data frame according to the target application domain core of the first Ethernet data frame;
In response to determining that the first ethernet data frame is a broadcast packet, the MAC determines each MTL unit in the ethernet control device as the target MTL unit;
and the MAC copies the Ethernet data frame and respectively sends the first Ethernet data frame to each MTL unit.
3. The method of claim 2, further comprising,
In response to determining that the first ethernet data frame is a multicast packet, the MAC determines at least two corresponding target MTL units according to an application domain core to which the first ethernet data frame is to be received;
And the MAC copies the Ethernet data frame and respectively sends the first Ethernet data frame to the at least two target MTL units.
4. The method of claim 2, further comprising,
In response to determining that the first ethernet data frame is a unicast packet, the MAC determines a corresponding one of the target MTL units according to an application domain core to which the first ethernet data frame is to be received;
The MAC obtains a priority of the first ethernet data frame and routes the first ethernet data frame to the target MTL unit based on the priority.
5. The method of claim 1, wherein the step of the corresponding DMA unit transferring the second Ethernet data frame from the corresponding memory region to the corresponding MTL unit comprises,
And acquiring the priority of the second Ethernet data frame, and based on the priority, the corresponding DMA unit carries the second Ethernet data frame to the corresponding MTL unit.
6. The method according to any of claims 1-5, wherein prior to transmitting an ethernet data frame, the method further comprises performing a pre-association configuration between the DMA unit and the MTL unit; wherein,
The number of the DMA units is the same as that of the MTL units in the Ethernet control device, and the DMA units are in one-to-one correspondence with the MTL units in the Ethernet control device; or alternatively, the first and second heat exchangers may be,
And the DMA unit is dynamically bound and configured with an MTL unit in the Ethernet control device.
7. An ethernet control device based on a multi-core heterogeneous SOC, wherein the multi-core heterogeneous SOC is configured with a security domain core and at least two application domain cores; the ethernet control device is configured in the security domain core to implement the ethernet bandwidth extension method based on multi-core heterogeneous SOC as set forth in claim 1; the apparatus may be configured to be coupled to a device,
A Media Access Controller (MAC), in response to receiving a first Ethernet data frame, transmitting the first Ethernet data frame to a corresponding target MTL unit based on a target application domain core to be received;
the at least two media access control layer (MTL) units are configured in one-to-one correspondence with the at least two application domain cores and are used for correspondingly receiving the first Ethernet data frame sent by the MAC;
A direct memory access DMA unit, configured to be corresponding to an MTL unit in the ethernet control device, and configured to carry the first ethernet data frame from the target MTL unit to a target memory area of a shared memory of the multi-core heterogeneous SOC, so that the target application domain core reads the first ethernet data frame from the target memory area; the target memory area is a memory area which is configured in the shared memory in one-to-one correspondence with the target application domain core.
8. A chip, wherein the chip is a multi-core heterogeneous SOC configured with a security domain core and at least two application domain cores; the security domain core configured with the ethernet control device of claim 7.
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