CN118100877A - Linear adjusting device and method in single-ended analog duty cycle adjuster - Google Patents
Linear adjusting device and method in single-ended analog duty cycle adjuster Download PDFInfo
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- CN118100877A CN118100877A CN202410470956.1A CN202410470956A CN118100877A CN 118100877 A CN118100877 A CN 118100877A CN 202410470956 A CN202410470956 A CN 202410470956A CN 118100877 A CN118100877 A CN 118100877A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
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Abstract
The invention provides a linear adjusting device and a method in a single-ended analog duty cycle adjuster, which relate to the technical field of duty cycle linear adjustment and comprise the following steps: the main circuit is used for being conducted when the duty ratio of an input clock signal does not need to be adjusted, and comprises a first inverter and a second inverter which are connected in series, wherein the first inverter and the second inverter comprise a P-MOS tube and an N-MOS tube; the device comprises a coarse tuning circuit and a fine tuning circuit which are connected in series, wherein the coarse tuning circuit comprises a plurality of groups of first fitting branches connected in parallel, and each first fitting branch comprises a P_1-MOS tube, an N_1-MOS tube and a resistor R ‑ c which are connected in series. The invention selects the resistor with small temperature and voltage variation, avoids the large-range variation of the duty ratio generated by adopting the pure MOS transistor as the equivalent resistor, and ensures the adjustment precision of the duty ratio range of the input clock signal; the difference between the MOS tubes connected in series and parallel is compensated, so that the arrival time of different signals is more consistent, the duty ratio change of an input clock signal is more linear, and the performance and stability of the circuit are improved.
Description
Technical Field
The invention relates to the technical field of duty cycle linear adjustment, in particular to a linear adjustment device and a linear adjustment method in a single-ended analog duty cycle adjuster.
Background
Along with the faster and faster demand on clock signal speed, the process, voltage and temperature changes will affect the duty ratio of the signal, so that errors are generated in the signal processing and the computing capability of the chip are affected, so that the improvement of the duty ratio of the clock signal in the high-speed application scene has urgent demand.
In the prior art, a parallel coarse-fine tuning device in a single-ended analog duty cycle adjuster has the application publication number CN117498840A, and the device comprises a main circuit, a first inverter and a second inverter, wherein the main circuit is used for being conducted when the duty cycle of an input clock signal does not need to be adjusted and comprises a first inverter and a second inverter which are connected in series; the multi-stage coarse tuning circuit is used for adjusting the duty ratio of an input clock signal in a large range, and comprises a first-stage coarse tuning circuit and a second-stage coarse tuning circuit, wherein the input end of the first-stage coarse tuning circuit is connected with the input end of a first inverter in parallel, the input end of the second-stage coarse tuning circuit is connected with the output end of the first-stage coarse tuning circuit in cascade, the output end of the second-stage coarse tuning circuit is connected with the output end of the second inverter in parallel, the multi-stage fine tuning circuit is used for adjusting the duty ratio of the input clock signal in fine mode, the multi-stage fine tuning circuit comprises a first-stage fine tuning circuit and a second-stage fine tuning circuit, the input end of the first-stage fine tuning circuit is connected with the input end of the first inverter in parallel, the output end of the second-stage fine tuning circuit is connected with the output end of the second inverter in parallel, the first-stage coarse tuning circuit comprises a P0-MOS tube and a N0-MOS tube which are connected in parallel, the second-stage fine tuning circuit comprises a P1-MOS tube and a N1-MOS tube which are connected in parallel, and the first-stage fine tuning circuit comprises a P2-MOS tube and a N2-MOS tube which are connected in parallel. According to the invention, the duty ratio of the input clock signal is adjusted by increasing the sizes of the N-MOS tube and the P-MOS tube.
But there are also the following disadvantages: it can be seen from the above description that when only the MOS transistors are connected in series and parallel, the threshold voltage of the MOS transistors is affected due to the temperature and voltage changes, and the on and off states of the MOS transistors are affected due to the change of the threshold voltage, so that the signal transmission and response time in the circuit are changed, and the adjustment accuracy of the duty ratio range of the input clock signal is affected.
Disclosure of Invention
The present invention is directed to a linear adjusting device and method in a single-ended analog duty cycle adjuster, so as to solve the above-mentioned problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
A linear adjustment device in a single-ended analog duty cycle adjuster, comprising:
The main circuit is used for being conducted when the duty ratio of an input clock signal does not need to be adjusted, and comprises a first inverter and a second inverter which are connected in series, wherein the first inverter and the second inverter comprise a P-MOS tube and an N-MOS tube;
the device comprises a coarse tuning circuit and a fine tuning circuit which are connected in series, wherein the coarse tuning circuit comprises a plurality of groups of first fitting branches connected in parallel, the first fitting branches comprise P_1-MOS tubes, N_1-MOS tubes and resistors R - c which are connected in series, the second fitting branches comprise P_1-MOS tubes, N_1-MOS tubes and resistors RX which are connected in series, the first fitting branches and the second fitting branches are connected in parallel in sequence, the fine tuning circuit comprises a plurality of groups of third fitting branches connected in parallel, the third fitting branches comprise P_2-MOS tubes, N_2-MOS tubes and resistors R - f which are connected in series, the fourth fitting branches comprise P_2-MOS tubes, N_2-MOS tubes and resistors RY which are connected in series, and the third fitting branches and the fourth fitting branches are connected in parallel continuously.
Further, the method further comprises the following steps:
the duty ratio detector is electrically connected with the coarse adjustment mode completion detector and the fine adjustment mode completion detector and is used for transmitting rising edge signals from 0 to 1 or falling edge signals from 1 to 0 generated by an input clock signal to the coarse adjustment mode completion detector and the fine adjustment mode completion detector;
The coarse adjustment mode completion detector is used for detecting that the coarse adjustment mode is completed when the duty ratio detector detects that the input clock signal changes;
The fine adjustment mode completion detector is used for detecting that the fine adjustment mode is completed when the duty ratio detector detects that an input clock signal changes;
A coarse duty cycle corrector counter electrically connected to the coarse mode completion detector for generating a coarse 5bit code value;
a fine-tuning duty cycle corrector counter electrically connected to the fine-tuning mode completion detector for generating a coarse-tuning 5bit code value;
And the latch is used for receiving signals of the coarse duty cycle corrector counter and the fine duty cycle corrector counter and respectively latching values of P_1<4:0>, N_1<4:0>, P_2<4:0> and N_2<4:0 >.
Further, the value of X in the resistor RX is 0 to 3, and the value of Y in the resistor RY is 4 to 7.
Further, the duty ratio range adjusted by the coarse adjustment circuit is 0-15%, and the duty ratio range adjusted by the fine adjustment circuit is 0-5%.
Further, the duty ratio detector is a digital logic circuit built by a latch circuit and a counting circuit, the coarse adjustment mode completion detector and the fine adjustment mode completion detector are integrated circuits of the digital logic circuit and a comparator circuit for detecting duty ratio, the counter of the coarse adjustment duty ratio corrector and the counter of the fine adjustment duty ratio corrector are digital logic circuits built by a timing trigger circuit, a latch circuit and the counting circuit, and the latch is a D trigger.
A method of linear adjustment in a single-ended analog duty cycle adjuster, the method of linear adjustment in a single-ended analog duty cycle adjuster being based on a linear adjustment device in a single-ended analog duty cycle adjuster as set forth in any one of the preceding claims, the method comprising the steps of:
s1, in an initial state, setting P_1<4:0> = 01111, and N_1<4:0> = 10000;
S2, coarse adjustment, namely conducting a single branch at each time, wherein the highest position determines the maximum adjustable range, the resistance of the highest position is a reference, the resistance is gradually switched from 1 time to 0.8 time, 0.6 time, 0.4 time and 0.2 time from the maximum value, 15% of the coarse adjustment range is divided into 5 gears, and when the R - c branch is conducted, the maximum adjustable value is 15%, P_1<4:0> =01111, and N_1<4:0> =10000; when the R - c branch and R0 are conducted, in order to make the equivalent resistance be 0.8 times of the reference, R0 of 4R needs to be connected in parallel, the adjustment range is 12%, P_1<4:0> =00111, and N_1<4:0> =11000; when the R - c branch and the R1 are conducted, in order to make the equivalent resistance be 0.6 times of the reference, R1 of 1.5R is required to be connected in parallel, the adjustment range is 9%, P_1<4:0> =01011, and N_1<4:0> =10100; when the R - c branch and the R2 are conducted, in order to make the equivalent resistance be 0.4 times of the reference, the R2 of 0.667R is required to be connected in parallel, the adjustment range is 6%, P_1<4:0> =01101, and N_1<4:0> =10010; when the R - c branch and R3 are conducted, in order to enable the equivalent resistance to be 0.2 times of a reference, R3 of 0.25R is required to be connected in parallel, the adjustment range is 3%, P_1<4:0> =01110, N_1<4:0> =10001, when the duty ratio of an input clock signal is greater than or less than 50%, a switching signal from 0 to 1 or from 1 to 0 is output by a duty ratio detector, then the coarse adjustment mode completion detector detects that the coarse adjustment mode is completed, the coarse adjustment duty ratio corrector counter stops working, the values of P_1<4:0> and N_1<4:0> are latched by a latch, and the coarse adjustment process of the duty ratio is finished;
S3, fine adjustment, wherein a thermometer code is adopted for fine adjustment resistance coding, resistors are continuously connected in parallel, the highest resistance of the whole adjustment range is used as a reference, the resistor is gradually switched from the maximum value of 1 time to 0.8 time, 0.6 time and 0.4 time, 0.2 time, the fine adjustment range of 5% is divided into 5 gears, when an R - f branch is conducted, 4R 4 is required to be connected in parallel in order to enable the equivalent resistance to be 0.8 time, the maximum value of adjustment is 5%, P_2<4:0> = 01111, and N_2<4:0> = 10000; when the R - f branch and the R4 are conducted, R5 of 2.4R is required to be connected in parallel in order to make the equivalent resistance be 0.6 times of the reference, the adjustment range is 4%, P_2<4:0> =00111, and N_2<4:0> =11000; when the R - f branch, the R4 and the R5 are conducted, R6 of 1.2R is required to be connected in parallel in order to make the equivalent resistance be 0.4 times of the reference, the adjustment range is 3%, P_2<4:0> =00011, and N_2<4:0> =11100; when the R - f branch, the R4, the R5 and the R6 are conducted, R7 of 0.4R is required to be connected in parallel in order to make the equivalent resistance be 0.2 times of the reference, the adjustment range is 2%, P_2<4:0> =00001, and N_2<4:0> =11110; when the R - f branch, the R4, the R5, the R6 and the R7 are conducted, the adjustment range is 1%, P_2<4:0> =00000, N_2<4:0> =11111, when the duty ratio of an input clock signal is more or less than 50%, the duty ratio detector outputs a turnover signal from 0 to 1 or from 1 to 0, then the fine adjustment mode completion detector detects that the fine adjustment mode is completed, the fine adjustment duty ratio corrector counter stops working, the values of P_2<4:0> and N_2<4:0> are latched by the latch, and the fine adjustment process of the duty ratio is ended.
Compared with the prior art, the invention has the beneficial effects that:
According to the invention, the first phase inverter is connected in series with the second phase inverter, the coarse tuning circuit is connected in series with the fine tuning circuit, the P_1-MOS tube, the N_1-MOS tube and the resistor R - c are connected in series, the P_1-MOS tube, the N_1-MOS tube and the resistor RX are connected in series, the first fitting branch and the second fitting branch are sequentially connected in parallel, the P_2-MOS tube, the N_2-MOS tube and the resistor R - f are connected in series, the P_2-MOS tube, the N_2-MOS tube and the resistor RY are connected in series, and the third fitting branch and the fourth fitting branch are continuously connected in parallel. Therefore, the rising time or the falling time of the signal is changed by fitting the equivalent resistance of the output end, so that the aim of adjusting the duty ratio is fulfilled, the coarse adjustment adopts a thermal code mode, the adjustment range is larger and more accurate, the fine adjustment adopts a thermometer coding mode, when each gear of the resistance is linear change, tr/Tf can also be linearly changed, thereby realizing good duty ratio linearity, simultaneously selecting the resistance with small temperature and voltage change, avoiding the wide-range change of the duty ratio generated by adopting a pure MOS tube as the equivalent resistance, and ensuring the adjustment precision of the duty ratio range of the input clock signal;
By connecting the P_1-MOS tube, the N_1-MOS tube and the resistor RX in series, the P_2-MOS tube, the N_2-MOS tube and the resistor RY are connected in series, and the resistor RX is added in the P_1-MOS tube and the N_1-MOS tube circuit, and the extra delay is introduced in the P_2-MOS tube and the N_2-MOS tube circuit in a manner of adding the resistor RY, so that the difference between the MOS tubes connected in series and parallel is compensated, the arrival time of different signals is more consistent, and the change of the duty ratio of an input clock signal is more linear, thereby improving the performance and the stability of the circuit.
Drawings
FIG. 1 is a schematic diagram of the overall circuit of the present invention;
FIG. 2 is a control circuit diagram of duty cycle adjustment according to the present invention;
FIG. 3 is a table fit for coarse linearity resistance of the present invention;
FIG. 4 is a table of a fit of the fine-tuned linearity resistance of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples:
referring to fig. 1 to 3, the present invention provides a technical solution:
a linear adjustment device in a single-ended analog duty cycle adjuster, as shown in fig. 1, comprising:
The main circuit is used for being conducted when the duty ratio of an input clock signal does not need to be adjusted, and comprises a first inverter and a second inverter which are connected in series, wherein the first inverter and the second inverter comprise a P-MOS tube and an N-MOS tube;
the device comprises a coarse tuning circuit and a fine tuning circuit which are connected in series, wherein the coarse tuning circuit comprises a plurality of groups of first fitting branches connected in parallel, the first fitting branches comprise P_1-MOS tubes, N_1-MOS tubes and resistors R - c which are connected in series, the second fitting branches comprise P_1-MOS tubes, N_1-MOS tubes and resistors RX which are connected in series, the first fitting branches and the second fitting branches are connected in parallel in sequence, the fine tuning circuit comprises a plurality of groups of third fitting branches connected in parallel, the third fitting branches comprise P_2-MOS tubes, N_2-MOS tubes and resistors R - f which are connected in series, the fourth fitting branches comprise P_2-MOS tubes, N_2-MOS tubes and resistors RY which are connected in series, and the third fitting branches and the fourth fitting branches are connected in parallel continuously.
On the basis of the above embodiment, as shown in fig. 2, the method further includes:
the duty ratio detector is electrically connected with the coarse adjustment mode completion detector and the fine adjustment mode completion detector and is used for transmitting rising edge signals from 0 to 1 or falling edge signals from 1 to 0 generated by an input clock signal to the coarse adjustment mode completion detector and the fine adjustment mode completion detector;
The coarse adjustment mode completion detector is used for detecting that the coarse adjustment mode is completed when the duty ratio detector detects that the input clock signal changes;
The fine adjustment mode completion detector is used for detecting that the fine adjustment mode is completed when the duty ratio detector detects that an input clock signal changes;
a counter of the coarse duty cycle corrector, wherein the counter of the coarse duty cycle corrector is electrically connected with the coarse mode completion detector and is used for generating a coarse 5bit code value;
A counter of the fine-tuning duty cycle corrector, the counter of the fine-tuning duty cycle corrector being electrically connected to the fine-tuning mode completion detector for generating a coarse-tuning 5bit code value;
And the latch is used for receiving signals of the coarse duty cycle corrector counter and the fine duty cycle corrector counter and respectively latching values of P_1<4:0>, N_1<4:0>, P_2<4:0> and N_2<4:0 >.
On the basis of the above embodiment, as shown in fig. 1, the value of X in the resistor RX is 0 to 3, and the value of Y in the resistor RY is 4 to 7.
On the basis of the embodiment, the duty ratio range adjusted by the coarse adjustment circuit is 0-15%, and the duty ratio range adjusted by the fine adjustment circuit is 0-5%.
On the basis of the embodiment, the duty ratio detector is a digital logic circuit built by a latch circuit and a counting circuit, the coarse adjustment mode completion detector and the fine adjustment mode completion detector are integrated circuits of a digital logic circuit and a comparator circuit for detecting duty ratio, the counter of the coarse adjustment duty ratio corrector and the counter of the fine adjustment duty ratio corrector are digital logic circuits built by a timing trigger circuit, a latch circuit and a counting circuit, and the latch is a D trigger.
In this embodiment, the detection process of the duty ratio detector: the duty cycle detector detects a change in duty cycle, in particular a rising edge from 0 to 1 or a falling edge from 1 to 0, and upon detection of a rising or falling edge the detector generates a pulse or continuous signal which acts to stop the count of the duty cycle corrector counter, the latch latching the values of P_1<4:0>, N_1<4:0>, P_2<4:0> and N_2<4:0 >.
In this embodiment, the counting process of the counter of the coarse duty cycle corrector and the counter of the fine duty cycle corrector includes: in the initial state, the counter output initial value is usually set to be 0000, for example, when an external trigger signal (for example, a clock signal) arrives, the counter starts to operate, when the edge (rising edge or falling edge) of each input clock signal arrives, the counter count value increases, the counter can be increased (from a lower value to a higher value 0000= = 0001= 0011= 0111= 1111) or decreased (from a higher value to a lower value 1111= 0111= 0001= 0000 0001=), the counter outputs the current count value to the corresponding output port, the output can be binary number, when the output of the duty ratio detector generates a flip signal (from a rising edge of 0 to 1 or a falling edge signal from 1 to 0), the counter stops counting, and the value of the counter can be latched by the counter.
The timer trigger circuit, the latch circuit, the counter circuit and the comparator are all in the prior art, so that the duty ratio detectors built by the timer trigger circuit, the latch circuit and the counter circuit are in the prior art, the coarse adjustment mode completion detector and the fine adjustment mode completion detector are in the prior art, and the counter of the coarse adjustment duty ratio corrector and the counter of the fine adjustment duty ratio corrector are in the prior art, and the latch consisting of the D trigger is in the prior art because the D trigger is in the prior art.
In this embodiment, the coarse adjustment mode completion detector and the fine adjustment mode completion detector compare the calculated duty ratio with a set coarse adjustment or fine adjustment threshold, and trigger a coarse adjustment or fine adjustment mode completion state if the output of the counter satisfies the coarse adjustment or fine adjustment threshold.
A method of linear adjustment in a single-ended analog duty cycle adjuster, the method of linear adjustment in a single-ended analog duty cycle adjuster being based on a linear adjustment device in a single-ended analog duty cycle adjuster as set forth in any one of the preceding claims, the method comprising the steps of:
s1, in an initial state, setting P_1<4:0> = 01111, and N_1<4:0> = 10000;
S2, coarse adjustment, namely conducting a single branch at each time, wherein the highest position determines the maximum adjustable range, the resistance of the highest position is a reference, the resistance is gradually switched from 1 time to 0.8 time, 0.6 time, 0.4 time and 0.2 time from the maximum value, 15% of the coarse adjustment range is divided into 5 gears, and when the R - c branch is conducted, the maximum adjustable value is 15%, P_1<4:0> =01111, and N_1<4:0> =10000; when the R - c branch and R0 are conducted, in order to make the equivalent resistance be 0.8 times of the reference, R0 of 4R needs to be connected in parallel, the adjustment range is 12%, P_1<4:0> =00111, and N_1<4:0> =11000; when the R - c branch and the R1 are conducted, in order to make the equivalent resistance be 0.6 times of the reference, R1 of 1.5R is required to be connected in parallel, the adjustment range is 9%, P_1<4:0> =01011, and N_1<4:0> =10100; when the R - c branch and the R2 are conducted, in order to make the equivalent resistance be 0.4 times of the reference, the R2 of 0.667R is required to be connected in parallel, the adjustment range is 6%, P_1<4:0> =01101, and N_1<4:0> =10010; when the R - c branch and R3 are conducted, in order to enable the equivalent resistance to be 0.2 times of a reference, R3 of 0.25R is required to be connected in parallel, the adjustment range is 3%, P_1<4:0> =01110, N_1<4:0> =10001, because T=RC, when each gear of the resistance is linear change, tr (rise time)/Tf (fall time) also linearly changes, so that good duty cycle linearity is realized, as the duty cycle of an input clock signal is greater than or less than 50%, a switching signal from 0 to 1 or from 1 to 0 is output by a duty cycle detector, then coarse adjustment mode completion detector detects coarse adjustment mode completion, the duty cycle corrector counter stops working, the values of P_1<4:0> and N_1<4:0> are latched by a latch, and the course of the duty cycle is finished;
S3, fine adjustment, wherein a thermometer code is adopted for fine adjustment resistance coding, resistors are continuously connected in parallel, the highest resistance of the whole adjustment range is used as a reference, the resistor is gradually switched from the maximum value of 1 time to 0.8 time, 0.6 time and 0.4 time, 0.2 time, the fine adjustment range of 5% is divided into 5 gears, when an R - f branch is conducted, 4R 4 is required to be connected in parallel in order to enable the equivalent resistance to be 0.8 time, the maximum value of adjustment is 5%, P_2<4:0> = 01111, and N_2<4:0> = 10000; when the R - f branch and the R4 are conducted, R5 of 2.4R is required to be connected in parallel in order to make the equivalent resistance be 0.6 times of the reference, the adjustment range is 4%, P_2<4:0> =00111, and N_2<4:0> =11000; when the R - f branch, the R4 and the R5 are conducted, R6 of 1.2R is required to be connected in parallel in order to make the equivalent resistance be 0.4 times of the reference, the adjustment range is 3%, P_2<4:0> =00011, and N_2<4:0> =11100; when the R - f branch, the R4, the R5 and the R6 are conducted, R7 of 0.4R is required to be connected in parallel in order to make the equivalent resistance be 0.2 times of the reference, the adjustment range is 2%, P_2<4:0> =00001, and N_2<4:0> =11110; when the R - f branch, the R4, the R5, the R6 and the R7 are conducted, the adjustment range is 1%, P_2<4:0> =00000, N_2<4:0> =11111, because T=RC, when each gear of the resistor is linear change, tr (rise time)/Tf (fall time) also linearly changes, so that good duty cycle linearity is realized, as the duty cycle of an input clock signal is greater than or less than 50%, the duty cycle detector outputs a turnover signal from 0 to 1 or from 1 to 0, then the fine adjustment mode completion detector detects that the fine adjustment mode is completed, the fine adjustment duty cycle corrector counter stops working, the values of P_2<4:0> and N_2<4:0> are latched by the latch, and the fine adjustment process of the duty cycle is ended.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A linear adjustment device in a single-ended analog duty cycle adjuster, comprising:
The main circuit is used for being conducted when the duty ratio of an input clock signal does not need to be adjusted, and comprises a first inverter and a second inverter which are connected in series, wherein the first inverter and the second inverter comprise a P-MOS tube and an N-MOS tube;
The device comprises a coarse tuning circuit and a fine tuning circuit which are connected in series, wherein the coarse tuning circuit comprises a plurality of groups of first fitting branches and second fitting branches which are connected in parallel, the first fitting branches comprise a P_1-MOS tube, an N_1-MOS tube and a resistor R - c which are connected in series, the second fitting branches comprise a P_1-MOS tube, an N_1-MOS tube and a resistor RX which are connected in series, the first fitting branches and the second fitting branches are connected in parallel in sequence, the fine tuning circuit comprises a plurality of groups of third fitting branches and a fourth fitting branches which are connected in parallel, the third fitting branches comprise a P_2-MOS tube, an N_2-MOS tube and a resistor R - f which are connected in series, and the fourth fitting branches comprise a P_2-MOS tube, an N_2-MOS tube and a resistor RY which are connected in series, and the third fitting branches and the fourth fitting branches are connected in parallel continuously.
2. A linear adjustment device in a single-ended analog duty cycle adjuster as recited in claim 1, further comprising:
the duty ratio detector is electrically connected with the coarse adjustment mode completion detector and the fine adjustment mode completion detector and is used for transmitting rising edge signals from 0 to 1 or falling edge signals from 1 to 0 generated by an input clock signal to the coarse adjustment mode completion detector and the fine adjustment mode completion detector;
The coarse adjustment mode completion detector is used for detecting that the coarse adjustment mode is completed when the duty ratio detector detects that the input clock signal changes;
The fine adjustment mode completion detector is used for detecting that the fine adjustment mode is completed when the duty ratio detector detects that an input clock signal changes;
A coarse duty cycle corrector counter electrically connected to the coarse mode completion detector for generating a coarse 5bit code value;
a fine-tuning duty cycle corrector counter electrically connected to the fine-tuning mode completion detector for generating a coarse-tuning 5bit code value;
And the latch is used for receiving signals of the coarse duty cycle corrector counter and the fine duty cycle corrector counter and respectively latching values of P_1<4:0>, N_1<4:0>, P_2<4:0> and N_2<4:0 >.
3. A linear regulator in a single-ended analog duty cycle adjuster according to claim 1, wherein X in the resistor RX has a value of 0 to 3 and Y in the resistor RY has a value of 4 to 7.
4. A linear adjustment device in a single-ended analog duty cycle adjuster according to claim 1, wherein the coarse adjustment circuit adjusts the duty cycle in the range of 0-15% and the fine adjustment circuit adjusts the duty cycle in the range of 0-5%.
5. The linear adjustment device in a single-ended analog duty cycle adjuster according to claim 2, wherein the duty cycle detector is a digital logic circuit built with a latch circuit and a counter circuit, the coarse adjustment mode completion detector and the fine adjustment mode completion detector are both integrated circuits of a digital logic circuit and a comparator circuit for detecting a duty cycle, and the counter of the coarse adjustment duty cycle corrector and the counter of the fine adjustment duty cycle corrector are digital logic circuits built with a timing trigger circuit, a latch circuit and a counter circuit, and the latch is a D trigger.
6. A method of linear adjustment in a single-ended analog duty cycle adjuster, characterized in that the method of linear adjustment in a single-ended analog duty cycle adjuster is based on a linear adjustment device in a single-ended analog duty cycle adjuster according to any one of claims 1-5, the method comprising the steps of:
s1, in an initial state, setting P_1<4:0> = 01111, and N_1<4:0> = 10000;
S2, coarse adjustment, namely conducting a single branch at each time, wherein the highest position determines the maximum adjustable range, the resistance of the highest position is a reference, the resistance is gradually switched from 1 time to 0.8 time, 0.6 time, 0.4 time and 0.2 time from the maximum value, 15% of the coarse adjustment range is divided into 5 gears, and when the R - c branch is conducted, the maximum adjustable value is 15%, P_1<4:0> =01111, and N_1<4:0> =10000; when the R - c branch and R0 are conducted, in order to make the equivalent resistance be 0.8 times of the reference, R0 of 4R needs to be connected in parallel, the adjustment range is 12%, P_1<4:0> =00111, and N_1<4:0> =11000; when the R - c branch and the R1 are conducted, in order to make the equivalent resistance be 0.6 times of the reference, R1 of 1.5R is required to be connected in parallel, the adjustment range is 9%, P_1<4:0> =01011, and N_1<4:0> =10100; when the R - c branch and the R2 are conducted, in order to make the equivalent resistance be 0.4 times of the reference, the R2 of 0.667R is required to be connected in parallel, the adjustment range is 6%, P_1<4:0> =01101, and N_1<4:0> =10010; when the R - c branch and R3 are conducted, in order to enable the equivalent resistance to be 0.2 times of a reference, R3 of 0.25R is required to be connected in parallel, the adjustment range is 3%, P_1<4:0> =01110, N_1<4:0> =10001, when the duty ratio of an input clock signal is greater than or less than 50%, a switching signal from 0 to 1 or from 1 to 0 is output by a duty ratio detector, then the coarse adjustment mode completion detector detects that the coarse adjustment mode is completed, the coarse adjustment duty ratio corrector counter stops working, the values of P_1<4:0> and N_1<4:0> are latched by a latch, and the coarse adjustment process of the duty ratio is finished;
S3, fine adjustment, wherein a thermometer code is adopted for fine adjustment resistance coding, resistors are continuously connected in parallel, the highest resistance of the whole adjustment range is used as a reference, the resistor is gradually switched from the maximum value of 1 time to 0.8 time, 0.6 time and 0.4 time, 0.2 time, the fine adjustment range of 5% is divided into 5 gears, when an R - f branch is conducted, 4R 4 is required to be connected in parallel in order to enable the equivalent resistance to be 0.8 time, the maximum value of adjustment is 5%, P_2<4:0> = 01111, and N_2<4:0> = 10000; when the R - f branch and the R4 are conducted, R5 of 2.4R is required to be connected in parallel in order to make the equivalent resistance be 0.6 times of the reference, the adjustment range is 4%, P_2<4:0> =00111, and N_2<4:0> =11000; when the R - f branch, the R4 and the R5 are conducted, R6 of 1.2R is required to be connected in parallel in order to make the equivalent resistance be 0.4 times of the reference, the adjustment range is 3%, P_2<4:0> =00011, and N_2<4:0> =11100; when the R - f branch, the R4, the R5 and the R6 are conducted, R7 of 0.4R is required to be connected in parallel in order to make the equivalent resistance be 0.2 times of the reference, the adjustment range is 2%, P_2<4:0> =00001, and N_2<4:0> =11110; when the R - f branch, the R4, the R5, the R6 and the R7 are conducted, the adjustment range is 1%, P_2<4:0> =00000, N_2<4:0> =11111, when the duty ratio of an input clock signal is more or less than 50%, the duty ratio detector outputs a turnover signal from 0 to 1 or from 1 to 0, then the fine adjustment mode completion detector detects that the fine adjustment mode is completed, the fine adjustment duty ratio corrector counter stops working, the values of P_2<4:0> and N_2<4:0> are latched by the latch, and the fine adjustment process of the duty ratio is ended.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
| CN103312299A (en) * | 2012-03-05 | 2013-09-18 | 联发科技（新加坡）私人有限公司 | Signal duty cycle detector and calibration system |
| CN113014233A (en) * | 2021-03-10 | 2021-06-22 | 苏州芯捷联电子有限公司 | Clock duty ratio calibration circuit |
| CN114759906A (en) * | 2022-05-19 | 2022-07-15 | 厦门澎湃微电子有限公司 | Precision-adjustable frequency doubling circuit structure |
| CN117352021A (en) * | 2022-06-29 | 2024-01-05 | 长鑫存储技术有限公司 | Duty cycle correction method, circuit and storage device |
| CN117498840A (en) * | 2023-12-29 | 2024-02-02 | 中茵微电子(南京)有限公司 | Parallel coarse-fine adjustment device in single-ended analog duty cycle regulator |
| CN117560004A (en) * | 2024-01-11 | 2024-02-13 | 中茵微电子(南京)有限公司 | Digital correction device and method for correcting differential mismatch in analog comparator |
-
2024
- 2024-04-18 CN CN202410470956.1A patent/CN118100877B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6320438B1 (en) * | 2000-08-17 | 2001-11-20 | Pericom Semiconductor Corp. | Duty-cycle correction driver with dual-filter feedback loop |
| CN103312299A (en) * | 2012-03-05 | 2013-09-18 | 联发科技（新加坡）私人有限公司 | Signal duty cycle detector and calibration system |
| CN113014233A (en) * | 2021-03-10 | 2021-06-22 | 苏州芯捷联电子有限公司 | Clock duty ratio calibration circuit |
| CN114759906A (en) * | 2022-05-19 | 2022-07-15 | 厦门澎湃微电子有限公司 | Precision-adjustable frequency doubling circuit structure |
| CN117352021A (en) * | 2022-06-29 | 2024-01-05 | 长鑫存储技术有限公司 | Duty cycle correction method, circuit and storage device |
| CN117498840A (en) * | 2023-12-29 | 2024-02-02 | 中茵微电子(南京)有限公司 | Parallel coarse-fine adjustment device in single-ended analog duty cycle regulator |
| CN117560004A (en) * | 2024-01-11 | 2024-02-13 | 中茵微电子(南京)有限公司 | Digital correction device and method for correcting differential mismatch in analog comparator |
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