CN118100629A

CN118100629A - Switching power supply, control circuit and control method thereof

Info

Publication number: CN118100629A
Application number: CN202410175793.4A
Authority: CN
Inventors: 廖小军; 吴江巍; 徐小照; 詹桦
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2024-02-07
Filing date: 2024-02-07
Publication date: 2024-05-28

Abstract

The application discloses a switching power supply, a control circuit and a control method thereof, wherein the control circuit comprises a sampling control module, a first control module, a second control module and a third control module, wherein the sampling control module is used for receiving demagnetizing time and third dithering current, converting a current signal into a voltage signal, and comparing the voltage signal with a second reference voltage to output a sampling control signal; the feedback module receives the sampling control signal, samples the feedback voltage to obtain a first sampling signal according to the sampling control signal, and divides the fourth reference voltage and an error amplification signal of the first sampling signal to generate a third reference voltage representing the peak current of the load state; the peak current jitter control module generates a peak current jitter signal according to the third reference voltage, a second sampling signal representing the primary inductor current and the second jitter current; and the driving module is used for controlling the turn-off of the power tube according to the peak current jitter signal. The application adjusts the sampling time by the generation time of the sampling control signal on the basis of peak current jitter control so as to reduce the output ripple and ensure the control precision of the switching power supply.

Description

Switching power supply, control circuit and control method thereof

Technical Field

The invention relates to the technical field of switching power supplies, in particular to a switching power supply, a control circuit and a control method thereof.

Background

Electromagnetic compatibility (EMC, electromagnetic Compatibility) refers to the ability of a device or system to operate satisfactorily in an electromagnetic environment and not to create intolerable electromagnetic disturbances to any device in its environment. When the switching frequency of the switching power supply is too large, a large amount of harmonic components are transmitted outwards through the transmission line and the space electromagnetic field, so that the electromagnetic compatibility of the switching power supply can be affected.

At present, the electromagnetic compatibility of a switching power supply is often improved through a frequency jitter control technology. Namely, when the control circuit of the switching power supply drives the power tube, frequency jitter is introduced to expand the switching frequency of the power tube to a wider frequency band, so that the peak value of electromagnetic interference (EMI, electromagnetic Interference) generated by the switching power supply at a certain frequency point is reduced. However, the existing frequency jitter control technology generally realizes the switching frequency jitter of the power tube in the switching power supply through a fixed oscillator, so as to generate the fixed switching frequency jitter. However, the above manner can cause the change of the switching frequency, so that the conduction time of the power tube deviates from an ideal value, and the output current of the switching power supply is affected, thereby causing the output ripple to follow the dithering of the dithering rule, increasing the output ripple, and further possibly generating surge voltage or current to cause abnormal operation of the electrical equipment or accelerate the aging of the equipment.

Disclosure of Invention

In view of the foregoing, an object of the present application is to provide a switching power supply, a control circuit and a control method thereof, so as to solve the problems in the prior art.

According to an aspect of the present invention, there is provided a control circuit of a switching power supply, including: the demagnetization detection module is used for detecting the feedback voltage representing the output voltage and obtaining the demagnetization time of the switching power supply; the sampling control module receives the demagnetizing time and the third dithering current, converts the current signal into a voltage signal according to the demagnetizing time, compares the voltage signal with a second reference voltage, and outputs a sampling control signal; the feedback module is used for receiving the sampling control signal, sampling the feedback voltage according to the sampling control signal to obtain a first sampling signal, and dividing the fourth reference voltage and an error amplification signal of the first sampling signal to generate a third reference voltage representing the peak current of the load state; the peak current jitter control module generates a peak current jitter signal according to the third reference voltage, a second sampling signal representing the primary inductor current and the second jitter current; and the driving module is used for controlling the turn-off of the power tube of the switching power supply according to the peak current jitter signal.

Optionally, when the peak current is increased by n×ic from the peak current in the load state, the demagnetizing time is correspondingly prolonged by n×td, and then the sampling time of the feedback module for sampling the feedback voltage is adjusted to be shifted by n×td; when the peak current is reduced by n×ic from the peak current in the load state, the demagnetizing time is correspondingly shortened by n×td, and the sampling time of the feedback module for sampling the feedback voltage is adjusted to advance by n×td, wherein Ic represents the peak current in the load state, TD represents the demagnetizing time, and n is a positive number.

Optionally, the third dithering current received by the sampling control module is opposite to the dithering direction of the second dithering current, and adjusts the slope of the voltage signal in the demagnetizing time according to the third dithering current so as to adjust the sampling time of the feedback voltage, so that the time interval between the sampling time and the demagnetizing ending time is fixed.

Optionally, when the peak current is increased by the peak current in the load state, the demagnetizing time is increased, the third dithering current is reduced, the absolute value of the slope of the voltage signal in the demagnetizing time is reduced, and the sampling time is shifted backward; when the peak current is reduced from the peak current in the load state, the demagnetizing time is reduced, the third dithering current is increased, the absolute value of the slope of the voltage signal in the demagnetizing time is increased, and the sampling time is advanced.

Optionally, the sampling control module discharges the first capacitor through the second reference current and the third dithering current from the demagnetization starting moment, the voltage signal is the voltage on the first capacitor, and the sampling control module adjusts the slope of the voltage signal in the demagnetization time and the discharge speed of the first capacitor according to the third dithering current; charging a first capacitor through a first reference current after demagnetization is finished, so that the voltage signal is lifted; the sampling control module generates the sampling control signal when the voltage signal is lower than the second reference voltage.

Optionally, the absolute value of the slope of the voltage signal in the demagnetizing time is the ratio of the sum of the second reference current and the third dithering current to the capacitance value of the first capacitor.

Optionally, the sampling control module includes: a first capacitor, a first end of which receives a first reference current, a second reference current and a third dithering current, a second end of which is grounded, the first reference current being provided after the demagnetization time is over, the second reference current and the third dithering current being provided within the demagnetization time; the first input end of the first comparator receives the second reference voltage, the second input end of the first comparator is connected with the first end of the first capacitor, and the output end of the first comparator outputs the sampling control signal.

Optionally, the sampling control module includes: a first capacitor, a first end of which receives a first reference current, a second reference current and a plurality of fourth dithering currents, a sum of the magnitudes of the plurality of fourth dithering currents being equal to a magnitude of a third dithering current, a second end of which is grounded, the first reference current being provided after the end of the demagnetization time, the second reference current and the third dithering current being provided within the demagnetization time; the first input end of the first comparator receives the second reference voltage, the second input end of the first comparator is connected with the first end of the first capacitor, and the output end of the first comparator outputs the sampling control signal.

Optionally, the feedback module includes: the switch module receives the sampling control signal, controls the switch module to be conducted according to the sampling control signal so as to sample the feedback voltage, and outputs a first sampling signal; and the feedback processing module generates a third reference voltage representing the peak current of the load state according to the first sampling signal and the fourth reference voltage.

Optionally, the peak current jitter control module includes: a first resistor; a second comparator, a first input terminal of the second comparator receives a second dithering current and the third reference voltage of the peak current signal representing the load state via the first resistor, a second input terminal of the second comparator receives the second sampling signal, and an output terminal of the second comparator outputs the peak current dithering signal.

Optionally, the control circuit further includes a dithering current generation module for generating a dithering current, wherein the dithering current generation module includes: the frequency dividing module is connected with the oscillation module and used for dividing the frequency of the received periodic clock signal to obtain a plurality of frequency dividing signals; the signal inversion module is connected with the frequency division module and is used for performing inversion processing on a plurality of frequency division signals to generate a plurality of inversion signals; a control signal generating module for generating N control signals according to the frequency division signals and the inversion signals; the current dithering module comprises a plurality of current sources with different current amplitudes and control switches connected in series with each current source, and corresponding control signals control the corresponding control switches to be conducted so that the corresponding current sources output currents with corresponding amplitudes, and the current dithering module generates reference dithering currents with 2N steps, wherein N is a natural number greater than or equal to 1; the current mirror module comprises at least two current mirror branches, and the corresponding current mirror branches mirror the reference dithering current according to the mirror proportion and generate dithering current with the same dithering direction as the reference dithering current; or, the corresponding current mirror leg connects in series with a current source at the output node of the dither current to generate a dither current that dithers in a direction opposite to the reference dither current.

Optionally, the switch module includes: the first switch is connected between the feedback voltage and the feedback processing module, the control end of the first switch is connected with the output end of the sampling control module, and the first switch is conducted according to the sampling control signal to sample the feedback voltage to obtain the first sampling signal.

Optionally, the control circuit of the switching power supply further includes: the frequency control module generates a frequency control signal with fixed frequency according to the first reference voltage, and the driving module controls the conduction of the power tube of the switching power supply according to the frequency control signal with fixed frequency.

Optionally, the feedback module further generates a third reference current characterizing a center frequency according to the first sampling signal and a fourth reference voltage, and the control circuit further includes: the frequency control module generates a frequency dithering signal according to a first reference voltage, the third reference current and the first dithering current, the driving module controls the conduction of a power tube of the switching power supply according to the frequency dithering signal, and the dithering directions of the first dithering current and the second dithering current are opposite.

Alternatively, when the switching frequency is increased by m×fc from the center frequency, the control peak current is reduced by n×ic from the peak current of the load state; when the switching frequency is reduced by m×fc from the center frequency, the peak current is controlled to be increased by n×ic from the peak current in the load state, where m/n=k, m, n are the frequency jitter ratio and the peak current jitter ratio, respectively, k is the ratio of the frequency jitter ratio and the peak current jitter ratio, and k is a positive number greater than 1, fc represents the center frequency, and Ic represents the peak current in the load state.

Optionally, the ratio k of the frequency jitter ratio and the peak current jitter ratio is equal to 2.

Optionally, the frequency control module charges a second capacitor through the third reference current and the first dithering current in each switching period, when the terminal voltage of the second capacitor is greater than the first reference voltage, the frequency dithering signal is turned over, and when the frequency dithering signal is turned over, the terminal voltage of the second capacitor is cleared; the frequency control module adjusts the charging speed of the second capacitor according to the first dithering current so as to change the switching frequency of the frequency dithering signal.

Optionally, the feedback processing module includes: a first error amplifier, a first input end of the first error amplifier receiving the fourth reference voltage, a second input end of the first error amplifier receiving the first sampling signal; the second resistor and the third resistor are sequentially connected between the output end of the first error amplifier and the ground, and the connection node of the second resistor and the third resistor outputs the third reference voltage.

Optionally, the feedback processing module includes: a first error amplifier, a first input end of the first error amplifier receiving the fourth reference voltage, a second input end of the first error amplifier receiving the first sampling signal; the fourth resistor, the second resistor and the third resistor are sequentially connected between the output end of the first error amplifier and the ground, and a connection node of the second resistor and the third resistor outputs the third reference voltage; a voltage follower including an operational amplifier, a transistor, and a fifth resistor, an intermediate node of the fourth resistor and the second resistor being connected to a first input of the operational amplifier, a second input of the operational amplifier being connected to an intermediate node of the transistor and the fifth resistor, the voltage follower converting a voltage at the intermediate node of the fourth resistor and the second resistor to a follow current; and a current mirror connected to the voltage follower for mirroring the follower current to a third reference current.

Optionally, the frequency control module is configured to generate a periodic frequency control signal with a fixed frequency, and the frequency control module includes: the first end of the second capacitor receives a third reference current and is connected with the first end of the first switch tube, and the second end of the second capacitor is grounded; the second end of the first switch tube is grounded, and the control end of the first switch tube receives a pulse signal; the edge generating module receives the frequency control signal and generates the pulse signal according to the jump edge of the frequency control signal; the first input end of the third comparator receives the first reference voltage, the second input end of the third comparator is connected with the first end of the second capacitor, the output end of the third comparator outputs the frequency control signal, and the third comparator enables the frequency control signal to generate a jump edge when the voltage on the second capacitor is larger than the first reference voltage.

Optionally, the frequency control module is configured to generate a frequency jitter signal with a switching frequency that is based on the center frequency jitter, and the frequency control module includes: the first end of the second capacitor receives the first dithering current and the third reference current representing the center frequency, and is connected with the first end of the first switch tube, and the second end of the second capacitor is grounded; the second end of the first switch tube is grounded, and the control end of the first switch tube receives a pulse signal; the edge generating module receives the frequency dithering signal and generates the pulse signal according to the jump edge of the frequency dithering signal; the first input end of the third comparator receives the first reference voltage, the second input end of the third comparator is connected with the first end of the second capacitor, the output end of the third comparator outputs the frequency jitter signal, and the third comparator enables the frequency jitter signal to generate a jump edge when the voltage on the second capacitor is larger than the first reference voltage.

Optionally, the control circuit of the switching power supply further includes: and the oscillation module generates a periodic reference clock signal and comprises an oscillator.

Optionally, the driving module includes: the setting end of the RS trigger is connected with the frequency control module and used for receiving the frequency control signal or the frequency dithering signal, the resetting end of the RS trigger is connected with the peak current dithering control module and used for receiving the peak current dithering signal, and the output end of the RS trigger outputs the switch control signal comprising a conducting signal and a switching-off signal; and the driving unit is used for enhancing the switch control signal to control the on and off of the power tube of the switch power supply.

Optionally, the control circuit of the switching power supply further includes: a power supply module for providing a power supply voltage to the control circuit; and the reference voltage generation module is used for generating the first reference voltage, the second reference voltage and the fourth reference voltage.

Optionally, the first dithering current, the second dithering current and the third dithering current are periodic step currents, and the number of switching cycles contained in each step of the first dithering current, the second dithering current and the third dithering current is the same.

According to another aspect of the present invention, there is provided a switching power supply, including: the power conversion circuit is used for converting alternating current input voltage into direct current output voltage and comprises a primary winding, a secondary winding and an auxiliary winding; the voltage acquisition circuit divides the voltage of the auxiliary winding and outputs feedback voltage; and the control circuit.

Optionally, the power conversion circuit is any one selected from the following topologies: a floating-type Buck-Boost topology, a field-type Buck-Boost topology, a floating-type Buck topology, a field-type Buck topology, a Boost topology, and a flyback topology.

According to another aspect of the present invention, there is provided a control method of a switching power supply, including: detecting a feedback voltage representing the output voltage and obtaining demagnetization time of the switching power supply; receiving the demagnetizing time and the third dithering current, converting the current signal into a voltage signal according to the demagnetizing time, comparing the voltage signal with a second reference voltage, and outputting a sampling control signal; receiving the sampling control signal, sampling the feedback voltage according to the sampling control signal to obtain a first sampling signal, and dividing the fourth reference voltage and an error amplification signal of the first sampling signal to generate a third reference voltage representing the peak current of the load state; generating a peak current dithering signal according to the third reference voltage, a second sampling signal representing the primary inductor current and a second dithering current; and controlling the turn-off of a power tube of the switching power supply according to the peak current jitter signal.

Optionally, the third dithering current is opposite to the dithering direction of the second dithering current, and the control method further includes: and adjusting the slope of the voltage signal in the demagnetizing time according to the third dithering current to adjust the sampling time of the feedback voltage, and fixing the time interval between the sampling time and the demagnetizing ending time.

Optionally, the control method of the switching power supply further includes: and generating a frequency control signal with fixed frequency according to the first reference voltage, and controlling the conduction of a power tube of the switching power supply according to the frequency control signal with fixed frequency.

Optionally, the control method of the switching power supply further includes: generating a third reference current according to the first sampling signal and a fourth reference voltage, wherein the third reference current represents a center frequency; generating a frequency dithering signal according to a first reference voltage, the third reference current and the first dithering current; and controlling the conduction of a power tube of the switching power supply according to the frequency dithering signal, wherein the dithering directions of the first dithering current and the second dithering current are opposite.

According to the switching power supply, the control circuit and the control method thereof, provided by the embodiment of the application, the peak current dithering signal is generated through the third reference voltage representing the peak current of the load state, the second sampling signal representing the primary inductor current and the second dithering current, so that the influence of the second dithering current is superposed on the peak current of the load state, and the peak current dithering signal dithering near the peak current of the load state is generated, so that the electromagnetic compatibility of the switching capacitor is enhanced. The jitter of the peak current causes the demagnetization time to follow the change, so that the sampling time of the output voltage needs to be adjusted.

Furthermore, the application detects the demagnetizing time through the demagnetizing detection module and adjusts the sampling time through the sampling control module. The sampling control module adjusts the sampling time through a third dithering current with the dithering direction opposite to the second dithering current, so that the sampling time changes along with the change of the peak current, and the time interval between the sampling time and the demagnetization ending time is fixed. And when the peak current is increased, the sampling time is adjusted to be backward, and when the peak current is reduced, the sampling time is adjusted to be forward, so that the time interval from the sampling time to the demagnetizing finishing time is the same in each switching period. Therefore, the sampling time of the output voltage changes along with the jitter of the peak current, so that the sampling precision is improved, and the ripple wave of the output voltage is small.

Furthermore, the third dithering current can be obtained by superposing a plurality of fourth dithering currents, so that the sum of the amplitudes of the fourth dithering currents is the same as the amplitude of the third dithering current, and the sampling precision and the electromagnetic compatibility are improved.

Furthermore, the application increases frequency jitter and peak current jitter which are opposite to each other, so that the output power of the switching power supply is constant on the basis of improving the EMI of the switching power supply, and the output ripple wave caused by jitter is avoided. Furthermore, the application adjusts the sampling time of the feedback voltage under the condition of introducing peak current jitter and frequency jitter, so as to ensure the control precision on the basis of improving the EMI of the switching power supply, so that the sampling precision is high, the ripple wave of the output voltage is small, and the output power is constant. Thereby achieving the beneficial effects of normal operation of the switching power supply and delaying the aging of the switching power supply and the load.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a schematic diagram showing a configuration of a switching power supply and a control circuit thereof according to a first embodiment of the present application.

Fig. 2 is a schematic structural diagram of a switching power supply and a control circuit thereof according to a second embodiment of the present application.

Fig. 3 shows a schematic diagram of frequency and peak current jitter of a control circuit of a switching power supply according to an embodiment of the present application.

Fig. 4 is a schematic diagram illustrating corresponding sampling moments at different peak currents in a control circuit of a switching power supply according to an embodiment of the present application.

Fig. 5a shows a schematic diagram of a sampling control module in a control circuit of a switching power supply according to a first embodiment of the present application.

Fig. 5b shows a schematic diagram of a sampling control module in a control circuit of a switching power supply according to a second embodiment of the present application.

Fig. 6a is a schematic diagram of a jitter current generation module in a control circuit of a switching power supply according to an embodiment of the present application.

Fig. 6b is a schematic waveform diagram illustrating generation of a dither current by the dither current generating module in the control circuit of the switching power supply according to an embodiment of the present application.

Fig. 7 shows a schematic diagram of a feedback processing module in a control circuit of a switching power supply according to a first embodiment of the present application.

Fig. 8 is a schematic diagram of a feedback processing module in a control circuit of a switching power supply according to a second embodiment of the present application.

Fig. 9 is a schematic diagram showing a frequency dithering module in a control circuit of a switching power supply according to a first embodiment of the present application.

Fig. 10 is a schematic diagram of a frequency dithering module in a control circuit of a switching power supply according to a second embodiment of the present application.

Fig. 11a shows a schematic diagram of a peak current jitter control module of a control circuit of a switching power supply according to an embodiment of the present application.

Fig. 11b shows a schematic waveform diagram of each signal in a peak current jitter control module of a control circuit of a switching power supply according to an embodiment of the present application.

Fig. 12 is a schematic waveform diagram of signals of a sampling control module and a peak current jitter control module in a control circuit of a switching power supply according to an embodiment of the present application during operation.

Fig. 13a shows a schematic diagram of a part of waveforms of a control circuit of a switching power supply according to the prior art, and fig. 13b shows a schematic diagram of a part of waveforms of a control circuit of a switching power supply according to an embodiment of the present application.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.

Fig. 1 shows a schematic structural diagram of a switching power supply and a control circuit thereof according to an embodiment of the present application. Fig. 2 is a schematic structural diagram of a switching power supply and a control circuit thereof according to a second embodiment of the present application.

As shown in fig. 1 and 2, a switching power supply 100 of the present application will be described by taking a primary side controlled switching power supply as an example. The switching power supply 100 includes a rectifying circuit 110, a power conversion circuit 120, a voltage acquisition circuit 130, and a control circuit 140.

The rectifying circuit 110 includes a rectifying bridge, an input capacitor Cin, and an ac power source. The rectifier bridge comprises diodes D1 to D4. The two inputs of the rectifier bridge receive an ac input voltage Vac from an ac power source. The input capacitor Cin is connected between the two output terminals of the rectifier bridge, thereby providing a dc input voltage.

The power conversion circuit 120 includes a transformer T1, a freewheeling diode D0, an output capacitor Co, a power transistor M0, and a current sampling resistor R3. The transformer T1 includes a primary winding Np, a secondary winding Ns, and an auxiliary winding Naux. The primary winding Np of the transformer T1, the power tube M0 and the current sampling resistor R3 are sequentially connected in series between the high potential end of the input capacitor Cin and the ground. The auxiliary winding Naux of the transformer T1 is connected to a voltage acquisition circuit 130. On the secondary side of the transformer T1, a flywheel diode D0 and an output capacitor Co are connected in series across the secondary winding Ns of the transformer T1. An anode of the freewheel diode D0 is connected to a homonymous terminal of the secondary winding Ns, and a cathode of the freewheel diode D0 is connected to one terminal of the output capacitor Co. An output voltage Vo is generated across the output capacitor Co to supply power to the load. The power conversion circuit 120 is any one selected from the following topologies: a floating-type Buck-Boost topology, a field-type Buck-Boost topology, a floating-type Buck topology, a field-type Buck topology, a Boost topology, and a flyback topology.

The voltage acquisition circuit 130 includes a voltage dividing network composed of a resistor R01 and a resistor R02. The intermediate node between the resistor R01 and the resistor R02 obtains a feedback voltage that characterizes the output voltage Vo of the switching power supply 100.

During operation of the switching power supply 100, the control circuit 140 outputs a driving signal to control on and off of the power transistor M0. During the conduction period of the power tube M0, the primary side inductance stores electric energy, and the secondary side is powered by the capacitor. During the off period of the power tube M0, the transformer T1 transfers energy to the secondary side through the forward conduction of the freewheeling diode D0 to supply power to the load.

The control circuit 140 includes a demagnetization detection module 141, a sampling control module 143, a power supply module 144, a reference voltage generation module 145, a frequency control module 147, a peak current dithering control module 148, a driving module 149, an oscillation module 151, a dithering current generation module 152, and a feedback module 154. The ports of the control circuit 140 include a supply terminal VCC, a feedback terminal FB, a ground terminal GND, a DRIVE terminal DRIVE, and a sampling terminal CS.

The demagnetization detection module 141 is connected to an intermediate node of the voltage dividing network of the voltage acquisition circuit 130 via a feedback terminal FB to receive the feedback voltage, detects the feedback voltage representing the output voltage, obtains a demagnetization time TD of the switching power supply, and makes the sampling control module 143 operate at a demagnetization starting time. The sampling control module 143 receives the demagnetizing time TD and the third dithering current Ij3, converts the current signal into a voltage signal V1 according to the demagnetizing time TD, compares the voltage signal V1 with the second reference voltage Vref2, and outputs the sampling control signal CTRL1. The feedback module 154 receives the sampling control signal CTRL1, samples the feedback voltage according to the sampling control signal CTRL1 to obtain a first sampling signal Vsa, and divides the fourth reference voltage Vref4 and the error amplified signal of the first sampling signal Vsa to generate a third reference voltage Vref3 representing the peak current of the load state. The feedback module 154 specifically includes a switch module 142 and a feedback processing module 146, and the sampling control module 143 is connected between the demagnetization detecting module 141 and the switch module 142. The switch module is connected between the feedback terminal FB and the feedback processing module 146, and is turned on according to the sampling control signal CTRL1, so that the feedback processing module 146 is communicated with the feedback terminal FB to sample the feedback voltage, and outputs a first sampling signal Vsa. The feedback processing module 146 obtains the first sampling signal Vsa at the time when the switching module 142 is turned on, and generates a third reference voltage Vref3 representing the peak current of the load state according to the first sampling signal Vsa and the fourth reference voltage Vref 4.

Further, the sampling control module 143 outputs the sampling control signal CTRL1 after the first time TD1 has elapsed from the demagnetization start time, and the time interval from the time point of outputting the sampling control signal CTRL1 to the demagnetization end time point is the second time TD2. The feedback module 154 starts sampling the feedback voltage at a sampling time, which is then approximately the time of generation of the sampling control signal CTRL 1. The third dithering current Ij3 received by the sampling control module 143 is opposite to the dithering direction of the second dithering current Ij2, and adjusts the slope of the voltage signal in the demagnetizing time according to the third dithering current Ij3 to adjust the sampling time of the feedback voltage, so that the time interval TD2 between the sampling time and the demagnetizing end time is fixed.

The peak current dithering control module 148 generates a peak current dithering signal according to the third reference voltage Vref3 generated by the feedback module 154, the second sampling signal VCS indicative of the primary inductor current, and the second dithering current Ij 2. The driving module 149 controls the turn-off of the power tube M0 of the switching power supply according to the peak current dithering signal. The driving module 149 includes an RS flip-flop U1 and a driving unit 153. The peak current jitter control module 148 is connected to the feedback processing module 146, the sampling terminal CS and the RS flip-flop U1, and obtains a second sampling signal VCS from the sampling terminal CS, where the second sampling signal VCS characterizes the magnitude of the primary inductor current. The peak current jitter control module 148 generates a peak current jitter signal according to the third reference voltage Vref3, the second jitter current Ij2 and the second sampling signal VCS, and controls the reset terminal R of the RS flip-flop U1. The frequency control module 147 is connected to the RS flip-flop U1, and generates a frequency control signal or a frequency jitter signal according to the first reference voltage Vref1, so as to control the set terminal S of the RS flip-flop U1. The driving unit 153 is connected to the output terminal Q of the RS flip-flop U1 and the control terminal of the power tube M0, and controls the power tube M0 to be turned off according to the peak current dithering signal, and controls the power tube M0 to be turned on according to the frequency control signal or the frequency dithering signal. In some embodiments, the power supply module 144 is connected with the auxiliary winding Naux via a power supply terminal VCC to receive a power supply voltage and provide the power supply voltage VDD to other modules in the control circuit 140. The reference voltage generating module 145 is configured to generate a plurality of reference voltages, such as a first reference voltage Vref1, a second reference voltage Vref2, and a fourth reference voltage Vref4. The driving unit 153 is configured to increase the driving capability of the switch control signal output by the RS flip-flop U1, and further drive the power transistor M0. The oscillation module 151 is configured to generate a periodic reference clock signal CLK, and the dithering current generation module 152 is configured to generate a plurality of dithering currents according to the reference clock signal CLK.

Further, in fig. 1, the frequency control module 147 is configured to generate a frequency control signal with a fixed frequency according to the first reference voltage Vref 1. The driving module 149 controls the conduction of the power tube M0 of the switching power supply according to the frequency control signal of the fixed frequency. The jitter current generation module 152 is configured to generate a second jitter current Ij2 and a third jitter current Ij3 according to the reference clock signal CLK.

In order to improve electromagnetic compatibility of the switching power supply 100, a peak current dithering strategy is adopted in the first embodiment of fig. 1, so that the peak current I is dithered around the peak current Ic of the load state, and the range of the peak current dithering is ic±Δi1. Accordingly, the peak current dithering control module 148 generates a peak current dithering signal based on the second sampling signal VCS, the second dithering current Ij2, and a third reference voltage Vref3, the third reference voltage Vref3 being indicative of the peak current Ic of the load state, the second dithering current Ij2 being configured to deviate the peak current dithering signal from the peak current Ic of the load state by a certain amount. When the peak current shakes, the electric energy stored in the primary inductor of the power tube M0 also fluctuates during the conduction period, and accordingly the demagnetization time TD can shake. In order to prevent the output voltage represented by the sampled first sampling signal Vsa from changing, the sampling timing needs to be adjusted so as to match the jitter of the peak current. At this time, a second reference voltage Vref2 may be set, and the capacitor C1 is used in the sampling control module 143 to store and release electric energy, and then the electric energy is compared with the second reference voltage Vref2, so as to control the sampling time. For example, the capacitor C1 is discharged from the demagnetization starting time by using the third dithering current Ij3 and the second reference current Iref2, and the voltage signal is the voltage on the capacitor C1. When the capacitor C1 discharges to a voltage signal that is smaller than the second reference voltage Vref2, the sampling control signal CTRL1 is output to turn on the switching module 142, and sampling of the first sampling signal Vsa is started. The sampling control module 143 further charges the capacitor C1 with the first reference current Iref1 after the demagnetization is completed, so that the voltage signal is raised, and the capacitor C1 is discharged again in the next demagnetization time, thus the cycle is performed. The time at which the feedback processing module 146 starts sampling the first sampling signal Vsa is regarded as a sampling time, which is approximately the same time as the output time of the sampling control signal CTRL1 and the on time of the switching module 142. The sampling control module 143 also adjusts the slope of the voltage signal during the demagnetizing time and the discharging speed of the capacitor C1 according to the third dithering current Ij3 to adjust the sampling time. The third dither current Ij3 is opposite to the dither direction of the second dither current Ij2, so that the sampling time can be matched to the dither of the peak current. The specific relationship between the sampling instant and the peak current jitter is presented in fig. 4-5.

Therefore, the control circuit of the switching power supply of the first embodiment of the present invention improves the electromagnetic compatibility of the switching power supply due to the introduction of peak current jitter. Meanwhile, the sampling time of the feedback voltage is matched with the jitter of the peak current, so that the accuracy of the sampled feedback voltage is improved, namely the sampling precision is improved, and meanwhile, the ripple wave of the output voltage can be reduced.

Further, the control circuit 140 may cause a change in the output power p_o for a few periods of a short time in the case of increasing the peak current jitter alone, which may cause a ripple of the output voltage or the output current of the switching power supply 100, and thus may generate a surge voltage or current, thereby causing malfunction of the electrical device or accelerating degradation of the device. The control circuit 140 of the present invention can thus also add frequency jitter in reverse while increasing peak current jitter to counteract the variation in output power, i.e. the second embodiment.

In fig. 2, the jitter current generation module 152 is configured to generate a first jitter current Ij1, a second jitter current Ij2, and a third jitter current Ij3 according to the reference clock signal CLK. The peak current dithering control module 148 still generates a peak current dithering signal based on the first sampling signal Vsa, the second dithering current Ij2, and the second sampling signal VCS. The feedback processing module 146 is connected to the frequency control module 147, and is further configured to generate a third reference current Iref3 according to the fourth reference voltage Vref4 and the first sampling signal Vsa, and provide the third reference current Iref3 to the frequency control module 147, where the third reference current Iref3 characterizes the center frequency. The frequency control module 147 generates a frequency dithering signal according to the third reference current Iref3, the first dithering current Ij1 and the first reference voltage Vref1, and the driving module 149 controls the on of the power transistor M0 of the switching power supply according to the frequency dithering signal. The first dither current Ij1 and the second dither current Ij2 have opposite dither directions, so that the influence on the output power can be mutually offset. Of course, the demagnetization detecting module 141, the switching module 142, and the sampling control module 143 are the same as those of the first embodiment, i.e., the sampling timing is still matched with the jitter of the peak current. That is, this embodiment adds a frequency jitter opposite to the peak current jitter on the basis of the embodiment of fig. 1.

The control circuit 140 of the present embodiment can counteract the variation of the output power by adding the peak current jitter in the opposite direction while adding the frequency jitter. This is because the control circuit 140 of the switching power supply enables the switching power supply to achieve a constant power output by controlling the peak current of the primary inductor and the switching frequency. The output power of the switching power supply, i.e., p_o=1/2l_p×i 2×f×η, is expressed by a formula. Where p_o is the output power, l_p is the inductance of the primary winding Np of the transformer T1, I is the peak current of the primary winding Np, F is the switching frequency of the switching control signal provided by the switching power supply control circuit 140, and η is the conversion efficiency of the switching power supply control circuit 140.

As can be seen from the above equation, the control circuit 140 may cause the output power p_o to change within a few periods of a short time when the frequency jitter (F change) or the peak current jitter (I change) is increased alone, which may cause the output voltage or the output current of the switching power supply 100 to change ripple, and thus may generate surge voltage or current, thereby causing the electrical device to malfunction or accelerating the device to age. While the control circuit 140 of this embodiment increases the frequency jitter, the peak current jitter is added reversely, and the double jitter counteracts the variation of the output power, so as to stabilize the output power and reduce the ripple of the output voltage. Meanwhile, the sampling precision is improved, and good electromagnetic compatibility of the switching power supply is guaranteed.

In combination with fig. 2 and 3, in the primary-side controlled switching power supply, the switching frequency jitter is increased, so that the switching frequency F is not at a fixed frequency point, but positive and negative jitter around the central frequency Fc point, and the frequency jitter range is fc±Δf1. The peak current jitter is increased while the frequency jitter control is increased. The peak current I is subjected to positive and negative jitter around the peak current Ic in the load state, and the range of the peak current jitter is Ic + -delta I1. Illustratively, the switching frequency F produces positive and negative jitter around the center frequency Fc, and each jitter step contains 1 or more switching cycles. Further, at each dithering of the frequency, the peak current is simultaneously dithered in opposite directions on the basis of the peak current Ic of the load state, i.e. the corresponding peak current decreases as the frequency increases.

In fig. 3, the relationships among Fc, Δf1, ic, Δi1 are as follows: Δf1=m×fc, Δi1=n×ic, m/n=k. m and n are frequency jitter proportion and peak current jitter proportion respectively, k is the ratio of the frequency jitter proportion and the peak current jitter proportion, k is a positive integer greater than 1, fc represents the center frequency, and Ic represents the peak current in the load state. In order to keep the output power constant, according to the output power expression, typically k is 2. That is, in the embodiment of fig. 2, when the switching frequency F is increased by m×fc from the center frequency Fc, the control peak current I is correspondingly decreased by n×ic from the peak current Ic of the load state; and when the switching frequency F is reduced by m×fc from the center frequency Fc, the control peak current I is correspondingly increased by n×ic from the peak current Ic of the load state. By adjusting the peak current and frequency in fig. 3, the output power is stabilized and the output ripple is reduced.

In the application of the primary side feedback control switch power supply, the voltage division value (feedback voltage) of the resistor on the auxiliary winding of the transformer T1 is sampled in the demagnetizing time TD of the auxiliary winding to represent the output load state, so that the peak current and the switching frequency of the switch power supply are feedback controlled based on the load state. Therefore, on the basis of increasing frequency jitter and peak current jitter, in order to ensure the control accuracy of the switching power supply, the sampling time of the feedback voltage needs to be adjusted along with the peak current jitter.

As shown in fig. 4, the demagnetization time TD of the secondary winding of the switching power supply 100 includes a first time TD1 and a second time TD2, and the first time TD1 represents a time interval between the start of demagnetization and the sampling time, that is, a time period from the start of demagnetization to the time at which the sampling control signal CTRL1 is output. And the second time TD2 represents a time interval from the start of the sampling time to the end of the demagnetization, i.e., a time interval from the output of the sampling control signal CTRL1 to the end of the demagnetization. The sampling instant is located at the end instant of the first time TD 1.

When the peak current I increases by the jitter, the peak current Ic in the load state becomes a peak current jitter value ic+n×ic. That is, when the peak current is inversely dithered to match the negative jitter m×fc of the frequency and n×ic is increased, the demagnetization time TD of the secondary winding becomes longer by n×td. Therefore, in order to prevent the output voltage represented by the sampled feedback voltage from changing, it is necessary to shift the original sampling time SAMPLE1 (a×td) by n×td backward, and the adjusted sampling time is SAMPLE2 (a×td+n×td). The time intervals from the sampling time before and after adjustment to the demagnetization end time are the same, and are the second time TD2. That is, the feedback voltage sampled at the sampling time SAMPLE2 after the peak current jitter is increased and the feedback voltage sampled at the sampling time SAMPLE1 when the peak current jitter is not increased are the same voltage value, so that deviation of the signal value at the sampling time caused by demagnetization time change caused by the peak current jitter is avoided, and undesired output ripple caused by deviation of the sampling time is avoided. Where a is the percentage of the sampling instant at the TD time; n is the ratio of peak current jitter.

Of course, when the frequency is increased by m×fc from the center frequency Fc, the peak current will be correspondingly reduced by n×ic from the peak current Ic in the load state, and the corresponding demagnetizing time will be reduced by n×td, and at this time, the sampling time needs to be shifted by n×td, i.e., a×td-n×td, from the corresponding SAMPLE1 (a×td).

In summary, when the peak current I increases by n×ic from the peak current Ic in the load state, the demagnetization time TD is correspondingly prolonged by n×td, and the sampling time is adjusted to be shifted by n×td; when the peak current is reduced by n×ic from the peak current in the load state, the demagnetization time TD is correspondingly shortened by n×td, and the adjustment sampling time is shifted forward by n×td, ic representing the peak current in the load state, TD representing the demagnetization time, and n being a positive number.

Fig. 5a shows a schematic diagram of a sampling control module in a control circuit of a switching power supply according to an embodiment of the present application. Fig. 5b shows a schematic diagram of a sampling control module in a control circuit of a switching power supply according to a second embodiment of the present application.

As shown in fig. 5a and 5b, the sampling control module 143 includes a first capacitor C1 and a first comparator COMP1. The first capacitor C1 is connected between the inverting input terminal of the first comparator COMP1 and the reference ground, the non-inverting input terminal of the first comparator COMP1 receives the second reference voltage Vrer2, and the output terminal of the first comparator COMP1 outputs the sampling control signal CTRL1. One end of the first capacitor C1 connected to the first comparator COMP1 is called a first end, and one end grounded is called a second end. A current source generating a first reference current Iref1 is connected between the power supply terminal VDD and the first terminal of the first capacitor C1; a current source generating a second reference current Iref2 is connected in parallel between the first end of the first capacitor C1 and the reference ground, and the first end of the first capacitor C1 also receives a third dither current Ij3. The first reference current Iref1 is provided after the end of the demagnetization time TD, and the second reference current Iref2 and the third dither current Ij3 are provided during the demagnetization time TD. The switch module 142 includes, for example, a first switch S1, where the first switch S1 is connected between the feedback terminal FB and the feedback processing module 146, and a control terminal of the first switch S1 is also connected to an output terminal of the first comparator COMP1, and is turned on according to the sampling control signal CTRL1 to enable the feedback processing module 146 to sample the feedback voltage to obtain a first sampling signal Vsa.

In fig. 5a, the current source generating the third dither current Ij3 is one, and the third dither current Ij3 is generated by the separate current source. In fig. 5b, the plurality of current sources generating the third dithering current Ij3 are connected in parallel, a plurality of parallel currents Ijn are generated, and a plurality of parallel currents Ijn form the third dithering current Ij3. The third dithering current source is adjusted to be connected with the dithering current sources in parallel, so that the sum of the current amplitudes generated by the dithering current sources is the same as the third dithering current amplitude generated by the third dithering current source, and the sampling precision and the electromagnetic compatibility are improved. The current source in fig. 5a and 5b that generates the third dither current is equivalent to the current mirror that outputs the dither current in fig. 6 a.

Referring to fig. 1,2 and 5 a-5 b, the sampling control module 143 generates a sampling control signal CTRL1 according to the demagnetizing time TD, the third dithering current Ij3, the first reference current Iref1, the second reference current Iref2 and the second reference voltage Vref2, and controls the switching module 142 to be turned on. The sampling control module 143 discharges the first capacitor C1 from the demagnetization starting time through the second reference current Iref2 and the third dithering current Ij3, and the voltage signal is the voltage on the first capacitor C1. And according to the third dithering current Ij3, the slope of the voltage signal in the demagnetizing time and the discharging speed of the first capacitor C1 are adjusted, so as to adjust the sampling time. The sampling control module 143 generates the sampling control signal CTRL1 when the voltage signal is lower than the second reference voltage Vref2. After demagnetization is finished, the first capacitor C1 is charged through the first reference current Iref1, so that the voltage signal is raised. That is, after the voltage V1 (or the voltage signal V1) on the first capacitor C1 is released, or after the demagnetizing time TD is ended, the first capacitor C1 is charged by the first reference current Iref1, so that the voltage V1 on the first capacitor C1 starts to rise and gradually exceeds the second reference voltage Vref2. The voltage on the first capacitor C1 is released, for example, to a voltage of 0. Thus, the first capacitor C1 is discharged at the beginning of each demagnetizing time, the sampling control signal CTRL1 is generated when the voltage signal begins to be lower than the second reference voltage Vref2, and the charge on the first capacitor C1 begins to be charged after the charge on the first capacitor C1 is released, so that the cycle is performed.

The sampling control module 143 also adjusts the slope of the voltage signal during the demagnetizing time according to the third dithering current Ij3 to adjust the sampling time. Specifically, when the peak current I increases from the peak current Ic in the load state, the demagnetizing time TD increases, the third dither current Ij3 decreases, the absolute value of the slope of the voltage signal in the demagnetizing time decreases, and the sampling time moves backward; when the peak current I decreases from the peak current Ic in the load state, the demagnetizing time TD decreases, the third dither current Ij3 increases, the absolute value of the slope of the voltage signal during the demagnetizing time increases, and the sampling time advances. Thus, the present embodiment controls the slope of the change of the voltage V1 on the first capacitor C1, i.e. controls the discharging speed of the first capacitor C1, by introducing the third dithering current Ij3 opposite to the dithering direction of the second dithering current Ij2, so as to control the generation timing of the sampling control signal CTRL1, i.e. control the sampling timing, so that the adjustment of the sampling timing matches the dithering of the peak current. The sampling precision of the feedback voltage is improved, the ripple wave of the output voltage is reduced, the sampling precision is high, and the accuracy is high.

Fig. 6a is a schematic diagram of a jitter current generation module in a control circuit of a switching power supply according to an embodiment of the present application. Fig. 6b is a schematic waveform diagram illustrating generation of a dither current by the dither current generating module in the control circuit of the switching power supply according to an embodiment of the present application.

As shown in fig. 6a, the dithering current generation module 152 includes a signal division module 1521, a signal inversion module 1522, a control signal generation module 1523, a current dithering module 1524, and a current mirror module 1525.

In fig. 1 and 2, the oscillation module 151 is configured to generate a periodic reference clock signal CLK, and the oscillation module 151 is, for example, an oscillator. The frequency dividing module 1521 is connected to the oscillating module 151, and is configured to divide the received reference clock signal CLK to obtain a plurality of divided signals. For example, the received reference clock signal CLK is divided by two into a first divided signal CLKA, a second divided signal CLKB, a third divided signal CLKC, and a fourth divided signal CLKD in sequence. The frequency dividing module 1521 includes a plurality of D flip-flops sequentially connected in series, 5D flip-flops being shown in fig. 6a, which is not limited thereto in practice. The D flip-flops 1,2, 3, 4, and 5 are sequentially connected in series, and the D flip-flop 1 is connected to the oscillation module 151 to receive the reference clock signal CLK. The reference clock signal CLK is divided into the first divided signal CLKA after passing through the D flip-flop 1 and the D flip-flop 2. The first divided signal CLKA is divided by two into a second divided signal CLKB after passing through the D flip-flop 3. The second divided signal CLKB is divided by two into a third divided signal CLKC after passing through the D flip-flop 4. The third divided signal CLKC is divided into a fourth divided signal CLKD after passing through the D flip-flop 5.

The signal inverting module 1522 is connected to the frequency dividing module 1521, and is configured to perform inverting processing on the plurality of frequency dividing signals, and generate inverted signals of the plurality of frequency dividing signals correspondingly. For example, the first divided signal CLKA, the second divided signal CLKB, the third divided signal CLKC, and the fourth divided signal CLKD are respectively inverted to obtain a first inverted signal XCLKA, a second inverted signal XCLKB, a third inverted signal XCLKC, and a fourth inverted signal XCLKD. The signal inverting module 1522 includes a plurality of inverters, for example, an inverter 1, an inverter 2, an inverter 3, and an inverter 4, where the inverter 1 is connected to the output terminal of the D flip-flop 2, and inverts the first frequency-divided signal CLKA to obtain a first inverted signal XCLKA. The inverter 2 is connected to the output terminal of the D flip-flop 3, and inverts the second divided signal CLKB to obtain a second inverted signal XCLKB. The inverter 3 is connected to the output terminal of the D flip-flop 4, and inverts the third divided signal CLKC to obtain a third inverted signal XCLKC. The inverter 4 is connected to the output terminal of the D flip-flop 5, and inverts the fourth divided signal CLKD to obtain a fourth inverted signal XCLKD.

The control signal generating module 1523 is connected to the frequency dividing module 1521 and the signal inverting module 1522, and generates N control signals according to the plurality of frequency dividing signals and the plurality of inverting signals. For example, a control signal is generated according to each frequency division signal and an opposite phase signal corresponding to the frequency division signal, and at any moment, the control signal is one of the frequency division signal and the opposite phase signal. The control signal generation module 1523 includes, for example, a transmission gate 1, a transmission gate 2, a transmission gate 3, a transmission gate 4, a transmission gate 5, and a transmission gate 6. The input terminals of the transmission gate 1 and the transmission gate 2 receive the first divided signal CLKA and the first inverted signal XCLKA, respectively, the control terminals of the transmission gate 1 and the transmission gate 2 receive the fourth divided signal CLKD and the fourth inverted signal XCLKD, respectively, and the output terminals of the transmission gate 1 and the transmission gate 2 are connected to output the first control signal a. When the fourth divided signal CLKD is at a high level, the first control signal a is the first divided signal CLKA; when the fourth divided signal CLKD is at a low level, the first control signal a is the first inverted signal XCLKA. The input terminals of the transmission gate 3 and the transmission gate 4 respectively receive the second divided signal CLKB and the second inverted signal XCLKB, the control terminals of the transmission gate 3 and the transmission gate 4 respectively receive the fourth divided signal CLKD and the fourth inverted signal XCLKD, and the output terminals of the transmission gate 3 and the transmission gate 4 are connected to output the second control signal B. When the fourth divided signal CLKD is at a high level, the second control signal B is the second divided signal CLKB; when the fourth divided signal CLKD is at a low level, the second control signal B is the second inverted signal XCLKB. The input terminals of the transmission gate 5 and the transmission gate 6 receive the third divided signal CLKC and the third inverse signal XCLKC, respectively, the control terminals of the transmission gate 5 and the transmission gate 6 receive the fourth divided signal CLKD and the fourth inverse signal XCLKD, respectively, and the output terminals of the transmission gate 5 and the transmission gate 6 are connected to output the third control signal C. When the fourth divided signal CLKD is at a high level, the third control signal C is the third divided signal CLKC; when the fourth divided signal CLKD is at a low level, the third control signal C is a third inverse signal XCLKC.

The current dithering module 1524 is connected to the control signal generating module 1523, and includes a plurality of current sources and control switches respectively connected in series with each current source, where the plurality of control switches are respectively controlled by a plurality of control signals in a one-to-one correspondence manner, and each current source generates a current with a different amplitude when being turned on. The current dithering module 1524 controls the N current sources to have 2N combined conduction modes according to the N control signals, so as to generate 2N currents with different magnitudes (current magnitudes), and forms a reference dithering current including 2N steps by the 2N currents with different magnitudes, where N is a natural number greater than or equal to 1. In this embodiment, the current dithering module 1524 includes, for example, three current sources, three control switches and a transistor, namely, a current source A1, a current source A2, a current source A3, a control switch S1, a control switch S2, a control switch S3 and a transistor M1, wherein the three current sources are connected in parallel and then connected in series with the transistor M1. The current paths (control switch S1, control switch S2, control switch S3) between the current sources A1, A2, A3 and the transistor M1 are controlled by the first control signal a, the second control signal B and the third control signal C, respectively. When the corresponding control switch is turned on by the control signal, a current path between the current source and the transistor M1 is turned on, and the current source supplies current to the transistor M1. Then, taking the current that can be provided by the current source A1, the current source A2 and the current source A3 as 1I, 2I and 4I, respectively as an example, I is the reference current, that is, the magnitude of the current that can be provided by the current source A1, the current source A2 and the current source A3 is sequentially multiplied. The current source A1, the current source A2 and the current source A3 can have 2N combined conduction modes, so that 8 kinds of currents with different magnitudes can be generated, namely 0, 1I, 2I, 3I, 4I, 5I, 6I and 7I, and the reference dithering currents with 2N steps are combined.

The current mirror module 1525 is connected to the current dithering module 1524, and mirrors the reference dithering current into a plurality of dithering currents, wherein in fig. 1, the current mirror module 1525 mirrors the reference dithering current into a second dithering current Ij2 and a third dithering current Ij3, and in fig. 2, the current mirror module 1525 mirrors the reference dithering current into a second dithering current Ij2, a third dithering current Ij3, and a first dithering current Ij1. The current mirror module 1525 includes a plurality of current mirror branches, and the corresponding current mirror branches mirror the reference dither current according to a mirror ratio and generate a dither current having the same dither direction as the reference dither current. Or the corresponding current mirror leg connects in series with a current source at the output node of the dither current to produce a dither current that dithers in a direction opposite to the reference dither current. The current mirror module 1525 shown in fig. 6a may for example comprise three current mirror branches, a first current mirror branch comprising a transistor M3 and a transistor M4, a second current mirror branch comprising a transistor M5 and a current source A4, and a third current mirror branch comprising a transistor M2. The gate of the transistor M3 is connected to the gate and drain of the transistor M1, and the sources of the transistors M1 and M3 are grounded. The current mirror ratio of transistor M1 and transistor M3 is 1:1. the drain and gate of the transistor M4 are connected to the drain of the transistor M3, and the gate and source of the transistor M2 are connected to the gate and source of the transistor M4, respectively. The reference dither current Ij0 is provided by the branch where the transistor M4 is located, the third dither current Ij3 is provided by the drain of the transistor M2, and the current mirror ratio of the transistor M4 to the transistor M2 is 1: n such that the third dither current Ij3 may be n times the reference dither current Ij 0. The transistors M1 and M3 are transistors of a first type, and the transistors M4 and M2 are transistors of a second type. The transistors M1 and M3 are, for example, NMOS, and the transistors M4 and M2 are, for example, PMOS. The third dither current Ij3 is identical to the dither direction of the reference dither current Ij 0. The gate and source of transistor M5 are connected to the gate and source of transistor M4, respectively, and the drain of transistor M5 is grounded via current source A4, with current source A4 providing a current of 7I. The second dither current Ij2 is provided by the drain of transistor M5, and the current mirror ratio of transistor M4 to transistor M5 is 1: n such that the second dither current Ij2 may be n times the reference dither current. The transistor M2 is a first type of transistor, for example NMOS, and the transistors M4 and M5 are for example PMOS. The current source A4 is present such that the second dither current Ij2 is dithered in the opposite direction to the reference dither current Ij0, such that the dither directions of the second and third dither currents Ij2, ij3 are opposite.

The current mirror module 1525 may include, for example, four current mirror branches, a first current mirror branch including a transistor M3 and a transistor M4, a second mirror branch including a transistor M5 and a current source A4, a third mirror branch including a transistor M2, and a fourth mirror branch including a transistor M6. The gate and source of the transistor M6 are connected to the gate and source of the transistor M4, respectively. The first dither current Ij1 is provided by the drain of transistor M6, and the current mirror ratio of transistor M4 to transistor M6 is 1: m, so that the first dither current Ij1 may be m times the reference dither current Ij0, m+.n. The transistor M6 is a second type of transistor, the transistors M1, M2, and M3 are NMOS, for example, and the transistors M4 and M6 are PMOS, for example. The first dither current Ij1 and the reference dither current Ij0 and the third dither current Ij3 have the same dither direction and different magnitudes. The current mirror module 1525 of the dither current generating module 152 of fig. 1 includes a first current mirror leg, a second current mirror leg, and a third current mirror leg. The current mirror module 1525 of the dither current generating module 152 in fig. 2 includes a first current mirror branch, a second current mirror branch, a third current mirror branch, and a fourth current mirror branch. Of course, in other embodiments, more current mirror branches may be added, which is not limited herein. For example, corresponding to fig. 5b, a plurality of current mirror branches for generating the fourth dithering current may be added, and the sum of the magnitudes of the plurality of fourth dithering currents is equal to the magnitude of the third dithering current by adjusting the mirror ratio.

As shown in fig. 6b, the reference clock signal CLK is divided by two to obtain a first divided signal CLKA, which is a periodic clock signal, the first divided signal CLKA is divided by two to obtain a second divided signal CLKB, the second divided signal CLKB is divided by two to obtain a third divided signal CLKC, and the third divided signal CLKC is divided by two to obtain a fourth divided signal CLKD. The period of the four divided signals increases in sequence. The inverted signal of the fourth divided signal CLKD is the fourth inverted signal XCLKD. The fourth inversion signal XCLKD is first high level and then low level in one period, and during the high level period, the first control signal a, the second control signal B and the third control signal C are inversion signals of the first frequency division signal CLKA, the second frequency division signal CLKB and the third frequency division signal CLKC, respectively; during the low level, the first, second and third control signals a, B and C are the first, second and third divided signals CLKA, CLKB and CLKC, respectively.

And controlling the corresponding control switches S1-S3 to be turned on or turned off according to the level states of the first control signal A, the second control signal B and the third control signal C, correspondingly obtaining a reference dithering current signal Ij0 which sequentially decreases from 7I to 0 and sequentially increases from 0 to 7I, wherein the third dithering current Ij3 is the same as the reference dithering current signal Ij 0. And the second dithering current Ij2 and the third dithering current Ij3 are opposite in dithering direction and same in amplitude. The first dithering current Ij1 and the second dithering current Ij2 have opposite dithering directions and different magnitudes.

Referring to fig. 1 and fig. 7, the feedback processing module 146 of the present embodiment is connected to the switch module 142 and samples the feedback voltage to obtain the first sampling signal Vsa when the switch module 142 is turned on. The feedback processing module 146 is further connected to the peak current dithering control module 148 to generate a third reference voltage Vref3 indicative of the peak current of the load state based on the first sampling signal Vsa. Illustratively, as shown in fig. 7, the feedback processing module 146 includes, for example, an error amplifier, an inverting input terminal of the error amplifier receives the first sampling signal Vsa, a non-inverting input terminal of the error amplifier receives the fourth reference voltage Vref4, and an error amplified signal between the first sampling signal output by the output terminal of the error amplifier and the reference voltage characterizes the peak current of the load state. Illustratively, the feedback processing module 146 further includes, for example, a resistor divider network and a capacitor, the resistor divider network includes a resistor R2 and a resistor R3 connected in series between the output terminal of the error amplifier and the ground, the capacitor is connected between a connection node between the resistor R2 and the resistor R3 and the ground, and the connection node between the resistor R2 and the resistor R3 outputs a third reference voltage Vref3 indicative of the peak current of the load state.

Referring to fig. 2 and 8, the feedback processing module 146 of the present embodiment is connected to the switch module 142 and samples the feedback voltage to obtain the first sampling signal Vsa when the switch module 142 is turned on. The feedback processing module 146 is further connected to the peak current jitter control module 148 and the frequency control module 147 to generate a third reference voltage Vref3 indicative of the peak current of the load state and a third reference current Iref3 indicative of the center frequency according to the fourth reference voltage Vref4 and the first sampling signal Vsa. Illustratively, as shown in fig. 8, the feedback processing module 146 includes, for example, an error amplifier having an inverting input terminal receiving the first sampling signal Vsa and a non-inverting input terminal receiving the fourth reference voltage Vref4. The feedback processing module 146 further includes a resistor divider network including a resistor R4, a resistor R2, and a resistor R3 connected in series between the output terminal of the error amplifier and the ground terminal, and a connection node between the resistor R2 and the resistor R3 outputs a third reference voltage Vref3 indicative of the peak current of the load state, and the third reference voltage Vref3 is provided to the peak current jitter control module 148. Further, the feedback processing module 146 also includes a voltage follower and a current mirror. The voltage follower comprises an operational amplifier U2, a transistor N1 and a resistor R5, wherein the output end of the operational amplifier U2 is connected with the control end of the transistor N1, the reverse input end of the operational amplifier U2 is connected to the intermediate node of the transistor N1 and the resistor R5, and the positive input end of the operational amplifier U2 is connected to the intermediate node of the resistor R4 and the resistor R2. The structure of the voltage follower is a general structure and is not described in detail here. The output of the voltage follower is connected to a current mirror consisting of a transistor P1 and a transistor P2, the voltage follower converts the voltage of the intermediate node of the resistor R4 and the resistor R2 into a following current, which is mirrored by the current mirror (output from P2) as a third reference current Iref3, the third reference current Iref3 characterizing the center frequency. The feedback processing module 146 provides the third reference voltage Vref3 to the peak current dithering control module 148 and the third reference current Iref3 to the frequency control module 147.

Referring to fig. 1 and 9, the frequency control module 147 of the present embodiment receives the first reference voltage Vref1 provided by the reference voltage generating module 145, and generates a frequency control signal with a fixed frequency according to the first reference voltage Vref1 and the internal third reference current Iref 3.

Further, as shown in fig. 9, the frequency control module 147 includes a second capacitor C2, a third comparator COMP3, and an integral clearing unit. The second capacitor C2 is connected between the inverting input terminal of the third comparator COMP3 and the ground, and one end of the second capacitor C2 connected to the third comparator COMP3 is called a first end. A current source generating a third reference current Iref3 is connected between the supply terminal VDD and the first terminal of the second capacitor C2 to provide the third reference current Iref3 to the second capacitor C2, and the second terminal of the second capacitor C2 is grounded. In some embodiments, the third reference current Iref3 may also characterize the center frequency. The positive input terminal of the third comparator COMP3 receives the first reference voltage Vref1 output by the reference voltage generating module 145, and the output terminal of the third comparator COMP3 outputs the frequency control signal Fo. At the beginning of each switching period, a third reference current Iref3 with a fixed current value is adopted to charge the second capacitor C2, and when the voltage V2 on the second capacitor C2 is greater than the first reference voltage Vref1, the level state of the output end of the third comparator COMP3 is inverted, so that the frequency control signal generates a jump edge. Further, the second comparator COMP2 is a PWM comparator, and when the voltage V2 of the second capacitor C2 reaches the voltage value of the first reference voltage Vref1, the output frequency control signal Fo is inverted from a high level to a low level.

Further, the integral zero clearing unit comprises an edge generating module and a transistor Q1, the transistor Q1 is connected in parallel with two ends of the capacitor C2, a control end of the transistor Q1 is connected with an edge control module, and an input end of the edge control module is connected to an output end of the comparator COMP 3. When the frequency control signal Fo output by the comparator COMP3 is turned from high level to low level, the edge generating module generates a high level pulse signal, so that the transistor Q1 is turned on, and the charge stored on the capacitor C2 is cleared.

And when the voltage V2 of the second capacitor C2 reaches the voltage value of the first reference voltage Vref1, the charges stored on the capacitor C2 are cleared, and the frequency control signal Fo with fixed frequency is output in a circulating mode.

Referring to fig. 2 and 10, the frequency control module 147 of the present embodiment is connected to the feedback processing module 146 to receive the third reference current Iref3 representing the center frequency, and generate the frequency dithering signal Fo according to the third reference current Iref3, the first dithering current Ij1 and the first reference voltage Vref 1.

Further, as shown in fig. 10, the frequency control module 147 includes a second capacitor C2, a third comparator COMP3, and an integral clearing unit. The second capacitor C2 is connected before the inverting input terminal of the third comparator COMP3 and the ground, and the end of the second capacitor C2 connected to the third comparator COMP3 is called the first end. The first terminal of the second capacitor C2 receives the first dither current Ij1. The first end of the second capacitor C1 is further connected to the third reference current Iref3 provided by the feedback processing module 146, and the second end of the second capacitor C2 is grounded. The positive input terminal of the third comparator COMP3 receives the first reference voltage Vref1 output by the reference voltage generating module 145, and the output terminal of the third comparator COMP3 outputs the frequency jitter signal Fo. In each switching cycle, the second capacitor C2 is charged together with the third reference current Iref3 having a fixed current value and the first dither current Ij1 having a variable current value. When the voltage V2 on the second capacitor C2 is greater than the first reference voltage Vref1, the third comparator COMP3 turns the level state of the output terminal, so that the frequency jitter signal Fo generates a jump edge. Further, the third comparator COMP2 is a PWM comparator, and when the voltage V2 on the second capacitor C2 is greater than the first reference voltage Vref1, the output frequency jitter signal Fo is inverted from a high level to a low level. That is, the frequency control module 147 charges the second capacitor C2 through the third reference current Iref3 and the first dithering current Ij1 in each switching period, and when the terminal voltage of the second capacitor C2 is greater than the first reference voltage Vref1, the frequency dithering signal Fo is inverted, and clears the terminal voltage of the second capacitor C2 when the frequency dithering signal Fo is inverted. The frequency control module 147 also adjusts the charging speed of the second capacitor C2 according to the first dithering current Ij1 to change the switching frequency of the frequency dithering signal Fo.

Further, the integral zero clearing unit comprises an edge generating module and a transistor Q1, the transistor Q1 is connected in parallel with two ends of the capacitor C2, a control end of the transistor Q1 is connected with an edge control module, and an input end of the edge control module is connected to an output end of the comparator COMP 3. When the frequency jitter signal Fo output by the comparator COMP3 is turned from high level to low level, the edge generating module generates a high level pulse signal, so that the transistor Q1 is turned on, and the charge stored on the capacitor C2 is cleared. The next period starts to charge and integrate the second capacitor C2 again, and when the voltage V2 of the second capacitor C2 reaches the voltage value of the first reference voltage Vref1, the charges stored on the capacitor C2 are cleared, and the cycle is sequentially performed.

Further, the first dither current Ij1 is, for example, a periodic step current. The first dither current Ij1 may be implemented, for example, by a digital circuit, by controlling several switches to be turned on or off to obtain a step current, each step of the dither current being controlled, for example, by 8 switches. The first dither current Ij1 may also be generated by the dither current generating module 152 shown in fig. 6 a. Further, the third comparator COMP2 is a PWM comparator, and further generates the frequency dithering signal Fo with dithering by superimposing the first dithering current Ij1 on the third reference current Iref3 and comparing with the first reference voltage Vref 1. The dithering directions of the first dithering current Ij1 and the second dithering current Ij2 are opposite. So that the frequency-varying frequency dither signal Fo can be output.

Further, the first jitter current Ij1, the second jitter current Ij2 and the third jitter current Ij3 are all periodic step currents, and the number of switching cycles included in each step of the first jitter current Ij1, the second jitter current Ij2 and the third jitter current Ij3 is the same.

Fig. 11a shows a schematic diagram of a peak current jitter control module of a control circuit of a switching power supply according to an embodiment of the present application. Fig. 11b shows a schematic waveform diagram of each signal in a peak current jitter control module of a control circuit of a switching power supply according to an embodiment of the present application.

Referring to fig. 1, 2 and 11 a-11 b, the peak current dithering control module 148 is coupled to the feedback processing module 146 and receives a third reference voltage Vref3 indicative of the peak current of the load condition, and generates a peak current dithering signal Io based on the third reference voltage Vref3, the second dithering current Ij2 and the second sampling signal VCS.

Further, as shown in fig. 11a, the peak current jitter control module 148 includes a resistor R1 and a second comparator COMP2. The positive input terminal of the second comparator COMP2 is connected to the first terminal of the resistor R1, and the second terminal of the resistor R1 is connected to the feedback processing module 146, so as to receive the third reference voltage Vref3 of the peak current signal representing the load state. An inverting input terminal of the second comparator COMP2 samples the second sampling signal VCS from the sampling terminal CS of the control circuit 140. The positive input of the second comparator COMP2 also receives a second dither current, which superimposes the effect of the second dither current Ij2 on the positive input of the second comparator COMP2 via the resistor R1. The second comparator COMP2 compares the magnitudes of the second sampling signal VCS and (Vref 3+ ij2×r1), and outputs the peak current jitter signal Io from the output terminal. As shown in fig. 11b, the second jitter current Ij2 is a step current, the voltage (Vref 3+ij2×r1) at the positive input terminal of the second comparator COMP2 is continuously changed, and when the voltage of the second sampling signal VCS is greater than Vref3+ij2×r1, the level state of the output terminal of the second comparator COMP2 is inverted, generating a high level pulse, and the peak current jitter signal Io is formed by a plurality of high level pulses. The second dither current Ij12 is, for example, a periodic step current. The second dithering current Ij2 may be implemented, for example, by a digital circuit, by controlling several switches to be turned on or off to obtain a step current, each step of the dithering current being controlled, for example, by 8 switches. Further, the second dithering current Ij2 is opposite to the first dithering current Ij1 in dithering direction, the dithering period is the same, and the amplitude of each step is different. Further, the second comparator COMP2 is an amplitude comparator, and further generates a peak current jitter signal Io with jitter by superimposing the second jitter current Ij2 on the peak current in the load state and comparing the second jitter current Ij2 with the second sampling signal VCS.

The S end of the RS flip-flop U1 is connected to the frequency control module 147 to receive the frequency control signal or the frequency jitter signal Fo, and the R end of the RS flip-flop U1 is connected to the peak current jitter control module 148 to receive the peak current jitter signal Io, so as to generate a conducting signal for controlling the power tube M0 to be conducted according to the frequency control signal or the frequency jitter signal Fo, and generate a shutoff signal for controlling the power tube M0 to be turned off according to the peak current jitter signal Io. The output end of the RS flip-flop U1 outputs a switch control signal including an on signal and an off signal to the control end of the power tube M0.

As shown in fig. 12, ij2 represents a second dither current, ij3 represents a third dither current, VCS represents a second sampling signal, TD represents a demagnetizing time, V1 represents a voltage across the first capacitor C1, or also referred to as a voltage signal V1, vref2 represents a second reference voltage Vref2, and CTRL1 represents a sampling control signal. Further, the third dither current Ij3 and the second dither current Ij2 have opposite dither directions, the same dither period, and different magnitudes of steps, for example.

Referring to fig. 1 to 12, the second dither current Ij2 is reduced by n×i based on the original current, for example, and the third dither current Ij3 is increased by n×i based on the original current, and the peak current dither signal is reduced, so that the peak value of the second sampling signal VCS is reduced and the demagnetizing time TD is shortened. The sampling control module 143 starts discharging the first capacitor C1 through the second reference current Iref2 and the third dither current Ij3 at the demagnetization starting time. At this time, the voltage signal V1 gradually decreases until the voltage V1 on the first capacitor C1 decreases to be lower than the second reference voltage Vref2, and the level state of the output terminal of the first comparator COMP1 is inverted, so as to output the sampling control signal CTRL1 of the high level pulse. The time elapsed at this time is the first time TD1. The slope of the voltage change of the voltage V1 on the first capacitor C1 is (iref2+ij3)/C1, i.e. the absolute value of the slope of the voltage signal during the demagnetizing time is the ratio ((iref2+ij3)/C1) of the sum of the second reference current iref2 and the third dithering current ij3 (iref2+ij3) to the capacitance of the first capacitor. The larger Ij3, the larger the absolute value of the slope of the voltage V1 in the demagnetizing time, the faster the capacitor discharges, and the shorter the first time TD1. Therefore, the TD1 is shortened as compared with the starting TD1. The sampling instants are relatively shifted forward so that the time interval from the start of the sampling instant to the end of the demagnetization is constant or fixed, i.e. TD2 is the same as when the peak current is not reduced. After the first comparator COMP1 outputs the sampling control signal CTRL1 of the high level pulse, the first capacitor C1 continues to discharge until the charges are completely released or the demagnetizing time TD is over, at this time, the sampling control module 143 starts to charge the first capacitor C1 by the first reference current Iref1, and the voltage V1 gradually increases from zero to exceed the second reference voltage Vref2 until the charge reaches the maximum value. Accordingly, when the peak current jitter signal decreases based on the peak current of the load state, the demagnetization time decreases, and at this time, the discharge rate of the first capacitor C1 increases, the absolute value of the slope of the voltage signal V1 during the demagnetization time increases, the discharge accelerates, the first time TD1 decreases, and the second time TD2 remains unchanged.

When the second dithering current Ij2 increases n×i based on the original current, the third dithering current Ij2 decreases n×i based on the original current, and the corresponding peak current dithering signal increases, so that the peak value of the second sampling signal VCS increases and the demagnetizing time TD increases. The sampling control module 143 starts discharging the first capacitor C1 through the second reference current Iref2 and the third dither current Ij3 at the demagnetization starting time. At this time, the voltage V1 gradually decreases until the voltage V1 (or the voltage signal V1) on the first capacitor C1 decreases to be lower than the second reference voltage Vref2, and the level state of the output terminal of the first comparator COMP1 is inverted, so as to output the sampling control signal CTRL1 of the high level pulse. The time interval from the demagnetization start time to the sampling time is the first time TD1. The smaller the discharge slope of the first capacitor C1 or the change slope of the voltage signal V1 is (iref2+ij3)/C1, ij3, the smaller the absolute value of the slope of the voltage signal V1 in the demagnetizing time is, the slower the discharge is, and the longer the first time TD1 is. The TD1 is thus increased compared to the TD1 at the beginning. The sampling time is shifted relatively backward so TD2 is the same as when the peak current is not increased. After the first comparator COMP1 outputs the sampling control signal CTRL1 of the high level pulse, the first capacitor C1 continues to discharge until the charge is released to zero. At the end of the demagnetization time TD, the sampling control module 143 starts charging the first capacitor C1 with the first reference current Iref1, and the voltage V1 rises from zero until the charging reaches the maximum value. Accordingly, when the peak current jitter signal increases based on the peak current of the load state, the demagnetizing time increases, and at this time, the discharging rate of the first capacitor C1 decreases, the absolute value of the slope of the voltage signal V1 during the demagnetizing time decreases, the discharging rate slows down, and the first time TD1 increases, so that the second time TD2 remains unchanged.

The sampling instant can follow the jitter-synchronized variation of the peak current such that the time of the sampling instant from the time period TD2 of the demagnetization end instant is fixed. The sampling precision is high, and the output ripple is small.

As shown in fig. 13a, the control circuit of the prior art switching power supply only increases the frequency jitter, so that the second jitter current Ij2 and the third jitter current Ij3 remain unchanged, and the first jitter current Ij1 is a step point flow. While improving EMI, the output ripple may increase. As shown in fig. 13a, when the switching frequency F is overall forward-dithered, the ripple of the output voltage Vo increases in the same direction, and when the switching frequency F is overall reverse-dithered, the ripple of the output voltage Vo decreases in the same direction. The peak current I is not dithered, and the corresponding sampling time SAMPLE is also unchanged.

As shown in fig. 13b, the control circuit of the switching power supply according to the embodiment of the present application not only increases frequency jitter, but also introduces peak current jitter and sampling time jitter, so that the first jitter current Ij1, the second jitter current Ij2 and the third jitter current Ij3 are all step point flows. The control circuit 140 in this embodiment makes the peak current I shake reversely when the switching frequency F shakes forward, so that the output power is constant, and meanwhile, the sampling time SAMPLE moves forward along with the decrease of the peak current I, thereby ensuring the control precision; and when the whole switching frequency F is in reverse jitter, the peak current I is enabled to be in forward jitter, so that the output power is constant, meanwhile, the sampling time SAMPLE is moved backwards along with the increase of the peak current I, the control precision is ensured, and the ripple wave of the output voltage Vo is extremely small.

It should be noted that, in the present application, the first input terminal of the comparator is a non-inverting input terminal, and the second input terminal of the comparator is an inverting input terminal. In other alternative embodiments, the first input is an inverting input and the second input of the comparator is a non-inverting input.

The application also provides a control method of the switching power supply, which comprises the following steps: detecting a feedback voltage representing the output voltage and obtaining demagnetization time of the switching power supply; receiving the demagnetizing time and the third dithering current, converting the current signal into a voltage signal according to the demagnetizing time, comparing the voltage signal with a second reference voltage, and outputting a sampling control signal; receiving a sampling control signal, sampling the feedback voltage according to the sampling control signal to obtain a first sampling signal, and dividing the fourth reference voltage and an error amplification signal of the first sampling signal to generate a third reference voltage representing the peak current of the load state; generating a peak current dithering signal according to the third reference voltage, a second sampling signal representing the primary inductor current and a second dithering current; and controlling the turn-off of a power tube of the switching power supply according to the peak current jitter signal. The sampling control module controls the third dithering current to be opposite to the dithering direction of the second dithering current.

Further, the method further comprises: and adjusting the slope of the voltage signal in the demagnetizing time according to the third dithering current to adjust the sampling time of the feedback voltage, and fixing the time interval between the sampling time and the demagnetizing ending time.

Further, the method further comprises: and generating a frequency control signal with fixed frequency according to the first reference voltage, and controlling the conduction of a power tube of the switching power supply according to the frequency control signal with fixed frequency.

Further, the method further comprises: generating a third reference current according to the first sampling signal and the fourth reference voltage, wherein the third reference current represents the center frequency; generating a frequency dithering signal according to the first reference voltage, the third reference current and the first dithering current; and controlling the conduction of a power tube of the switching power supply according to the frequency dithering signal, wherein the dithering directions of the first dithering current and the second dithering current are opposite.

Embodiments of the invention are described above without exhaustive details, nor without limiting the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the following claims.

Claims

1. A control circuit for a switching power supply, comprising:

The demagnetization detection module is used for detecting the feedback voltage representing the output voltage and obtaining the demagnetization time of the switching power supply;

the sampling control module receives the demagnetizing time and the third dithering current, converts the current signal into a voltage signal according to the demagnetizing time, compares the voltage signal with a second reference voltage, and outputs a sampling control signal;

The feedback module is used for receiving the sampling control signal, sampling the feedback voltage according to the sampling control signal to obtain a first sampling signal, and dividing the fourth reference voltage and an error amplification signal of the first sampling signal to generate a third reference voltage representing the peak current of the load state;

The peak current jitter control module generates a peak current jitter signal according to the third reference voltage, a second sampling signal representing the primary inductor current and the second jitter current;

And the driving module is used for controlling the turn-off of the power tube of the switching power supply according to the peak current jitter signal.

2. The control circuit of a switching power supply according to claim 1, wherein when a peak current is increased by n×ic from a peak current of a load state, a demagnetization time is prolonged by n×td, and a sampling time at which the feedback module samples the feedback voltage is adjusted to be shifted backward by n×td; when the peak current is reduced by n×ic from the peak current in the load state, the demagnetizing time is correspondingly shortened by n×td, and the sampling time of the feedback module for sampling the feedback voltage is adjusted to advance by n×td, wherein Ic represents the peak current in the load state, TD represents the demagnetizing time, and n is a positive number.

3. The control circuit of a switching power supply according to claim 1 or 2, wherein the third dithering current received by the sampling control module has a dithering direction opposite to that of the second dithering current, and adjusts a slope of the voltage signal in a demagnetizing time according to the third dithering current to adjust a sampling time of the feedback voltage, so that a time interval between the sampling time and a demagnetizing end time is fixed.

4. A control circuit of a switching power supply according to claim 3, wherein the demagnetizing time increases and the third dither current decreases when the peak current increases from the peak current of the load state, the absolute value of the slope of the voltage signal during the demagnetizing time decreases, and the sampling timing shifts backward; when the peak current is reduced from the peak current in the load state, the demagnetizing time is reduced, the third dithering current is increased, the absolute value of the slope of the voltage signal in the demagnetizing time is increased, and the sampling time is advanced.

5. The control circuit of a switching power supply according to claim 1 or 2, wherein the sampling control module discharges a first capacitor through a second reference current and a third dither current from a demagnetization start time, the voltage signal is a voltage on the first capacitor, and the sampling control module adjusts a slope of the voltage signal during a demagnetization time and a discharge speed of the first capacitor according to the third dither current; charging a first capacitor through a first reference current after demagnetization is finished, so that the voltage signal is lifted; the sampling control module generates the sampling control signal when the voltage signal is lower than the second reference voltage.

6. The control circuit of claim 5, wherein an absolute value of a slope of the voltage signal over a demagnetization time is a ratio of a sum of the second reference current and the third dithering current to a capacitance of the first capacitor.

7. The control circuit of a switching power supply according to claim 1 or 2, wherein the sampling control module includes:

A first capacitor, a first end of which receives a first reference current, a second reference current and a third dithering current, a second end of which is grounded, the first reference current being provided after the demagnetization time is over, the second reference current and the third dithering current being provided within the demagnetization time;

the first input end of the first comparator receives the second reference voltage, the second input end of the first comparator is connected with the first end of the first capacitor, and the output end of the first comparator outputs the sampling control signal.

8. The control circuit of a switching power supply according to claim 1 or 2, wherein the sampling control module includes:

A first capacitor, a first end of which receives a first reference current, a second reference current and a plurality of fourth dithering currents, a sum of the magnitudes of the plurality of fourth dithering currents being equal to a magnitude of a third dithering current, a second end of which is grounded, the first reference current being provided after the end of the demagnetization time, the second reference current and the third dithering current being provided within the demagnetization time;

9. The control circuit of a switching power supply of claim 1, wherein the feedback module comprises:

the switch module receives the sampling control signal, controls the switch module to be conducted according to the sampling control signal so as to sample the feedback voltage, and outputs a first sampling signal;

And the feedback processing module generates a third reference voltage representing the peak current of the load state according to the first sampling signal and the fourth reference voltage.

10. The control circuit of a switching power supply of claim 1, wherein the peak current dithering control module comprises:

A first resistor;

a second comparator, a first input terminal of the second comparator receives a second dithering current and the third reference voltage of the peak current signal representing the load state via the first resistor, a second input terminal of the second comparator receives the second sampling signal, and an output terminal of the second comparator outputs the peak current dithering signal.

11. The control circuit of a switching power supply according to claim 1 or 2, wherein the control circuit further comprises a dither current generating module for generating a dither current, wherein the dither current generating module comprises:

the frequency dividing module is connected with the oscillation module and used for dividing the frequency of the received periodic clock signal to obtain a plurality of frequency dividing signals;

the signal inversion module is connected with the frequency division module and is used for performing inversion processing on a plurality of frequency division signals to generate a plurality of inversion signals;

A control signal generating module for generating N control signals according to the frequency division signals and the inversion signals;

The current dithering module comprises a plurality of current sources with different current amplitudes and control switches connected in series with each current source, and corresponding control signals control the corresponding control switches to be conducted so that the corresponding current sources output currents with corresponding amplitudes, and the current dithering module generates reference dithering currents with 2N steps, wherein N is a natural number greater than or equal to 1;

The current mirror module comprises a plurality of current mirror branches, and the corresponding current mirror branches mirror the reference dithering current according to the mirror proportion and generate dithering current with the same dithering direction as the reference dithering current; or, the corresponding current mirror leg connects in series with a current source at the output node of the dither current to generate a dither current that dithers in a direction opposite to the reference dither current.

12. The control circuit of a switching power supply of claim 9, wherein the switching module comprises:

The first switch is connected between the feedback voltage and the feedback processing module, the control end of the first switch is connected with the output end of the sampling control module, and the first switch is conducted according to the sampling control signal to sample the feedback voltage to obtain the first sampling signal.

13. The control circuit of a switching power supply according to claim 1, further comprising:

the frequency control module generates a frequency control signal with fixed frequency according to the first reference voltage, and the driving module controls the conduction of the power tube of the switching power supply according to the frequency control signal with fixed frequency.

14. The control circuit of a switching power supply of claim 1 wherein the feedback module further generates a third reference current indicative of a center frequency from the first sampled signal and a fourth reference voltage, the control circuit further comprising:

The frequency control module generates a frequency dithering signal according to a first reference voltage, the third reference current and the first dithering current, the driving module controls the conduction of a power tube of the switching power supply according to the frequency dithering signal,

The first dithering current is opposite to the dithering direction of the second dithering current.

15. The control circuit of a switching power supply according to claim 14, wherein when the switching frequency is increased by m x Fc from the center frequency, the control peak current is decreased by n x Ic from the peak current of the load state; when the switching frequency is reduced by m×fc from the center frequency, the peak current is controlled to be increased by n×ic from the peak current in the load state, where m/n=k, m, n are the frequency jitter ratio and the peak current jitter ratio, respectively, k is the ratio of the frequency jitter ratio and the peak current jitter ratio, and k is a positive number greater than 1, fc represents the center frequency, and Ic represents the peak current in the load state.

16. The control circuit of a switching power supply of claim 15 wherein the ratio k of the frequency jitter ratio and the peak current jitter ratio is equal to 2.

17. The control circuit of a switching power supply of claim 14, wherein the frequency control module charges a second capacitor with the third reference current and the first dither current in each switching cycle, the frequency dither signal toggles when a terminal voltage of the second capacitor is greater than the first reference voltage, and clears the terminal voltage of the second capacitor when the frequency dither signal toggles; the frequency control module adjusts the charging speed of the second capacitor according to the first dithering current so as to change the switching frequency of the frequency dithering signal.

18. The control circuit of claim 13, wherein the feedback processing module comprises:

A first error amplifier, a first input end of the first error amplifier receiving the fourth reference voltage, a second input end of the first error amplifier receiving the first sampling signal;

The second resistor and the third resistor are sequentially connected between the output end of the first error amplifier and the ground, and the connection node of the second resistor and the third resistor outputs the third reference voltage.

19. The control circuit of a switching power supply of claim 14 wherein the feedback processing module comprises: a first error amplifier, a first input end of the first error amplifier receiving the fourth reference voltage, a second input end of the first error amplifier receiving the first sampling signal;

The fourth resistor, the second resistor and the third resistor are sequentially connected between the output end of the first error amplifier and the ground, and a connection node of the second resistor and the third resistor outputs the third reference voltage;

A voltage follower including an operational amplifier, a transistor, and a fifth resistor, an intermediate node of the fourth resistor and the second resistor being connected to a first input of the operational amplifier, a second input of the operational amplifier being connected to an intermediate node of the transistor and the fifth resistor, the voltage follower converting a voltage at the intermediate node of the fourth resistor and the second resistor to a follow current; and

And the current mirror is connected with the voltage follower and mirrors the following current into a third reference current.

20. The control circuit of claim 13, wherein the frequency control module is configured to generate a periodic frequency-fixed frequency control signal, the frequency control module comprising:

The first end of the second capacitor receives a third reference current and is connected with the first end of the first switch tube, and the second end of the second capacitor is grounded;

the second end of the first switch tube is grounded, and the control end of the first switch tube receives a pulse signal;

the edge generating module receives the frequency control signal and generates the pulse signal according to the jump edge of the frequency control signal; and

The first input end of the third comparator receives the first reference voltage, the second input end of the third comparator is connected with the first end of the second capacitor, the output end of the third comparator outputs the frequency control signal, and the third comparator enables the frequency control signal to generate a jump edge when the voltage on the second capacitor is larger than the first reference voltage.

21. The control circuit of the switching power supply of claim 14 wherein the frequency control module is configured to generate a frequency dithering signal having a switching frequency that is dithered based on the center frequency, the frequency control module comprising:

The first end of the second capacitor receives the first dithering current and the third reference current representing the center frequency, and is connected with the first end of the first switch tube, and the second end of the second capacitor is grounded;

The edge generating module receives the frequency dithering signal and generates the pulse signal according to the jump edge of the frequency dithering signal; and

The first input end of the third comparator receives the first reference voltage, the second input end of the third comparator is connected with the first end of the second capacitor, the output end of the third comparator outputs the frequency jitter signal, and the third comparator enables the frequency jitter signal to generate a jump edge when the voltage on the second capacitor is larger than the first reference voltage.

22. The control circuit of a switching power supply according to claim 1 or 2, further comprising:

and the oscillation module generates a periodic reference clock signal and comprises an oscillator.

23. The control circuit of a switching power supply according to claim 13 or 14, wherein the driving module includes:

the setting end of the RS trigger is connected with the frequency control module and used for receiving the frequency control signal or the frequency dithering signal, the resetting end of the RS trigger is connected with the peak current dithering control module and used for receiving the peak current dithering signal, and the output end of the RS trigger outputs the switch control signal comprising a conducting signal and a switching-off signal;

and the driving unit is used for enhancing the switch control signal to control the on and off of the power tube of the switch power supply.

24. The control circuit of a switching power supply according to claim 13 or 14, further comprising:

A power supply module for providing a power supply voltage to the control circuit;

And the reference voltage generation module is used for generating the first reference voltage, the second reference voltage and the fourth reference voltage.

25. The control circuit of a switching power supply according to claim 13 or 14, wherein the first, second and third dither currents are periodic step currents, and each step of the first, second and third dither currents contains the same number of switching cycles.

26. A switching power supply, comprising:

the power conversion circuit is used for converting alternating current input voltage into direct current output voltage and comprises a primary winding, a secondary winding and an auxiliary winding;

The voltage acquisition circuit divides the voltage of the auxiliary winding and outputs feedback voltage; and

A control circuit as claimed in any one of claims 1 to 25.

27. The switching power supply of claim 26 wherein the power conversion circuit is any one selected from the following topologies: a floating-type Buck-Boost topology, a field-type Buck-Boost topology, a floating-type Buck topology, a field-type Buck topology, a Boost topology, and a flyback topology.

28. A control method of a switching power supply, comprising:

detecting a feedback voltage representing the output voltage and obtaining demagnetization time of the switching power supply;

Receiving the demagnetizing time and the third dithering current, converting the current signal into a voltage signal according to the demagnetizing time, comparing the voltage signal with a second reference voltage, and outputting a sampling control signal;

receiving the sampling control signal, sampling the feedback voltage according to the sampling control signal to obtain a first sampling signal, and dividing the fourth reference voltage and an error amplification signal of the first sampling signal to generate a third reference voltage representing the peak current of the load state;

Generating a peak current dithering signal according to the third reference voltage, a second sampling signal representing the primary inductor current and a second dithering current;

And controlling the turn-off of a power tube of the switching power supply according to the peak current jitter signal.

29. The control method of a switching power supply according to claim 28, wherein the third dither current is opposite to the dither direction of the second dither current, the control method further comprising:

And adjusting the slope of the voltage signal in the demagnetizing time according to the third dithering current to adjust the sampling time of the feedback voltage, and fixing the time interval between the sampling time and the demagnetizing ending time.

30. The control method of a switching power supply according to claim 28, further comprising:

and generating a frequency control signal with fixed frequency according to the first reference voltage, and controlling the conduction of a power tube of the switching power supply according to the frequency control signal with fixed frequency.

31. The control method of a switching power supply according to claim 28, further comprising:

generating a third reference current according to the first sampling signal and a fourth reference voltage, wherein the third reference current represents a center frequency;

Generating a frequency dithering signal according to a first reference voltage, the third reference current and the first dithering current; and

And controlling the conduction of a power tube of the switching power supply according to the frequency dithering signal, wherein the dithering directions of the first dithering current and the second dithering current are opposite.