CN118069336A

CN118069336A - Memory device

Info

Publication number: CN118069336A
Application number: CN202211475729.5A
Authority: CN
Inventors: 尹荣镇; 李光庚; 裴丞哲; 李刚敏; 全相珉; 尹舜炳
Original assignee: American Merchant Silicon Integrated Circuit Co ltd
Current assignee: American Merchant Silicon Integrated Circuit Co ltd
Priority date: 2022-11-23
Filing date: 2022-11-23
Publication date: 2024-05-24

Abstract

The invention provides a memory device, which comprises a plurality of memory banks. Each memory bank includes a memory array and a driver circuit. The driver circuit is coupled to the memory array and is configured to operably write data to the memory array in response to a write signal. The driver circuit includes a plurality of row driver circuits each coupled to a row of memory cells. The global driver power supply circuit is coupled to the row driver circuits in the plurality of banks to provide global driver power. Each bank further includes a local driver power circuit coupled to a corresponding row driver circuit in each bank to provide a local driver power. The local driver power supply circuit comprises a first P-type multi-threshold complementary metal oxide semiconductor, is coupled with a supply power supply and a control signal, and is controlled by the control signal to provide a local multi-threshold power supply signal for the corresponding row driver circuit.

Description

Memory device

Technical Field

The present invention relates to a memory device, and more particularly, to a driver circuit capable of reducing leakage current during turn-off of the memory device.

Background

Conventional memory devices include a plurality of banks, each of which includes a memory array of a plurality of memory cells arranged for data storage. Beside each memory array, a plurality of input/output drivers are arranged for managing data write operations. The input/output drivers, also referred to as GIO drivers, are configured to receive the data write signals and convert them to a pair of differential signals to control the data write operations of the memory array. The pair of differential signals are generally denoted as GIO signal and GIOB signal.

In a conventional memory device, one global power driver is provided to power the GIO drivers in all banks. During various modes, such as precharge or active modes, the GIO driver may switch to an off mode to save power consumption if no operation request for data writing occurs. The off mode may also be understood as a standby mode. In standby mode, the global power driver remains active for other memory banks, and thus leakage current through the GIO driver may be induced.

Multi-threshold complementary metal oxide semiconductors (multi-threshold complementary metal-oxide semiconductor; MTCMOS) are known to be an effective power gating technique. By effectively using the high threshold voltage and low threshold voltage devices, leakage power consumption of the chip can be reduced and high performance of the chip can be maintained. In implementing P-type MTCMOS, the supply power VDD is converted to a multi-threshold power signal VMTH, which has a high driving load and a high voltage threshold. In contrast, an N-type MTCMOS may generate the multi-threshold power supply signal VMTL from the ground voltage VSS. The multi-threshold power signal VMTL also has a high threshold voltage and is well separated from the ground voltage VSS. The one-to-many threshold power signals VMTH and VMTL may be used to drive the GIO driver. Based on the characteristics of high threshold voltage and circuit separation, the implementation can significantly reduce leakage current in standby mode.

With the popularity of technology, the number of memory cells in the memory array is increasing, so that the global power driver bears more load when supplying power to all GIO drivers at the same time. The size of the circuit affects the sensitivity of the response of the mode switch. For example, the multi-threshold power supply signals VMTL and VMTH may deviate from the normal level in the standby mode due to accumulated current leakage in the GIO driver. When the GIO driver is re-opened from the standby mode, the GIO driver needs a longer time to be ready to run.

Disclosure of Invention

In view of the described problems, one embodiment of the present invention provides a memory device. The memory device includes a plurality of banks for storing data. Each memory device includes a memory array and a driver circuit. The memory array includes a plurality of memory cells arranged in rows and columns. The driver circuit may be coupled to the memory array and configured to operably write data to the memory array in response to a write signal. The memory device also includes a global driver power circuit coupled to the plurality of banks, configured to operably provide global driver power to the row driver circuits in all of the plurality of banks. Each bank also includes a local driver power circuit that provides local driver power for the row driver circuits in the corresponding bank. The local driver power supply includes a first multi-threshold power supply signal. The local driver power supply circuit comprises a first P-type MTCMOS coupling supply power supply and a control signal, and is controlled by the control signal to provide the first multi-threshold power supply signal to the row driver circuits in the corresponding memory banks.

In a further embodiment, the local driver power supply further comprises a first multi-threshold ground signal. The local driver power supply circuit further includes a first N-type MTCMOS coupled to a ground voltage source and a complementary control signal, the first multi-threshold ground signal being provided to the row driver circuits in the corresponding bank under control of the complementary control signal.

In a further embodiment, when the first P-type MTCMOS is turned off by the control signal, a leakage current flowing from the supply power source to the first multi-threshold power source signal is substantially zero.

In further embodiments, each row driver circuit may include an operation stage and an output stage. An operational stage is coupled to the global driver power circuit, driven by the global driver power circuit, and operable to receive and process write signals. The output stage is coupled with the operation stage and the local driver power supply circuit, is driven by the first multi-threshold power supply signal and generates a differential input/output signal according to the output of the operation stage; wherein the differential input output signals are transmitted to a corresponding row of the memory cells in the memory array.

In a further embodiment, the global driver power circuit includes a second P-type MTCMOS coupled to the supply power and the control signal, controlled by the control signal, to generate and supply a second multi-threshold power signal to the operational stage in each of the row driver circuits in each of the banks.

In a further embodiment of the memory device, a leakage current from the supply power source to the second multi-threshold power supply signal is substantially zero when the second P-type MTCMOS is turned off by the control signal.

In a further embodiment of the memory device, the global driver power supply circuit comprises an N-type MTCMOS coupled to a ground voltage source and to complementary control signals, controlled by the complementary control signals to generate and supply a second multi-threshold ground signal to the operational stage in each of the row driver circuits in each of the banks.

In a further embodiment of the memory device, the leakage current from the multi-threshold ground signal to the ground voltage source is substantially zero when the N-type MTCMOS is turned off by the complementary control signal.

In a further embodiment of the memory device, the control signal and the complementary control signal are complementary in polarity. When the control signal is triggered from a low voltage, the row driver circuit transitions from an active mode to an off mode. During the off mode, the first multi-threshold power supply signal gradually drops from a first voltage to a second voltage.

In a further embodiment of the memory device, the row driver circuit switches from the off mode to a recovery mode when the control signal drops to the low voltage. During the recovery mode, the first multi-threshold power supply signal gradually rises from the second voltage to the first voltage. During the recovery mode, the row driver circuit switches to an active mode when the first multi-threshold power supply signal reverts to the first voltage.

During the off mode, the first multi-threshold ground signal may gradually rise from the ground voltage to the bias voltage. During the recovery mode, the first multi-threshold ground signal may gradually drop from the bias voltage to the ground voltage. When the first multi-threshold ground signal returns to ground voltage, the row driver circuit will enter an active mode.

Drawings

FIG. 1 is a schematic diagram of one embodiment of a memory device;

FIG. 2 is a diagram of a second memory device according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating one of the row driver circuits of an embodiment of the present invention;

FIG. 4 is a diagram illustrating a third memory device according to an embodiment of the invention;

FIG. 5 is a second row driver circuit illustrating an embodiment of the invention;

Fig. 6 is a timing diagram of signal levels in various modes.

Reference numerals illustrate:

100 memory device

104 Driver circuit

110 Memory bank

120 Global driver power supply circuit

122 Global P-type MTCMOS

124 Global N-type MTCMOS

130 Local driver power supply circuit

P-type MTCMOS

134N-type MTCMOS

140 Memory array

142 Memory cell columns

200 Memory device

300 Row driver circuit

310 Operation level

320 Output stage

400 Memory device

500 Row driver circuit

Detailed Description

The following description is of the best contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

Multiple Threshold Complementary Metal Oxide Semiconductor (MTCMOS) is an effective power gating technique that can reduce the leakage power consumption of a chip and maintain high performance of the chip by effectively using high and low threshold voltage devices.

Fig. 1 shows a memory device 100 according to an embodiment of the invention. Memory device 100 includes a plurality of banks 110 coupled to global driver power supply circuit 120. Global driver power supply circuit 120 provides global driver power Gp to drive bank 110. Each bank 110 includes a memory array 140, driver circuitry 104, and local driver power supply circuitry 130. In fig. 1, one of the repositories 110 is shown in more detail. The driver circuits 104 in the bank 110 include a plurality of row driver circuits 300. Memory array 140 may include a plurality of memory cells arranged in rows and columns. For example, memory array 140 includes a number of memory cell rows 142 corresponding to the number of row driver circuits 300. Different portions of each driver circuit 300 are driven by the local driver power supply Lp provided by the local driver power supply circuit 130 and the global driver power supply Gp provided by the global driver power supply circuit 120, respectively. When an operation request for data writing occurs, a write command and data to be written are sent to the driver circuit 104. The row driver circuit 300 receives the corresponding row data in the driver circuit 104 and converts it into corresponding differential signals GIO and GIOB. The memory array 140 stores data in corresponding memory cell rows 142 based on the differential signals GIO and GIOB.

As shown in the embodiment of FIG. 1, global driver power circuit 120 is coupled to all banks 110 in memory device 100, and each local driver power circuit 130 is associated with only one bank 110. In practice, each row driver circuit 300 is driven by both the global driver power circuit 120 and the local driver power circuit 130, wherein different portions of the row driver circuit 300 are coupled to different driver power circuits. Because the local driver power supply circuit 130 is coupled to fewer row driver circuits 300 than the global driver power supply circuit 120, the local driver power supply circuit 130 is less loaded and may exhibit faster response in mode switching. With proper settings, the performance of the driver circuit 104 may be improved based on the coordination of the global driver power supply circuit 120 and the local driver power supply circuit 130.

Fig. 2 shows a memory device 200 according to an embodiment of the invention. Based on the structure of memory device 100, the details of memory device 200 are further described below. As with FIG. 1, memory device 200 may include a plurality of banks 110 for data storage, where each bank 110 includes a memory array 140 and driver circuitry 104 (not shown). The driver circuit 104 is coupled to the memory array 140 and configured to write data into the memory array 140 according to the write signal. One of the row driver circuits 300 in the driver circuit 104 is described in particular detail below. The local driver power supply circuit 130 of fig. 1 may include a P-type MTCMOS 132 for providing a local multi-threshold power supply signal LVMTH. In one embodiment, the P-type MTCMOS 132 may be a P-type multi-threshold complementary metal oxide semiconductor (MTCMOS) coupled to the power supply VDD2 and the control signal NOT_EN, controlled by the control signal NOT_EN, providing a local multi-threshold power signal LVMTH to the corresponding row driver circuit 300.

In fig. 2, the row driver circuit 300 includes an operation stage 310 and an output stage 320. The local driver power supply circuit 130 acts as a signal interpreter in the row driver circuit 300, including thousands of transistors, operating in accordance with known memory device control protocols. The detailed circuit design is omitted here. The embodiment of fig. 2 focuses on the respective operations of local multi-threshold power signal LVMTH and local multi-threshold ground signal LVMTL. The output stage 320 can in turn be understood as a termination circuit for directly outputting the differential signals GIO and GIOB. In one embodiment, the output stage 320 is configured to be powered by the P-type MTCMOS 132, causing the row driver circuit 300 to increase the agility of the reaction during mode switching, particularly when re-turning from standby mode.

The operation stage 310 is coupled to the global driver power circuit 120, and is driven by the global driver power Gp to operatively receive and process the write signal IO. The output stage 320 is coupled to the operation stage 310 and the local driver power circuit 130, driven by the local multi-threshold power signal LVMTH, and generates differential input-output signals GIO and GIOB based on the output of the operation stage 310. As shown in FIG. 1, the differential input-output signals GIO and GIOB are then sent into corresponding memory cell columns 142 in the corresponding memory array 140.

In the embodiment of the memory device 100, the global driver power circuit 120 includes a global P-type MTCMOS 122 coupled to a supply power VDD2 and a control signal NOT_EN, which is controlled by the control signal NOT_EN to generate and supply a global multi-threshold power signal GVMTH to the operation stage 310 of each row driver circuit 300 in each bank 110.

In a further embodiment of the memory device 100, the global driver power circuit 120 includes a global N-type MTCMOS 124 coupled to a ground voltage source VSS and a complementary control signal EN, which is controlled by the complementary control signal EN to generate a local multi-threshold ground signal LVMTL. As shown in fig. 2, the local multi-threshold ground signal LVMTL is coupled to the row driver circuit 300 in the operation stage 310 and the output stage 320, and provides a stable pull-down voltage for the row driver circuit 300 to generate high-quality differential input-output signals GIO and GIOB.

When the bank 110 enters the standby mode, the P-type MTCMOS 132 is turned off by the control signal not_en, and the row driver circuit 300 stops operating. Leakage current from supply power VDD2 through local multi-threshold power supply signal LVMTH into output stage 320 is substantially zero. Thus, the local multi-threshold power signal LVMTH required by the output stage 320 does not drop severely during standby mode, which enables the output stage 320 to obtain enough power to quickly react to various mode switches.

Similar to the P-type MTCMOS 132, the global P-type MTCMOS 122 is turned off under the control of the control signal not_en in the standby mode. The leakage current from supply power VDD2 to global multi-threshold power supply signal GVMTH is now substantially zero. Similarly, when the global N-type MTCMOS 124 is turned off by the complementary control signal EN, the leakage current flowing from the local multi-threshold ground signal LVMTL to the ground voltage source VSS is substantially zero.

Fig. 3 shows details of a row driver circuit 300 further derived based on fig. 2, in accordance with an embodiment of the present invention. The row driver circuit 300 includes an operation stage 310 and an output stage 320. The operational stage 310 includes a plurality of transistors, inverters, logic gates for processing input signals into output signals. Most of the components are powered by global multi-threshold power signal GVMTH and global multi-threshold ground signal GVMTL. In operation stage 310, connection pads A and B represent connections to global multi-threshold power signal GVMTH and multi-threshold ground signal LVMTL, respectively. The detailed functions of the operation stage 310 are based on the memory device control protocol, a detailed description is omitted herein, and are not limited to the illustrated configuration in the operation stage 310. For example, global multi-threshold power supply signal GVMTH is provided by global driver power supply circuit 120 in fig. 2, and global multi-threshold ground signal GVMTL is provided by global driver power supply circuit 120 in fig. 2.

In fig. 3, the output stage 320 outputs a pair of differential signals GIO and GIOB. The output signal GIO is output by a pair of cascode transistors P1 and N1. Transistor P1 is coupled to connection pad C and is powered by local multi-threshold power signal LVMTH. In an alternative embodiment, transistor N1 may be coupled to connection pad B and powered by global multi-threshold ground signal GVMTL. Similarly, the complementary output signal GIOB is output by a pair of cascode transistors P2 and N2. Transistor P2 is coupled to connection pad C and is powered by local multi-threshold power signal LVMTH. In an alternative embodiment, transistor N2 may be coupled to connection pad B and powered by global multi-threshold ground signal GVMTL. For example, the local multi-threshold power supply signal LVMTH is provided by the P-type MTCMOS 132 of FIG. 2, while the global multi-threshold ground signal GVMTL is provided by the global driver power supply circuit 120 of FIG. 2. The output stage 320 operates to convert the output signal from the operation stage 310 into a pair of differential signals GIO and GIOB, which are then sent to control a corresponding memory cell, such as one of the memory cell rows 142 in fig. 1.

The local driver power supply circuit 130 functions similarly to the global driver power supply circuit 120, but is coupled to fewer circuits. Thus, the local driver power supply circuit 130 is less subject to leakage current and load line capacity, and can react faster. Since the local multi-threshold power supply signal LVMTH in this embodiment is instead provided by the local driver power supply circuit 130, rather than the global driver power supply circuit 120, the output stage 320 exhibits better performance in mode switching.

Fig. 4 illustrates a memory device 400 according to an embodiment of the invention. Memory device 400 is a more detailed view derived based on memory device 100. As with fig. 2, one of the row driver circuits 300 in the driver circuit 104 is shown in particular detail. The local driver power supply circuit 130 of fig. 1 may include a P-type MTCMOS 132 for providing a local multi-threshold power supply signal LVMTH and an N-type MTCMOS 134 for providing a local multi-threshold ground signal LVMTL. In one embodiment, the P-type MTCMOS 132 is coupled to the power supply VDD2 and the control signal NOT_EN, and is controlled by the control signal NOT_EN to provide a local multi-threshold power signal LVMTH to the corresponding row driver circuit 300. The N-type MTCMOS 134 is coupled to the ground voltage VSS and the control signal EN, and provides a local multi-threshold ground signal LVMTL to the corresponding row driver circuit 300 under control of the control signal EN.

The foregoing advantages of the present invention are also applicable to embodiments of N-type MTCMOS 134. When the N-type MTCMOS134 is turned off by the control signal EN, the leakage current from the row driver circuit 300 through the N-type MTCMOS134 to ground is substantially zero.

In fig. 4, the row driver circuit 300 includes an operation stage 310 and an output stage 320. The local driver power supply circuit 130 acts as a signal interpreter in the row driver circuit 300, including thousands of transistors operating based on the memory device control protocol. Therefore, detailed circuit designs thereof are omitted herein. This embodiment focuses on the respective operations of the P-type MTCMOS 132 and the N-type MTCMOS 134. The output stage 320, also referred to as a termination circuit, may directly output differential signals GIO and GIOB. In this embodiment, the output stage 320 is configured to be powered by the P-type MTCMOS 132 and the N-type MTCMOS 134, so that the row driver circuit 300 increases the sensitivity of the reaction during mode switching, particularly when re-turning from standby mode.

The operation stage 310 is coupled to the global driver power circuit 120 and is driven by the global driver power Gp to operably receive and process the write signal IO. The output stage 320 couples the operational stage 310 and the local driver power circuit 130. The local multi-threshold power signal LVMTH and the local multi-threshold ground signal LVMTL are pull-up and pull-down voltages for the output stage 320 to generate differential signals GIO and GIOB corresponding to the outputs of the operation stage 310. The differential signals GIO and GIOB are sent into a column 142 of memory cells in a corresponding memory array 140.

In an embodiment of the memory device 100, the global driver power circuit 120 includes a P-type MTCMOS 122 coupled to a supply power VDD2 and a control signal NOT_EN, by which a global multi-threshold power signal GVMTH is generated and supplied to the operational stage 310 in each row driver circuit 300 in each bank 110.

In a further embodiment of the memory device 100, the global driver power circuit 120 includes an N-type MTCMOS 124 coupled to a ground voltage source VSS and a complementary control signal EN, controlled by the complementary control signal EN to generate a multi-threshold ground signal LVMTL to the operational stage 310 in each row driver circuit 300 in each bank 110.

As with the P-type MTCMOS 132, when the P-type MTCMOS 122 is turned off by the control signal not_en, the leakage current flowing from the supply power VDD2 to the global multi-threshold power signal GVMTH is substantially zero. Similarly, when the N-type MTCMOS 124 is turned off by the complementary control signal EN, the leakage current flowing from the global multi-threshold ground signal GVMTL to the ground voltage source VSS is substantially zero.

Fig. 5 shows a row driver circuit 500 according to an embodiment of the invention. The row driver circuit 500 includes an operation stage 310 and an output stage 320 as shown in fig. 4. The operational stage 310 includes a plurality of transistors, inverters, and logic gates for processing input signals into output signals. Most of the components are powered by global multi-threshold power signal GVMTH and global multi-threshold ground signal GVMTL. In operation stage 310, connection pads A and B represent connections to global multi-threshold power signal GVMTH and global multi-threshold ground signal GVMTL, respectively. The detailed functions of the operation stage 310 may be implemented based on a memory device control protocol, so a detailed description is omitted herein and are not limited to the configuration depicted in the operation stage 310. For example, the global multi-threshold power signal GVMTH may be provided by the P-type MTCMOS 122 in fig. 4, while the global multi-threshold ground signal GVMTL may be provided by the N-type MTCMOS 124 in fig. 4.

In fig. 5, the output stage 320 outputs a pair of differential signals GIO and GIOB. The output signal GIO is output by a pair of cascode transistors P1 and N1. Transistor P1 is coupled to connection pad C and is powered by local multi-threshold power signal LVMTH. In an alternative embodiment, transistor N1 may be coupled to connection pad D and powered by local multi-threshold ground signal LVMTL. Similarly, the complementary output signal GIOB is output by a pair of cascode transistors P2 and N2. Transistor P2 is coupled to connection pad C and is powered by local multi-threshold power signal LVMTH. In an alternative embodiment, transistor N2 may be coupled to connection pad D and powered by local multi-threshold ground signal LVMTL. For example, the local multi-threshold power signal LVMTH may be provided by the P-type MTCMOS 132 of FIG. 4 and the local multi-threshold ground signal LVMTL may be provided by the N-type MTCMOS 134 of FIG. 4. The output stage 320 converts the output signal from the operation stage 310 into a pair of differential signals GIO and GIOB, which are then sent to control corresponding memory cells, such as a row of memory cells 142 in fig. 1.

Since the local multi-threshold power supply signal LVMTH and the local multi-threshold ground signal LVMTL of the present embodiment are provided by the local driver power supply circuit 130 instead of the global driver power supply circuit 120, the output stage 320 exhibits better performance in mode switching.

Fig. 6 is a level timing chart showing signals in various modes. The control signal not_en and the complementary control signal EN are mutually complementary signals. In the present embodiment, the control signal EN/not_en ranges from 0V to 1.1V, respectively. The operation of the row driver circuit 300 may be divided into four phases, an active mode, an off mode, a resume mode, and finally back into the active mode. When the row driver circuit 300 is in an active mode, memory device access operations, such as read/write/precharge operations, may be performed. The off mode is also referred to as a standby mode, during which the row driver circuit 300 is turned off to save power. The recovery mode refers to a period of time after the row driver circuit 300 is turned back on from the off mode. The recovery mode is also referred to as an off exit mode during which a period tr is required for the power supply driver circuit to regain full functionality to drive the row driver circuit 300.

For example, when the control signal not_en is triggered from low voltage 0V, the row driver circuit 300 transitions from the active mode to the off mode. During the off mode, the current path P1 shows the voltage drop according to the P-type MTCMOS 132 in fig. 2 and 4. Wherein, due to current leakage, the local multi-threshold power supply signal LVMTH gradually drops from the first voltage 1.1V to the second voltage 0.95V during the off mode. The current path P2 shows a voltage drop caused by leakage current in the conventional power driver circuit. As can be seen from fig. 6, the current of the current path P2 decreases more severely than the current of the current path P1. In addition, the current path P2 requires tr+td time to restore the entire functions after the control signal EN/not_en turns on the row driver circuit 300. Obviously, the recovery time tr of the present embodiment is better than the recovery time required for the current path P2.

In a similar embodiment of the memory device 100, the row driver circuit 300 transitions from the off mode to the resume mode when the control signal NOT_EN is turned down to a low voltage of 0V. In the resume mode, current path P3 shows local multi-threshold ground signal LVMTL rising gradually from 0V to 0.15V. When the local multi-threshold ground signal LVMTL returns to ground voltage 0V in the recovery mode, the row driver circuit 300 transitions into the active mode. The current path P4 shows the same procedure as the conventional power driver circuit, shows a significant voltage offset due to current leakage, and requires an additional time td to recover from the off mode, thus having poor performance.

Embodiments of the present invention provide independent MTCMOS power supplies, such as local driver power supply circuits 130 in each bank 110. The local driver power supply circuit 130 may be used to provide the local driver power supply Lp in place of the global driver power supply Gp in place of the global driver power supply circuit 120. This may solve the problem of insufficient recovery time that occurs when the global driver power circuit generates the multi-threshold power signal and the multi-threshold ground signal in the off exit mode.

While the invention has been described by way of example and preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. The scope of the appended claims is, therefore, to be construed broadly, to include all such modifications and similar arrangements.

Claims

1. A memory device comprising a plurality of banks for data storage, wherein each bank comprises:

a memory array including a plurality of memory cells arranged in rows and columns; and

A driver circuit coupled to the memory array, configured to operably write data to the memory array according to a write signal;

Wherein:

The driver circuit comprises a plurality of row driver circuits, each row driver circuit being coupled to a corresponding row of the memory cells;

The memory device further includes a global driver power circuit coupled to the plurality of banks, configured to operatively provide global driver power to row driver circuits in all of the plurality of banks;

Each memory bank further includes a local driver power circuit, each providing a local driver power for the row driver circuits in the corresponding memory bank;

The local driver power supply includes a first multi-threshold power supply signal; and

The local driver power supply circuit includes a first P-type multi-threshold complementary metal oxide semiconductor (MTCMOS) coupled to a supply power supply and a control signal, the first multi-threshold power supply signal being provided to the row driver circuits in the corresponding bank under control of the control signal.

2. The memory device of claim 1, wherein:

The local driver power supply further includes a first multi-threshold ground signal; and

The local driver power supply circuit further includes a first N-type MTCMOS coupled to a ground voltage source and a complementary control signal, the first multi-threshold ground signal being provided to the row driver circuits in the corresponding bank under control of the complementary control signal.

3. The memory device of claim 1 wherein a leakage current from the supply power to the first multi-threshold power signal is substantially zero when the first P-type MTCMOS is turned off by the control signal.

4. The memory device of claim 1, wherein each of the row driver circuits comprises:

An operation stage coupled to the global driver power circuit, driven by the global driver power circuit, operable to receive and process a write signal; and

An output stage coupled to the operation stage and the local driver power circuit, driven by the first multi-threshold power signal, and generating a differential input/output signal according to an output of the operation stage;

Wherein: the differential input output signals are transmitted to a corresponding row of the memory cells in the memory array.

5. The memory device of claim 3 wherein said global driver power circuit comprises a second P-type MTCMOS coupled to said supply power and said control signals, said control signals controlling to generate and supply a second multi-threshold power signal to an operational stage in each of said row driver circuits in each of said banks.

6. The memory device of claim 5 wherein the global driver power circuit comprises an N-type MTCMOS coupled to a ground voltage source and a complementary control signal, the complementary control signal being controlled to generate and supply a second multi-threshold ground signal to the operational stage in each of the row driver circuits in each of the banks.

7. The memory device of claim 6, wherein:

the control signal and the complementary control signal are complementary in polarity;

When the control signal is triggered from a low voltage, the row driver circuit transitions from an active mode to an off mode; and

During the off mode, the first multi-threshold power supply signal gradually drops from a first voltage to a second voltage.

8. The memory device of claim 7, wherein:

when the control signal drops to the low voltage, the row driver circuit switches from the off mode to a recovery mode;

during the recovery mode, the first multi-threshold power supply signal gradually rises from the second voltage to the first voltage; and

During the recovery mode, the row driver circuit switches to the active mode when the first multi-threshold power supply signal reverts to the first voltage.

9. The memory device of claim 7, wherein during the off mode, the first multi-threshold ground signal gradually rises from a ground voltage to a bias voltage.

10. The memory device of claim 9, wherein:

During a recovery mode, the first multi-threshold ground signal gradually drops from the bias voltage to the ground voltage; and

During the recovery mode, the row driver circuit switches to the active mode when the first multi-threshold ground signal returns to the ground voltage.