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CN118053470A - Memory circuit, memory device, and electronic apparatus - Google Patents

Memory circuit, memory device, and electronic apparatus Download PDF

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Publication number
CN118053470A
CN118053470A CN202211440011.2A CN202211440011A CN118053470A CN 118053470 A CN118053470 A CN 118053470A CN 202211440011 A CN202211440011 A CN 202211440011A CN 118053470 A CN118053470 A CN 118053470A
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CN
China
Prior art keywords
type transistor
bit line
circuit
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211440011.2A
Other languages
Chinese (zh)
Inventor
蔡江铮
布明恩
欧阳晟
程宽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN202211440011.2A priority Critical patent/CN118053470A/en
Priority to PCT/CN2023/104499 priority patent/WO2024103779A1/en
Publication of CN118053470A publication Critical patent/CN118053470A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The application provides a storage circuit, a storage device and electronic equipment, and relates to the technical field of storage. The memory circuit comprises a plurality of memory blocks, a main input-output circuit and a global bit line. Each storage block comprises a storage array and a local input/output circuit connected with the storage array; the main input/output circuit comprises a global precharge unit for globally precharging the global bit line. The local input/output circuit comprises a local control circuit; the local control circuit is configured to: precharging the global bit line before the global precharge unit stops global precharging the global bit line; and, after the precharge is completed, a read signal from the memory array is output to the global bit line.

Description

Memory circuit, memory device, and electronic apparatus
Technical Field
The present application relates to the field of storage technologies, and in particular, to a storage circuit, a storage device, and an electronic device.
Background
In a memory circuit of a large-capacity SRAM (static random access memory ), a multi-memory block (multi bank) is generally adopted, and as shown in fig. 1, an LIO (local input output ) circuit in the multi banks is connected to an MIO (main input output ) circuit through a global bit line GBL (global bitline), so that read data in the banks is transferred to the MIO circuit through the LIO circuit. The MIO circuit may also be referred to as a global input output (global input output) circuit, i.e., GIO circuit.
As shown in fig. 1 and 2 (partial schematic diagram of fig. 1), in the conventional LIO circuit, in transmitting the read data in bank to the MIO circuit, the MIO circuit needs to perform Global Precharge (GPRE) on the global bit line GBL through the transistor M1, but the global bit line GBL has a leakage path. Therefore, in order to combat the problem of leakage in data transmission, a keeper circuit (keeper) is required in the MIO circuit in the prior art, and the data on the global bit line GBL is maintained by the keeper circuit (keeper). However, in data transmission, the transistor in the keeper circuit (keeper) and the transistor M0 in the LIO circuit are turned on at the same time, so that a certain competition relationship exists between the charge-discharge capability of the transistor in the keeper circuit (keeper) and the charge-discharge capability of the transistor M0; for example, in the case of a read 0 operation on the global bit line GBL, the discharging capability on the path of the transistor M0 needs to be greater than the charging capability on the path of the keeper to ensure that the potential on the global bit line GBL is inverted (1 to 0); that is, the design of the transistors in keeper requires matching read 0 and read 1 operations. In addition, when designing an actual circuit, under the condition of different PVT (process, voltage, temperature), it is required to ensure that the current intensity of the holding circuit (keeper) matches to meet the requirement, so that the design complexity of the holding circuit (keeper) is high, and a series of problems such as failure of a flow sheet test function are caused.
Disclosure of Invention
The application provides a memory circuit, a memory device and an electronic device, which avoid adopting a retaining circuit (keeper), and maintain the potential of a global bit line (global bit line) by performing relay precharge through an LIO circuit.
The application provides a memory circuit, which comprises a plurality of memory blocks, a main input/output circuit and a global bit line. Each memory block comprises a memory array and a local input output circuit (MIO circuit or GIO circuit) connected with the memory array; the local input/output circuit (LIO circuit) includes a local control circuit. The main input/output circuit includes a global precharge unit for globally precharging the global bit line. The local control circuit is configured to: precharging (or relay precharging) the global bit line before the global precharge unit stops global precharging the global bit line; and, after the precharge is completed, a read signal from the memory array is output to the global bit line.
In the memory circuit of the embodiment of the application, a retaining circuit (keeper) is not required to be arranged, but a local control circuit with a novel structure is arranged in the LIO circuit, and before the global precharge unit stops global precharge on the global bit line, the global bit line can be precharged based on the arrangement of the local control circuit, namely, the global bit line can be precharged by the relay global precharge unit through the local control circuit, so that the potential on the global bit line is ensured not to be overturned by leakage. The memory circuit avoids the use of a keeper circuit (keeper) to maintain the potential of the global bit line, thereby avoiding the current intensity matching design of transistors in the keeper circuit (keeper) and further reducing the design difficulty of the memory circuit.
In some possible implementations, the memory circuit includes a first voltage terminal, a second voltage terminal. The local input/output circuit further includes: a sense amplifier circuit; the sense amplifying circuit comprises a first input end, a first output end, a sense amplifying enabling end and a precharge voltage end. The main input/output circuit also comprises a latch; the global precharge unit, the latch and the local control circuit are all connected with a global bit line. The local control circuit comprises a second input end, a second output end and a local pre-charge signal end, and is connected with the first voltage end and the second voltage end. The first input is connected to the memory array and the first output is connected to the second input. The second output is connected to the global bit line. The sense amplifying circuit is configured to: under the control of signals of the sensitive amplification enabling end and the precharge voltage end, the reading signal from the storage unit received by the first input end is amplified and then output to the local control circuit through the first output end. The local control circuitry is further configured to: before the global precharge unit stops global precharge on the global bit line, outputting the potential of the first voltage end to the second output end to precharge the global bit line under the control of signals of the local precharge signal end and the second input end; and after the precharge is completed, outputting the potential of the first voltage terminal or the second voltage terminal to the global bit line through the second output terminal according to the read signal input from the second input terminal, so as to be latched into the latch.
In some possible implementations, the local control circuit includes a first inverter, a first N-type transistor, a first P-type transistor, and a second P-type transistor. The input end of the first inverter is connected with the first output end, and the output end of the first inverter is connected to the grid electrode of the first N-type transistor and the grid electrode of the second P-type transistor. The grid electrode of the first P-type transistor is connected to the local pre-charge signal end, the source electrode of the first P-type transistor is connected with the first voltage end, the drain electrode of the first P-type transistor is connected with the source electrode of the second P-type transistor, and the drain electrode of the second P-type transistor is connected to the global bit line; the source of the first N-type transistor is connected with the second voltage end, and the drain of the first N-type transistor is connected with the global bit line.
In some possible implementations, the local control circuit further includes a second inverter; the input end of the second inverter is connected with the local pre-charge signal end, and the output end of the second inverter is connected with the pre-charge voltage end so as to pre-charge the sensitive amplifying circuit through the local pre-charge signal end.
In some possible implementations, the global precharge unit includes a third P-type transistor, a global precharge signal terminal. The grid electrode of the third P-type transistor is connected with the global pre-charge signal end, the source electrode of the third P-type transistor is connected with the first voltage end, and the drain electrode of the third P-type transistor is connected with the global bit line.
In some possible implementations, the primary input-output circuit further includes a delay module. The delay module is connected with the global bit line, the sense amplification enabling end and the latch. The delay module is configured to delay the signal on the global bit line and output a control signal to the latch under the control of the signal at the sense amplification enable end so that the latch latches the signal on the global bit line and closes in advance.
In some possible implementations, the delay module includes a delay chain, a nand gate, a third inverter. The input end of the delay chain is connected with the global bit line, the output end of the delay chain is connected with the first input end of the NAND gate, and the second input end of the NAND gate is connected with the sensitive amplifying enabling end. The output end of the NAND gate is connected to the inverting control end of the latch and the input end of the third inverter; the output of the third inverter is connected to the non-inverting control terminal of the latch.
In some possible implementations, the sense amplifying circuit includes: fourth P-type transistor, fifth P-type transistor, sixth P-type transistor, seventh P-type transistor, second N-type transistor, third N-type transistor, fourth N-type transistor, fifth N-type transistor, sixth N-type transistor, first node, second node. The first input terminal includes a first amplification input terminal and a second amplification input terminal. The grid electrode of the fourth P-type transistor and the grid electrode of the sixth P-type transistor are connected to the precharge voltage terminal; the sources of the fourth P-type transistor, the fifth P-type transistor, the sixth P-type transistor and the seventh P-type transistor are all connected to the first voltage end; the drains of the fourth P-type transistor and the fifth P-type transistor are connected with the first node, and the drains of the sixth P-type transistor and the seventh P-type transistor are connected with the second node; a gate of the fifth P-type transistor is connected to the second node; a gate of the seventh P-type transistor is connected to the first node and the first node is connected to the first output terminal. The gates of the second N-type transistor and the third N-type transistor are connected to the isolation signal control end, the source electrode of the second N-type transistor is connected to the first amplifying input end, and the drain electrode of the second N-type transistor is connected to the second node. The source of the third N-type transistor is connected to the second amplifying input terminal, and the drain of the third N-type transistor is connected to the first node. The grid electrode of the fourth N-type transistor is connected with the first node, the drain electrode of the fourth N-type transistor is connected with the second node, and the source electrode of the fourth N-type transistor is connected with the drain electrode of the sixth N-type transistor. The grid electrode of the fifth N-type transistor is connected with the second node, the drain electrode of the fifth N-type transistor is connected with the first node, and the source electrode of the fifth N-type transistor is connected with the drain electrode of the sixth N-type transistor. The gate of the sixth N-type transistor is connected to the sense amplifier enable terminal, and the source of the sixth N-type transistor is connected to the second voltage terminal.
In some possible implementations, the latch includes an eighth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, a fourth inverter, a positive control terminal, and a negative control terminal. The gate of the eighth P-type transistor is connected to the inverted control terminal, the source of the eighth P-type transistor is connected to the first voltage terminal, and the drain of the eighth P-type transistor is connected to the source of the ninth P-type transistor. A gate of the ninth P-type transistor is connected to the global bit line, and a drain of the ninth P-type transistor is connected to an input terminal of the fourth inverter; the output of the fourth inverter is connected to the output of the latch. The gate of the tenth P-type transistor is connected to the non-inverting control terminal, the source of the tenth P-type transistor is connected to the first voltage terminal, and the drain of the tenth P-type transistor is connected to the source of the eleventh P-type transistor. The gate of the eleventh P-type transistor is connected to the output terminal of the fourth inverter, and the drain of the eleventh P-type transistor is connected to the input terminal of the fourth inverter. The gate of the seventh N-type transistor is connected to the global bit line, the drain of the seventh N-type transistor is connected to the input of the fourth inverter, and the source of the seventh N-type transistor is connected to the drain of the eighth N-type transistor. The gate of the eighth N-type transistor is connected to the non-inverting control terminal, and the source of the eighth N-type transistor is connected to the second voltage terminal. The gate of the ninth N-type transistor is connected to the output terminal of the fourth inverter, the drain of the ninth N-type transistor is connected to the input terminal of the fourth inverter, and the source of the ninth N-type transistor is connected to the drain of the tenth N-type transistor. The gate of the tenth N-type transistor is connected to the inversion control terminal, and the source of the tenth N-type transistor is connected to the second voltage terminal.
The embodiment of the application also provides a control method of the memory circuit, which is provided in any one of the possible implementation manners, and comprises the following steps: a precharge phase and a data read phase. Wherein, during the precharge phase, it comprises: controlling the global precharge unit to be started, and performing global precharge on the global bit line; and controls the local control circuit to precharge the global bit line before the global precharge unit is turned off. The data reading stage comprises the following steps: the local control circuit is controlled to output a read signal from the memory array to the global bit line.
The embodiment of the application also provides a storage device, which comprises a controller and a storage circuit provided in any one of the possible implementation manners, wherein the storage circuit is electrically connected with the controller.
The embodiment of the application also provides electronic equipment, which comprises a printed circuit board and a storage device provided in any one of the possible modes; the memory device is electrically connected to the printed wiring board.
Drawings
FIG. 1 is a schematic diagram of a memory circuit according to the prior art;
FIG. 2 is a partial schematic diagram of the memory circuit of FIG. 1;
FIG. 3 is a schematic diagram of a memory according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a memory circuit according to an embodiment of the present application;
FIG. 5 is a schematic circuit diagram of a memory cell according to an embodiment of the present application;
FIG. 6 is a timing signal diagram of a memory circuit according to an embodiment of the present application;
fig. 7 is a schematic diagram of a memory circuit according to an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one" means one or more, and "a plurality" means two or more. "connected," "coupled," and the like are to be construed broadly, and may be mechanically coupled or electrically coupled, for example; either directly or indirectly through intermediaries, or through communication between two elements. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. "upper", "lower", "left", "right", etc. are used merely with respect to the orientation of the components in the drawings, these directional terms are relative terms, which are used for description and clarity with respect thereto, and which may vary accordingly depending on the orientation in which the components are placed in the drawings.
An embodiment of the present application provides an electronic device including a printed circuit board (printed circuit board, PCB; may also be referred to as a circuit board) and a memory device disposed on the printed circuit board, the memory device being electrically connected to the circuit board. The storage device is provided with a storage circuit and a controller connected with the storage circuit, so that the control of the storage circuit is realized through the controller.
The present application is not limited to the arrangement form of the above-described electronic device. The electronic equipment can be electronic products such as mobile phones, tablet computers, notebooks, vehicle-mounted computers, intelligent watches, intelligent bracelets and the like.
The present application is not limited to the arrangement form of the above-described storage device. Illustratively, the memory device may include a memory device such as an SRAM, a nonvolatile memory, or the like.
A keeper circuit (keeper) is required to resist the leakage problem in data transfer compared to the memory circuits in existing memory devices. The memory device adopts a novel memory circuit, and a retaining circuit (keeper) is not required to be arranged in the memory circuit to maintain the potential on a global bit line (global bit line), so that the current intensity matching design of transistors in the retaining circuit (keeper) is avoided, and the design difficulty of the memory circuit is further reduced.
Taking a memory device as an example of SRAM, a specific configuration of the memory circuit provided by the embodiment of the present application is described below with reference to the prior art.
Referring to fig. 3, the memory circuit provided in the embodiment of the present application includes a plurality of memory blocks (banks), which is not limited to the 4 memory blocks bank0, bank1, bank2, and bank3 illustrated in fig. 3. Among them, a single bank includes a memory array formed of a plurality of memory cells C (cells), and a row decoder, a column decoder, an LIO circuit, and the like connected to the memory array. LIO circuits in multiple banks are connected to MIO circuits through global bit lines GBL.
In the memory circuit of the present application, as shown in fig. 4, a global precharge unit 101 and a latch 102 are included in an MIO circuit 100. LIO circuit 200 includes a sense amplifier circuit 201 and a local control circuit 202. The local control circuit 202, global precharge unit 101, latch 102 are all connected to a global bit line GBL.
The input terminals (In 1a, in1 b) of the sense amplifier circuit 201 are connected to the memory cells C In the memory array, and the output terminal (Out 1) is connected to the global bit line GBL through the local control circuit 202. The sense amplifier circuit 201 can read and amplify data (0 or 1) in the memory cell C. When reading data in a certain memory cell C in the memory array, the row decoder and the column decoder decode according to the received address to determine the memory cell C to be read.
When the memory circuit reads and stores the memory data, the global bit line GBL needs to be globally precharged by the global precharge unit 101 in the MIO circuit 100; then, the data in the selected memory cell C is read and amplified by the sense amplifier circuit 201 in the LIO circuit 200, and the corresponding read data is latched by the global bit line GBL output latch 102 under the control of the local control circuit 202.
In the prior art, in order to maintain a high potential on the global bit line GBL during the precharge phase, as shown with reference to fig. 1 and 2, a hold circuit (keeper) needs to be added to the MIO circuit, which causes a series of negative effects: 1. during the read 0 operation, the discharging capability of the transistor M0 on the path needs to be greater than the charging capability of the transistor in the keeper circuit (keeper) (i.e., the transistor M0 needs to compete with the transistor in keeper) to ensure that the potential on the global bit line GBL can be flipped (i.e., from 1 to 0), otherwise, the read 0 performance of the memory circuit is affected; 2. the current strength design of the transistors in the keeper circuit (keeper) requires matching read 0 and read 1 operations, and matching conditions are difficult to meet at various PVT. Therefore, in the case of a hold circuit (keeper) design, the following conditions must be met: current conditions in the read 0 scenario: icel0+ (n-1) Ileak1; current conditions for read 1 scenario: icel1+ (n-1) Ileak0. 3. Current of the holding circuit (keeper): icel0+ (n-1) Ileak1> Ikeeper > icel1+ (n-1) Ileak0. However, matching these 3 conditions under different PVT conditions is difficult, which results in difficulty in designing a memory circuit, and even failure of the test function of the tape-out test occurs because the above 3 conditions are not satisfied due to some deviation of the process. Where n represents the number of memory blocks (banks) in the memory circuit; icell0 represents the read current of the selected bank in the read 0 scene, and Ileak1 represents the leakage current in the rest of banks in the read 0 scene; icell1 represents the read current of the selected bank in the read 1 scenario; ileak0 represents leakage current in the remaining banks in the read 1 scenario.
In contrast, referring to fig. 4, in the memory circuit according to the embodiment of the present application, there is no need to provide a keeper circuit (keeper), but by providing a local control circuit 202 with a novel structure in the LIO circuit 200, before the global precharge unit 101 stops global precharge on the global bit line GBL, the global bit line GBL can be precharged (or locally precharged) by the local control circuit 202, that is, the global bit line GBL can be precharged by the global precharge unit 101 in a "relay" manner by the local control circuit 202, so as to ensure that the potential on the global bit line GBL is not pulled by leakage. The local control circuit has the charge and discharge capability in the path, and does not have a charge and discharge competition relationship with other paths, so that the current intensity matching design is not needed, and the design complexity of the memory circuit is reduced.
Of course, after the local control circuit 202 completes the relay precharge of the global bit line GBL, the local control circuit 202 outputs the corresponding high potential or low potential to the global bit line GBL according to the read data amplified by the sense amplifier circuit 201, so as to latch by the global bit line GBL output latch 102.
The local, such as local precharge, local control circuit, etc., related to the application is the connection setting, control, etc., of the inside of a single bank, while the global, such as global precharge, global precharge unit, etc., related to the application is the connection setting, control, etc., of the whole of a plurality of banks.
Illustratively, the process of locally precharging global bit line GBL after global precharge by local control circuitry 202 is described below in connection with a particular circuit arrangement of the memory circuit.
Referring to fig. 4, a first voltage terminal and a second voltage terminal are provided in the memory circuit of the present application, and the MIO circuit 100 and the LIO circuit 200 are connected to the first voltage terminal and the second voltage terminal to supply power through the first voltage terminal and the second voltage terminal as power terminals. Illustratively, the first voltage terminal may be a high-level voltage terminal Vdd, and the second voltage terminal may be a ground terminal GND, hereinafter abbreviated as: a first voltage terminal Vdd, a second voltage terminal GND; the application is not so limited.
Schematically, referring to fig. 4, the sense amplifier circuit 201 includes input terminals In1a and In1b (which may also be referred to as first input terminals), an output terminal Out1 (which may also be referred to as first output terminals), a sense amplifier enable terminal SAE, and a precharge voltage terminal LPREB. The local control circuit 202 includes an input In2 (which may also be referred to as a second input), an output Out2, and a local precharge signal terminal LPRE (local precharge).
The input terminals (In 1a, in1 b) of the sense amplifier circuit 201 are connected to bit lines (bit lines, BL) and bit bar (BLB) of the memory cells C In the memory array, and reference is made to the following description. The output Out1 of the sense amplifier circuit 201 is connected to the input In2 of the local control circuit 202, and the output Out2 of the local control circuit 202 is connected to the global bit line GBL. The sense amplifier circuit 201 is capable of amplifying the read signal from the memory cell C received by the first input terminal (In 1a, in1 b) under the control of the sense amplifier enable terminal SAE and the precharge voltage terminal LPREB, and outputting the amplified read signal to the local control circuit 202 through the first output terminal Out 1.
For the local control circuit 202 described above:
Before the global precharge unit 101 stops global precharge of the global bit line GBL (i.e., before the global precharge unit is turned off), the potential of the first voltage terminal Vdd is outputted to the second output terminal Out2 to precharge the global bit line GBL under the signal control of the local precharge signal terminal LPRE and the second input terminal In 2.
After the global precharge unit 101 stops global precharge of the global bit line GBL (i.e., after the global precharge unit is turned off), the potential of the first voltage terminal Vdd or the second voltage terminal GND is output to the global bit line GBL through the second output terminal Out2 according to the read signal input from the second input terminal In 2.
That is, before the global precharge unit 101 stops precharging the global bit line GBL, the local control circuit 202 precharges the global bit line GBL in advance to ensure that the global bit line GBL maintains a high voltage, so as to avoid the global bit line GBL from being pulled over by leakage. After the global precharge unit 101 stops precharging the global bit line GBL, the on/off between the first voltage terminal Vdd and the global bit line GBL is selectively controlled according to the read signal input by the sense amplifier circuit 201, so as to ensure that the output of the potential of the first voltage terminal Vdd or the second voltage terminal GND corresponding to the read signal (0 or 1) is latched to the latch 102, that is, the output of the potential of the first voltage terminal Vdd or the second voltage terminal GND can be directly latched to the latch 102 according to the read signal (0 or 1) through the setting of the local control circuit 202.
In addition, for a plurality of banks in the whole memory circuit, relay precharge is realized by controlling the local control circuit 202 in the operating bank (i.e. the bank performing data reading), while in the non-operating bank, the leakage compensation path between the first voltage terminal Vdd and the global bit line GBL can be cut off through the local precharge signal terminal LPRE, so that the influence of other banks on the data on the global bit line GBL in the operating bank is avoided.
The specific circuit configurations of the sense amplifier circuit 201, the local control circuit 202, the global precharge unit 101, and the latch 102 are not limited in the present application, as long as the foregoing functional conditions can be satisfied.
Illustratively, in some possible implementations, as shown in fig. 4, the local control circuit 202 may include a first inverter a1, a first N-type transistor N1, a first P-type transistor P1, and a second P-type transistor P2. The input terminal of the first inverter a1 is connected to the input terminal In2 of the local control circuit 202, and the input terminal of the first inverter a1 is connected to the first output terminal Out 1. The output terminal of the first inverter a1 is connected to the gate of the first N-type transistor N1 and the gate of the second P-type transistor P2. The gate of the first P-type transistor P1 is connected to the local precharge signal terminal LPRE, the source of the first P-type transistor P1 is connected to the first voltage terminal Vdd, the drain of the first P-type transistor N1 is connected to the source of the second P-type transistor P2, and the drain of the second P-type transistor P2 is connected to the output terminal Out2 of the local control circuit 202. The source of the first N-type transistor N1 is connected to the second voltage terminal GND, and the drain of the first N-type transistor N1 is connected to the output terminal Out2 of the local control circuit 202. The output Out2 of the local control circuit 202 is connected to the global bit line GBL.
Illustratively, in some possible implementations, as shown in fig. 4, the global precharge unit 101 may include a third P-type transistor MP3, a global precharge signal terminal GPREB. The gate of the third P-type transistor MP3 is connected to the global precharge signal terminal GPREB, the source of the third P-type transistor MP3 is connected to the first voltage terminal Vdd, and the drain of the third P-type transistor MP3 is connected to the global bit line GBL. In this case, as shown in fig. 6, in the precharge phase, the third P-type transistor MP3 is turned on under the low level control of the global precharge signal terminal GPREB, and outputs the high level of the first voltage terminal Vdd to the global bit line GBL for precharge.
For the setting of the sense amplifier circuit 201, the specific circuit configuration of the sense amplifier circuit 201 may be selected according to the circuit configuration of the memory cell C in practice, and the present application is not limited thereto. For example, in some embodiments, referring to fig. 5, in the case where the circuit structure of the memory cell C includes a Bit Line (BL) and an inverted Bit Line (BLB), the input terminals of the sense amplifying circuit 201 may be two input terminals: a first amplification input terminal In1a and a second amplification input terminal In1b, wherein the first amplification input terminal In1a may be connected to a Bit Line (BL) and the second amplification input terminal In1b may be connected to an inverted Bit Line (BLB).
The specific circuit structure of the memory cell C is not limited, and may be selected and set as needed in practice. Fig. 5 is only a schematic diagram illustrating a circuit configuration in which the memory cell C can employ 6 transistors, i.e., a 6T configuration.
In addition, as shown in fig. 4, in order to simplify the circuit, in some possible implementations, a second inverter a2 may also be provided in the local control circuit 202. The input end of the second inverter a2 is connected to the local pre-charge signal end LPRE, and the output end of the second inverter a2 is connected to the pre-charge voltage end LPREB of the sense amplifying circuit 201, so that the local pre-charge signal end LPRE can simultaneously perform pre-charge on the sense amplifying circuit 201. Of course, in some possible implementations, sense amplifier circuit 201 may be precharged by setting precharge voltage terminal LPREB alone. The following embodiments are described by taking the case where the second inverter a2 is provided in the local control circuit 202 as an example.
Illustratively, in some possible implementations, as shown in fig. 4, the sense amplifying circuit 201 may include: fourth P-type transistor MP4, fifth P-type transistor MP5, sixth P-type transistor MP6, seventh P-type transistor MP7, second N-type transistor MN2, third N-type transistor MN3, fourth N-type transistor MN4, fifth N-type transistor MN5, sixth N-type transistor MN6, first node DLB, second node DL. Wherein the potentials of the first node DLB and the second node DL are opposite to each other. The input terminal In1 of the sense amplifying circuit 201 includes a first amplifying input terminal In1a and a second amplifying input terminal In1b.
In the above-described sense amplifying circuit 201, the gate of the fourth P-type transistor MP4 and the gate of the sixth P-type transistor MP6 are both connected to the amplified pre-charge signal terminal LPREB, and the amplified pre-charge signal terminal LPREB is connected to the output terminal of the second inverter a 2. The sources of the fourth P-type transistor MP4, the fifth P-type transistor MP5, the sixth P-type transistor MP6, and the seventh P-type transistor MP7 are all connected to the first voltage terminal Vdd. The drains of the fourth P-type transistor MP4 and the fifth P-type transistor MP5 are connected to the first node DLB. The drains of the sixth P-type transistor MP6 and the seventh P-type transistor MP7 are connected to the second node DL. The gate of the fifth P-type transistor MP5 is connected to the second node DL. The gate of the seventh P-type transistor MP7 is connected to the first node DLB, and the first node DLB is connected to the first output terminal Out 1.
In the above-described sense amplifier circuit 201, the gates of the second N-type transistor MN2 and the third N-type transistor MN3 are both connected to the isolation signal control terminal S1. The source of the second N-type transistor MN2 is connected to the first amplifying input terminal In1a, and the drain of the second N-type transistor MN2 is connected to the second node DL. The source of the third N-type transistor MN3 is connected to the second amplifying input terminal In1b, and the drain of the third N-type transistor MN3 is connected to the first node DLB. In reading the signal, the second N-type transistor MN2 and the third N-type transistor MN3 are turned on by controlling the signal input from the isolation signal control terminal S1 to read the signal on the bit line BL and the bit bar line BLB In the memory cell C through the first amplification input terminal In1a and the second amplification input terminal In1 b. After the reading signal is finished, the second N-type transistor MN2 and the third N-type transistor MN3 are turned off by controlling the signal input from the isolation signal control terminal S1, so as to avoid the interference of the external signal to the sense amplifying circuit 201.
In the sense amplifier circuit 201, the gate of the fourth N-type transistor MN4 is connected to the first node DLB, the drain of the fourth N-type transistor MN4 is connected to the second node DL, and the source of the fourth N-type transistor MN4 is connected to the drain of the sixth N-type transistor MN 6. The gate of the fifth N-type transistor MN5 is connected to the second node DL, the drain of the fifth N-type transistor MN5 is connected to the first node DLB, and the source of the fifth N-type transistor MN5 is connected to the drain of the sixth N-type transistor MN 6. The gate of the sixth N-type transistor MN6 is connected to the sense amplification enable terminal SAE, and the source of the sixth N-type transistor MN6 is connected to the second voltage terminal GND.
The control process of the memory circuit in the precharge phase and the data reading phase will be described with reference to fig. 4 and 6, in combination with the pass terminals of the transistors in the above-described sense amplifier circuit 201 and local control circuit 202.
In the precharge phase, the local precharge signal terminal LPRE inputs a high level, which is inverted by the inverter a2 (i.e. the amplified precharge signal terminal LPREB is a low level), and controls the fourth P-type transistor MP4 and the sixth P-type transistor MP6 to be turned on, so as to precharge the sense amplifying circuit 201, and the first output terminal Out1 outputs a high level. After the local precharge signal terminal LPRE turns to a low potential, the first P-type transistor MP1 is turned on; the first output terminal Out1 maintains a high potential to control the second P-type transistor MP2 to be turned on, that is, the first P-type transistor MP1 and the second P-type transistor MP2 are turned on, so that the high level of the first voltage terminal Vdd is output to the global bit line GBL for precharging, and thus the relay precharge can be implemented before the global precharge unit 101 stops global precharge on the global bit line GBL.
In the data reading stage (Read 1, read 0), the isolation signal control terminal S1 controls the second N-type transistor MN2 and the third N-type transistor MN3 to be turned on, the first amplification input terminal In1a and the second amplification input terminal In1b receive the Read signal In the memory cell C, and input the Read signal to the second node DL and the first node DLB, respectively, and under the control of the sense amplifier enable terminal SAE, the sense amplifier circuit 201 amplifies the voltage difference between the second node DL and the first node DLB, and outputs the corresponding Read signal through the first output terminal Out 1.
Illustratively, during a Read0 operation (Read 0), the isolation signal control terminal S1 controls the second N-type transistor MN2 and the third N-type transistor MN3 to be turned on, the high level on the bit line BL is transferred to the second node DL, and the weak high level on the bit line BLB is transferred to the first node DLB. Under the control of a high level signal of the sense amplifier enable terminal SAE, the sixth N-type transistor MN6 is turned on, and the potential of the first node DLB is lower than that of the second node DL, so that the potential of the first node DLB is further lower and the potential of the second node DL is higher in the circuit; finally, the fifth P-type transistor MP5 and the fourth N-type transistor MN4 are turned off, and the seventh P-type transistor MP7 is turned on to output the high level of the first voltage terminal Vdd to the second node DL; the fifth N-type transistor MN5 is turned on to output the low level of the second voltage terminal GND to the first node DLB, and the first output terminal Out1 outputs the low level, i.e., outputs "0". In this case, the second input terminal In2 of the local control circuit 202 receives the low potential from the first output terminal Out1, and inverts to the high potential via the first inverter a1, and under the control of the low potential, the second P-type transistor P2 is turned off, so that the path between the first voltage terminal Vdd and the global bit line GBL is cut off (no competition exists); the first N-type transistor N1 is turned on to output the low voltage of the second voltage terminal GND to the global bit line GBL.
Illustratively, during a Read1 operation (Read 1), the isolation signal control terminal S1 controls the second N-type transistor MN2 and the third N-type transistor MN3 to be turned on, the weak high level on the bit line BL is transferred to the second node DL, and the high level on the bit line BLB is transferred to the first node DLB. Under the control of the high level signal of the sense amplifier enable terminal SAE, the sixth N-type transistor MN6 is turned on, and since the potential at the first node DLB is higher than the potential at the second node DL, the potential at the first node DLB is further higher and the potential at the second node DL is lower in the circuit, and finally the fifth N-type transistor MN5 and the seventh P-type transistor MP7 are turned off, the fourth N-type transistor MN4 is turned on to output the low level of the second voltage terminal GND to the second node DL, the fifth P-type transistor MP5 is turned on to output the high level of the first voltage terminal Vdd to the first node DLB, and the first output terminal Out1 outputs the high level, i.e., outputs "1". In this case, the input terminal In2 of the local control circuit 202 receives the high voltage from the first output terminal Out1, and is inverted to the low voltage by the first inverter a1, the first N-type transistor N1 is turned off under the control of the low voltage, the second P-type transistor P2 is turned on, and the first P-type transistor P1 is turned on under the control of the low voltage of the local precharge signal terminal LPRE, so as to output the high voltage of the first voltage terminal Vdd to the global bit line GBL.
Illustratively, in some possible implementations, as shown in fig. 4, the latch 102 may include an eighth P-type transistor MP8, a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a seventh N-type transistor MN7, an eighth N-type transistor MN8, a ninth N-type transistor MN9, a tenth N-type transistor MN10, a fourth inverter a4, a positive control terminal LAT, and a negative control terminal LATB. The signals input by the positive control terminal LAT and the negative control terminal LATB are a group of negative signals.
In the latch 102, the gate of the eighth P-type transistor MP8 is connected to the inversion control terminal LATB, the source of the eighth P-type transistor MP8 is connected to the first voltage terminal Vdd, and the drain of the eighth P-type transistor MP8 is connected to the source of the ninth P-type transistor MP 9. The gate of the ninth P-type transistor MP9 is connected to the global bit line GBL (i.e., the input of the latch 102), the drain of the ninth P-type transistor MP9 is connected to the input of the fourth inverter a4, and the output of the fourth inverter a4 is connected to the output of the latch 102. The gate of the tenth P-type transistor MP10 is connected to the non-inverting control terminal LAT, the source of the tenth P-type transistor MP10 is connected to the first voltage terminal Vdd, and the drain of the tenth P-type transistor MP10 is connected to the source of the eleventh P-type transistor MP 11. The gate of the eleventh P-type transistor MP11 is connected to the output terminal of the fourth inverter a4, and the drain of the eleventh P-type transistor MP11 is connected to the input terminal of the fourth inverter a 4. The gate of the seventh N-type transistor MN7 is connected to the global bit line GBL (i.e., the input of latch 102). The drain of the seventh N-type transistor MN7 is connected to the input terminal of the fourth inverter a 4. The source of the seventh N-type transistor MN7 is connected to the drain of the eighth N-type transistor MN 8. The gate of the eighth N-type transistor MN8 is connected to the non-inverting control terminal LAT, and the source of the eighth N-type transistor MN8 is connected to the second voltage terminal GND. The gate of the ninth N-type transistor MN9 is connected to the output terminal of the fourth inverter a4, the drain of the ninth N-type transistor MN9 is connected to the input terminal of the fourth inverter a4, and the source of the ninth N-type transistor MN9 is connected to the drain of the tenth N-type transistor MN 10. The gate of the tenth N-type transistor MN10 is connected to the inverting control terminal LATB, and the source of the tenth N-type transistor MN10 is connected to the second voltage terminal GND.
For the control of the latch 102, during the Read1 operation (Read 1), the global bit line GBL is kept at a high level, and under the control of the high level input from the normal phase control terminal LAT, the seventh N-type transistor MN7 and the eighth N-type transistor MN8 are turned on, the low level of the second voltage terminal GND is output to the input terminal of the fourth inverter a4, the high level after the inversion of the fourth inverter a4 is obtained, at the end of the Read, the eighth N-type transistor N8 and the eighth P-type transistor P8 are turned off, and the tenth P-type transistor P10 and the tenth N-type transistor N10 are turned on, thereby realizing the latch of the high level. In the Read0 operation (Read 0), the potential on the global bit line GBL is inverted from a high level to a low level, and under the control of the low level input by the inversion control terminal LATB, the eighth P-type transistor MP8 and the ninth P-type transistor MP9 are turned on, the high level of the first voltage terminal Vdd is output to the input terminal of the fourth inverter a4, the low potential inverted by the fourth inverter a4, and at the end of reading, the eighth N-type transistor N8 and the eighth P-type transistor P8 are turned off, and the tenth P-type transistor P10 and the tenth N-type transistor N10 are turned on, thereby realizing the latch of the low level.
Based on the setting of the latch 102 in the present application, the output of the potential of the first voltage terminal Vdd or the second voltage terminal GND can be directly latched to the MIO circuit 100 according to the read signal (0 or 1) under the control of the normal phase control terminal LAT and the reverse phase control terminal LATB, without forcibly rewriting the data in the latch (latch), that is, a small-sized transistor can be adopted in the local control circuit 202.
In addition, in order to simulate a real read operation path and perform an and operation with the sense amp enable SAE so that the latch 102 can be closed in advance when performing a read 0 operation, ensuring that data is normally latched, in some possible implementations, as shown in fig. 7, a delay module 103 may be provided in the MIO circuit 100, where the delay module 103 is connected to the global bit line GBL, the sense amp enable SAE, and the latch 102. The delay module 103 is configured to delay the signal on the global bit line GBL and output a control signal to the latch 102 under the control of the signal at the sense amp enable SAE, so that the latch 102 latches the signal on the global bit line GBL and closes in advance.
The specific circuit configuration of the delay module 103 is not particularly limited in the present application, as long as the foregoing functional conditions can be satisfied.
Illustratively, in some embodiments, as shown in fig. 7, the delay module 103 may include a delay chain 30, a nand gate b1, and a third inverter a3. The input terminal of the delay chain 30 is connected to the global bit line GBL, the output terminal of the delay chain 30 is connected to the first input terminal of the nand gate b1, and the second input terminal of the nand gate b1 is connected to the sense amplifier enable terminal SAE. The output end of the NAND gate b1 is connected to the inverting control end LATB of the latch 102 and the input end of the third inverter a 3; the output of the third inverter a3 is connected to the non-inverting control terminal LAT of the latch 102.
Referring to fig. 6 and 7, when the Read0 operation is performed (i.e., read 0), the potential on the global bit line GBL is inverted from the high potential to the low potential, in this case, the low potential on the global bit line GBL is delayed by the delay chain 30, and after the delay signal is and-ed with the signal of the sense amplifier enable terminal SAE by the nand gate b1, the control signal of the inverted control terminal LATB is generated, and the control signal of the non-inverted control terminal LAT is generated by the inverter a3, so that the control signal of the non-inverted control terminal LAT is inverted from the high potential to the low potential before the low potential on the global bit line GBL is inverted to the high potential due to the delay action of the delay chain 30, thereby closing the latch 102 in advance and ensuring the normal latching of the data "0".
The entire Read operation (Read 1 and Read 0) procedure of the memory circuit of the present application is schematically described below with reference to fig. 6 and 7.
A precharge phase:
after the Read operations (Read 1 and Read 0) are started (i.e., the clock signal CLK is at a high level), the global precharge signal terminal GPREB inputs a low level, controls the third P-type transistor MP3 to be turned on (i.e., the global precharge unit 101 is turned on), and outputs a high level signal of the first voltage terminal Vdd to the global bit line GBL for global precharge. And before the input signal of the global precharge signal terminal GPREB turns to high level (i.e., before the global precharge unit 101 is turned off), a high level signal is input to the local precharge signal terminal LPRE in the operating bank, the amplified precharge signal terminal LPREB is a low level signal, the sense amplifier circuit 201 performs precharge, the second P-type transistor MP2 remains on, and after the local precharge signal terminal LPRE turns to low level signal (i.e., the first control signal), the first P-type transistor MP1 turns on, so that the high level signal of the first voltage terminal Vdd is output to the global bit line GBL for relay precharge, and the high potential on the global bit line GBL is maintained, so that the local relay precharge can be implemented before the global precharge unit 101 stops precharge.
In addition, referring to fig. 3, in the non-operating banks (e.g., bank1, bank2, and bank 3), the local precharge signal terminal LPRE may be controlled to input a high level signal, so as to control the first P-type transistor MP1 to be turned off, thereby avoiding the non-operating banks (e.g., bank1, bank2, and bank 3) from affecting the data on the global bit line GBL in the operating banks (e.g., bank 0).
Data reading stage:
In the Read1 operation (Read 1), the sense amplifier circuit 201 amplifies the signal from the memory cell C, and then the first output terminal Out1 keeps outputting high voltage, the first P-type transistor MP1 and the second P-type transistor P2 keep on, and the high signal of the first voltage terminal Vdd is outputted to the global bit line GBL and latched in the latch 102.
In the Read0 operation (Read 0), the sense amplifier circuit 201 is controlled to amplify the signal from the memory cell C, the signal at the first output terminal Out1 is changed from the high potential to the low potential, the second P-type transistor P2 is turned off, the first N-type transistor MN1 is turned on, and the high signal at the second voltage terminal GND is outputted to the global bit line GBL and latched in the latch 102.
In the process of the Read operation (Read 1 and Read 0), the specific control procedures of the sense amplifying circuit 201 and the latch 102 may refer to the foregoing descriptions, and will not be repeated here.
It should be noted that, the N-type transistor and the P-type transistor in the present application may be enhancement type transistors or depletion type transistors, which is not limited in this aspect of the present application; and the source and drain of the transistor may not be clearly distinguished, i.e., the two electrodes (source and drain) other than the gate in the transistor may be interchanged, which is not limited by the present application.
It should be noted that, in other possible implementations of the embodiments of the present application, the N-type transistor and the P-type transistor in the foregoing memory circuit may be inverted entirely, that is, the N-type transistor in fig. 4 and fig. 7 is inverted entirely to be a P-type transistor, and the P-type transistor is inverted entirely to be an N-type transistor, which, of course, also causes the corresponding control signal to be inverted correspondingly.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (12)

1. A memory circuit is characterized by comprising a plurality of memory blocks, a main input/output circuit and a global bit line;
each storage block comprises a storage array and a local input/output circuit connected with the storage array; the local input/output circuit comprises a local control circuit;
The main input/output circuit comprises a global precharge unit; the global precharge unit is used for performing global precharge on the global bit line;
The local control circuit is configured to: precharging the global bit line before the global precharge unit stops global precharging the global bit line; and, after the precharge is completed, a read signal from the memory array is output to the global bit line.
2. The memory circuit of claim 1, wherein,
The memory circuit comprises a first voltage end and a second voltage end;
The local input/output circuit further comprises: a sense amplifier circuit; the sensitive amplifying circuit comprises a first input end, a first output end, a sensitive amplifying enabling end and a precharge voltage end;
The main input/output circuit also comprises a latch;
the global precharge unit, the latch and the local control circuit are all connected with the global bit line;
The local control circuit comprises a second input end, a second output end and a local pre-charging signal end, and is connected with the first voltage end and the second voltage end;
the first input terminal is connected to the memory array, and the first output terminal is connected to the second input terminal; the second output terminal is connected to the global bit line;
the sense amplifying circuit is configured to: under the control of signals of the sensitive amplification enabling end and the pre-charging voltage end, the reading signal from the storage unit received by the first input end is amplified and then output to the local control circuit through the first output end;
The local control circuit is further configured to: outputting the potential of the first voltage end to the second output end to precharge the global bit line under the control of signals of the local precharge signal end and the second input end before the global precharge unit stops performing global precharge on the global bit line; and outputting the potential of the first voltage terminal or the second voltage terminal to the global bit line through the second output terminal according to the read signal input from the second input terminal after the precharge is completed.
3. The memory circuit of claim 2, wherein,
The local control circuit comprises a first inverter, a first N-type transistor, a first P-type transistor and a second P-type transistor;
The input end of the first inverter is connected with the first output end, and the output end of the first inverter is connected to the grid electrode of the first N-type transistor and the grid electrode of the second P-type transistor;
The grid electrode of the first P-type transistor is connected to the local pre-charge signal end, the source electrode of the first P-type transistor is connected with the first voltage end, the drain electrode of the first P-type transistor is connected with the source electrode of the second P-type transistor, and the drain electrode of the second P-type transistor is connected to the global bit line; the source of the first N-type transistor is connected with the second voltage end, and the drain of the first N-type transistor is connected to the global bit line.
4. The memory circuit of claim 3 wherein,
The local control circuit further comprises a second inverter; the input end of the second inverter is connected with the local pre-charge signal end, and the output end of the second inverter is connected with the pre-charge voltage end.
5. A memory circuit according to any one of claims 1 to 4, wherein,
The global precharge unit comprises a third P-type transistor and a global precharge signal terminal;
the grid electrode of the third P-type transistor is connected with the global pre-charge signal end, the source electrode of the third P-type transistor is connected to the first voltage end, and the drain electrode of the third P-type transistor is connected to the global bit line.
6. A memory circuit according to any one of claims 1 to 5, wherein,
The main input/output circuit further comprises a delay module;
The delay module is connected with the global bit line, the sense amplification enabling end and the latch;
The delay module is configured to delay the signal on the global bit line and output a control signal to the latch under the control of the signal of the sense amplification enabling end so that the latch latches the signal on the global bit line and then closes in advance.
7. The memory circuit of claim 6, wherein,
The delay module comprises a delay chain, a NAND gate and a third inverter;
the input end of the delay chain is connected with the global bit line, the output end of the delay chain is connected with the first input end of the NAND gate, and the second input end of the NAND gate is connected with the sense amplification enabling end;
the output end of the NAND gate is connected to the inverting control end of the latch and the input end of the third inverter;
An output of the third inverter is connected to a non-inverting control of the latch.
8. A memory circuit according to any one of claims 2 to 7, wherein,
The sense amplifying circuit includes: a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a first node, a second node;
the first input terminal includes: a first amplification input and a second amplification input;
the grid electrode of the fourth P-type transistor and the grid electrode of the sixth P-type transistor are connected to the pre-charge voltage terminal; the sources of the fourth P-type transistor, the fifth P-type transistor, the sixth P-type transistor and the seventh P-type transistor are all connected to the first voltage end; the drains of the fourth P-type transistor and the fifth P-type transistor are connected with the first node, and the drains of the sixth P-type transistor and the seventh P-type transistor are connected with the second node; a gate of the fifth P-type transistor is connected to the second node; a gate of the seventh P-type transistor is connected to the first node, and the first node is connected to the first output terminal;
The gates of the second N-type transistor and the third N-type transistor are connected to an isolation signal control end, the source electrode of the second N-type transistor is connected to the first amplifying input end, and the drain electrode of the second N-type transistor is connected to the second node; a source of the third N-type transistor is connected to the second amplification input terminal, and a drain of the third N-type transistor is connected to the first node;
A grid electrode of the fourth N-type transistor is connected with the first node, a drain electrode of the fourth N-type transistor is connected with the second node, and a source electrode of the fourth N-type transistor is connected with a drain electrode of the sixth N-type transistor;
A grid electrode of the fifth N-type transistor is connected with the second node, a drain electrode of the fifth N-type transistor is connected to the first node, and a source electrode of the fifth N-type transistor is connected to a drain electrode of the sixth N-type transistor;
A gate of the sixth N-type transistor is connected to the sense amplification enable terminal, and a source of the sixth N-type transistor is connected to the second voltage terminal.
9. A memory circuit according to any one of claims 1 to 8, wherein,
The latch comprises an eighth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a seventh N-type transistor, an eighth N-type transistor, a ninth N-type transistor, a tenth N-type transistor, a fourth inverter, a normal phase control end and an inversion control end;
A gate of the eighth P-type transistor is connected to the inversion control terminal, a source of the eighth P-type transistor is connected to the first voltage terminal, and a drain of the eighth P-type transistor is connected to a source of the ninth P-type transistor;
A gate of the ninth P-type transistor is connected to the global bit line, and a drain of the ninth P-type transistor is connected to an input terminal of the fourth inverter; the output end of the fourth inverter is connected to the output end of the latch;
A grid electrode of the tenth P-type transistor is connected to the positive control end, a source electrode of the tenth P-type transistor is connected to the first voltage end, and a drain electrode of the tenth P-type transistor is connected to a source electrode of the eleventh P-type transistor;
a gate of the eleventh P-type transistor is connected to the output terminal of the fourth inverter, and a drain of the eleventh P-type transistor is connected to the input terminal of the fourth inverter;
A gate of the seventh N-type transistor is connected to the global bit line, a drain of the seventh N-type transistor is connected to the input terminal of the fourth inverter, and a source of the seventh N-type transistor is connected to the drain of the eighth N-type transistor;
A grid electrode of the eighth N-type transistor is connected to the positive control end, and a source electrode of the eighth N-type transistor is connected to the second voltage end;
A gate of the ninth N-type transistor is connected to the output terminal of the fourth inverter, a drain of the ninth N-type transistor is connected to the input terminal of the fourth inverter, and a source of the ninth N-type transistor is connected to the drain of the tenth N-type transistor;
a gate of the tenth N-type transistor is connected to the inversion control terminal, and a source of the tenth N-type transistor is connected to the second voltage terminal.
10. A control method of a memory circuit according to any one of claims 1 to 9, comprising:
A precharge phase:
Controlling the global precharge unit to be started, and performing global precharge on the global bit line; and before the global precharge unit is turned off, controlling the local control circuit to precharge the global bit line;
Data reading stage:
The local control circuit is controlled to output a read signal from the memory array to the global bit line.
11. A memory device comprising a controller and a memory circuit according to any one of claims 1-9, the memory circuit being electrically connected to the controller.
12. An electronic device comprising a printed wiring board and the memory device of claim 11; the storage device is electrically connected with the printed circuit board.
CN202211440011.2A 2022-11-17 2022-11-17 Memory circuit, memory device, and electronic apparatus Pending CN118053470A (en)

Priority Applications (2)

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CN202211440011.2A CN118053470A (en) 2022-11-17 2022-11-17 Memory circuit, memory device, and electronic apparatus
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US7782692B2 (en) * 2008-01-09 2010-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Single end read module for register files
US7668035B2 (en) * 2008-04-07 2010-02-23 International Business Machines Corporation Memory circuits with reduced leakage power and design structures for same
US20140126273A1 (en) * 2012-11-02 2014-05-08 International Business Machines Corporation Power management sram global bit line precharge circuit
US9087565B2 (en) * 2012-11-20 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pre-charging a data line
US10049726B1 (en) * 2017-02-03 2018-08-14 Advanced Micro Devices, Inc. Contention-free dynamic logic
US20220122657A1 (en) * 2020-10-15 2022-04-21 Stmicroelectronics International N.V. Device and method for reading data from memory cells

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