CN118057530A - Reading circuit of memory - Google Patents
Reading circuit of memory Download PDFInfo
- Publication number
- CN118057530A CN118057530A CN202211463550.8A CN202211463550A CN118057530A CN 118057530 A CN118057530 A CN 118057530A CN 202211463550 A CN202211463550 A CN 202211463550A CN 118057530 A CN118057530 A CN 118057530A
- Authority
- CN
- China
- Prior art keywords
- array
- read
- memory
- control mos
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013643 reference control Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1697—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention provides a reading circuit of a memory, comprising: the read array comprises a plurality of memory cells positioned on a column; the reference circuit includes a reference resistor and a reference array for matching leakage current generated by the non-turned-on memory cells during a read operation of the read array.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a memory read circuit.
Background
Reading the information stored by the MRAM is achieved by detecting the resistance of the memory cell. The resistance of the memory cell has two states, a high resistance state Rap ("AP" state) or a low resistance state Rp ("P" state). When the read operation is performed, the read current pulse Idata is generated by applying the clamp voltage (Vclamp) to the resistor of the memory cell, the reference current Iref is generated by applying the reference voltage (Vref) to the reference resistor Rref, and the sense amplifier can recognize that the memory cell is in a high-resistance state or a low-resistance state by comparing the read current Idata with the reference current Iref, so that "1" or "0" can be read.
In the process of realizing the invention, the inventor finds that at least the following technical problems exist in the prior art:
Memory cells on the same column are turned on during a read operation, and the other memory cells are turned off. However, due to the subthreshold leakage phenomenon, the memory cell in the off state still has a small leakage current Ileak passing therethrough, and the higher the temperature, the larger the leakage current. As shown in fig. 1, the data terminal current iap_high in the ap state at a high temperature is larger than the data terminal current iap_low in the ap state at a low temperature due to the influence of the leakage. But the reference terminal current Iref does not substantially change with temperature. This will lead to a reduced read window at high temperatures and even a disappearance of the read window, affecting the read yield.
Disclosure of Invention
In order to solve the above problems, the present invention provides a read circuit of a memory, which can reduce the influence of leakage current on a read window.
The invention provides a reading circuit of a memory, comprising:
a read array including a plurality of memory cells located on a column;
the gate end of the clamping control MOS tube is input with clamping voltage and is used for generating data end current on the read array;
The reference circuit comprises a reference resistor and a reference array, wherein the reference array is used for matching leakage current generated by an unopened memory cell during a read operation of the read array;
The gate end of the reference control MOS tube inputs reference voltage and is used for generating reference end current on the reference circuit;
and one end of the sense amplifier is connected with the read array through the clamping control MOS tube, the other end of the sense amplifier is connected with the reference circuit through the reference control MOS tube, and the sense amplifier is used for outputting a read result by comparing the current of the data end with the current of the reference end.
Optionally, each of the memory cells includes a magnetic tunnel junction and a switching tube connected to the magnetic tunnel junction.
Optionally, the reference array includes a plurality of memory cells located on a column, the memory cell structure of the reference array is the same as the memory cell structure of the read array, the number of memory cells included in the reference array is one less than the number of memory cells included in the read array, a bit line of the reference array is connected with the reference control MOS transistor, and a source line of the reference array is connected with a ground line.
Optionally, the reference resistor includes a reference cell and a first resistor, the reference cell is implemented by a memory cell, the structure of the reference cell is the same as that of the memory cell of the read array, the magnetic tunnel junction state in the reference cell is in a parallel state, the state of a switch tube in the reference cell is controlled by a reference word line, and the reference cell and the reference array share a bit line and a source line;
the first resistor is connected between a source line and a ground line of the reference array, and forms a reference resistor for a read operation together with the reference cell.
Optionally, the resistance value of the first resistor is R, and Rp < rp+r < Rap is satisfied, rp represents the resistance of the magnetic tunnel junction in the parallel state, and Rap represents the resistance of the magnetic tunnel junction in the antiparallel state.
Optionally, the reference array and the reference unit are implemented by a column of redundant columns of the storage array, the number of storage units included in the redundant columns is the same as that of the read array, the structures of the storage units are the same, any one storage unit of the redundant columns is used as the reference unit, and other storage units except the reference unit form the reference array.
Optionally, the method further comprises:
The first branch switch is connected between the clamping control MOS tube and a bit line of the read array;
The second branch switch is connected between a source line and a ground line of the read array;
and the third branch switch is connected between the bit line of the reference array and the reference control MOS tube.
Optionally, the reference resistor comprises a second resistor, and the second resistor is connected between the reference control MOS transistor and the ground line to form a reference resistor for reading operation.
Optionally, the resistance of the second resistor is between Rp and Rap, rp represents the resistance of the magnetic tunnel junction in the parallel state, and Rap represents the resistance of the magnetic tunnel junction in the antiparallel state.
Optionally, the method further comprises:
the fourth branch switch is connected between the clamping control MOS tube and the bit line of the read array;
a fifth branch switch connected between a source line and a ground line of the read array;
the sixth branch switch is connected between the bit line of the reference array and the reference control MOS tube;
And the seventh branch switch is connected between the second resistor and the reference control MOS tube.
According to the read circuit of the memory, the reference array is added in the reference circuit, and can be matched with the electric leakage generated by the unopened memory cells in the read array, so that the influence of the electric leakage on the read window is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art method for reducing a read window due to leakage current at high temperature;
FIG. 2 is a schematic diagram of a read circuit of a memory according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a read circuit for implementing leakage current matching using the memory of FIG. 2;
FIG. 4 is a schematic diagram of a read circuit of a memory according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of a read circuit for implementing leakage current matching using the memory of FIG. 4;
FIG. 6 is a schematic diagram showing the effect of reducing the influence of leakage current on a read window.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are only used to better describe the present application and its embodiments and are not intended to limit the scope of the indicated devices, elements or components to the particular orientations or to configure and operate in the particular orientations.
Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the present application will be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, the terms "mounted," "configured," "provided," "connected," "coupled," and "sleeved" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
An embodiment of the present invention provides a read circuit of a memory, including: the read array, the clamping control MOS tube, the reference circuit, the reference control MOS tube and the sensitive amplifier, wherein,
The read array comprises a plurality of memory cells positioned on a column;
the gate end of the clamping control MOS tube inputs clamping voltage for generating data end current on the read array;
The reference circuit comprises a reference resistor and a reference array, wherein the reference array is used for matching leakage current generated by an unopened memory cell during read operation of the read array;
The gate end of the reference control MOS tube inputs reference voltage for generating reference end current on the reference circuit;
One end of the sense amplifier is connected to the read array through the clamping control MOS tube, the other end of the sense amplifier is connected to the reference circuit through the reference control MOS tube, and the sense amplifier is used for outputting a read result by comparing the current of the data end with the current of the reference end.
As an embodiment, fig. 2 shows a schematic circuit configuration of a read circuit of a memory, and as shown in fig. 2, the read circuit of the memory includes: the read array 101, the clamping control MOS tube M1, the reference circuit, the reference control MOS tube M2 and the sense amplifier SA, wherein,
The read array 101 may be any column of a memory array including 2 n (n is a positive integer) memory cells located on a column, each memory cell including a magnetic tunnel junction and a switching tube connected to the magnetic tunnel junction. The switching state of the switching tube of each memory cell is controlled by the corresponding WL <2 n -1:0> signal.
The gate terminal of the clamp control MOS transistor M1 is inputted with a clamp voltage Vclamp for generating a data terminal current on the read array.
The reference circuit includes a reference resistor and a reference array 102, the reference array 102 being configured to match leakage currents generated by the non-activated memory cells during a read operation of the read array.
The gate end of the reference control MOS tube M2 inputs a reference voltage Vref for generating a reference end current on a reference circuit;
One end of the sense amplifier SA is connected to the read array 101 through the clamping control MOS tube M1, the other end of the sense amplifier SA is connected to the reference circuit through the reference control MOS tube M2, and the sense amplifier is used for outputting a read result by comparing the current of the data end with the current of the reference end.
Specifically, in this embodiment, the reference array 102 includes a plurality of memory cells located on a column, the memory cell structure of the reference array 102 is the same as the memory cell structure of the read array 101, the number of memory cells included in the reference array 102 is one less than the number of memory cells included in the read array 101, the bit line of the reference array 102 is connected to the reference control MOS transistor M2, and the source line of the reference array is connected to the ground line. The magnetic tunnel junction state in each memory cell of the reference array 102 is not particularly limited, and may be parallel or antiparallel.
In this embodiment, the reference resistor includes a reference cell 103 and a first resistor RINT, the reference cell 103 is implemented by a memory cell, the structure of the reference cell 103 is the same as that of the memory cell of the read array 101, the magnetic tunnel junction state in the reference cell 103 is in a parallel state, the switching transistor state in the reference cell 103 is controlled by a reference word line wl_ref, and the reference cell 103 and the reference array 102 share a bit line and a source line; the first resistor RINT is connected between the source line and ground line of the reference array, and forms a reference resistor for a read operation with the reference cell 103. The resistance value of the first resistor RINT is R, and Rp < Rp+R < Rap, rp represents the resistance of the magnetic tunnel junction in the parallel state, and Rap represents the resistance of the magnetic tunnel junction in the anti-parallel state.
As shown in fig. 2, the reference array 102 and the reference cell 103 may be implemented by a column of a redundant column of the memory array, where the number of memory cells included in the redundant column is the same as that of the read array, and the structures of the memory cells are the same, and any one of the memory cells in the redundant column is used as the reference cell 103, and the memory cells in the redundant column except for the reference cell constitute the reference array 102.
In addition, the read circuit of the present embodiment further includes:
the first branch switch K1 is connected between the clamping control MOS tube M1 and a bit line of the read array 101;
A second branch switch K2 connected between the source line and the ground line of the read array 101;
The third branch switch K3 is connected between the bit line of the reference array 102 and the reference control MOS transistor M2. By means of the bypass switch, different read arrays can be selected, which column is connected to, and which column of data is read.
For the read circuit of the memory provided by the embodiment, the reference unit and the reference array are directly realized by using one column of redundant columns of the memory array without changing the array structure, and only one resistor is required to be additionally connected in series, so that the realization is simple and the applicability is strong.
To illustrate the technical effect of embodiments of the present invention, referring to FIG. 3, a read array is composed of 1024 memory cells, the switching state of the switching tube of each memory cell is controlled by the corresponding WL <1023:0> signals. The control signals of the reference array are all turned off, WL_REF controls the switch of the reference cell, and the MTJ state in the reference cell is Rp state.
During reading operation, vref, vclamp and branch switches K1, K2 and K3 are opened, the memory cells to be read are opened by controlling WL <1023>, and WL_REF is opened at the same time, so that the leakage of the unopened memory cells in the read array and the leakage of the reference array can be matched with each other, the difference of currents of a data end and a reference end caused by the leakage is avoided, and the problem of reduction of a read window is solved.
On the other hand, as an embodiment, fig. 4 shows a schematic circuit configuration of a read circuit of a memory, which differs from the configuration of fig. 2 in that: the reference resistor is implemented differently. In this embodiment, the reference resistor includes a second resistor Rref, and the second resistor Rref is connected between the reference control MOS transistor and the ground line to form a reference resistor for the read operation. The second resistor Rref has a resistance value between Rp, which represents the resistance of the magnetic tunnel junction in the parallel state, and Rap, which represents the resistance of the magnetic tunnel junction in the antiparallel state.
In addition, the read circuit of the present embodiment further includes:
The fourth branch switch K4 is connected between the clamping control MOS tube and a bit line of the read array;
A fifth branch switch K5 connected between the source line and the ground line of the read array;
The sixth branch switch K6 is connected between the bit line of the reference array and the reference control MOS tube;
and the seventh branch switch K7 is connected between the second resistor and the reference control MOS tube.
For the read circuit of the memory provided by the embodiment, a reference resistor is not required to be designed, the reference array is only required to be one memory cell less than the read array, the realization is simple, and the applicability is strong.
To illustrate the technical effect of embodiments of the present invention, referring to FIG. 5, a read array is composed of 1024 memory cells, the switching state of the switching tube of each memory cell is controlled by the corresponding WL <1023:0> signals. The control signals of the reference array are all turned off.
During reading operation, vref, vclamp and branch switches K4, K5, K6 and K7 are opened, and memory cells to be read are opened by controlling WL <1023>, so that the leakage of unopened memory cells in the read array and the leakage of the reference array can be matched with each other, the difference between the currents of a data end and a reference end caused by the leakage is avoided, and the problem of reduction of a read window is solved. As shown in fig. 6, after the read circuit of the embodiment of the present invention is applied, the read window is not reduced at high temperature.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A read circuit for a memory, comprising:
a read array including a plurality of memory cells located on a column;
the gate end of the clamping control MOS tube is input with clamping voltage and is used for generating data end current on the read array;
The reference circuit comprises a reference resistor and a reference array, wherein the reference array is used for matching leakage current generated by an unopened memory cell during a read operation of the read array;
The gate end of the reference control MOS tube inputs reference voltage and is used for generating reference end current on the reference circuit;
and one end of the sense amplifier is connected with the read array through the clamping control MOS tube, the other end of the sense amplifier is connected with the reference circuit through the reference control MOS tube, and the sense amplifier is used for outputting a read result by comparing the current of the data end with the current of the reference end.
2. The memory read circuit of claim 1 wherein each of the memory cells includes a magnetic tunnel junction and a switching tube connected to the magnetic tunnel junction.
3. The memory read circuit of claim 1, wherein the reference array comprises a plurality of memory cells on a column, the memory cells of the reference array have the same structure as the memory cells of the read array, the reference array comprises one fewer memory cells than the read array, the bit line of the reference array is connected with the reference control MOS transistor, and the source line of the reference array is connected with the ground line.
4. The memory read circuit of claim 3, wherein,
The reference resistor comprises a reference unit and a first resistor, wherein the reference unit is realized by a storage unit, the structure of the reference unit is the same as that of the storage unit of the read array, the magnetic tunnel junction state in the reference unit is in a parallel state, the state of a switch tube in the reference unit is controlled by a reference word line, and the reference unit and the reference array share a bit line and a source line;
the first resistor is connected between a source line and a ground line of the reference array, and forms a reference resistor for a read operation together with the reference cell.
5. The memory read circuit of claim 4 wherein the first resistance has a resistance value R and satisfies Rp < rp+r < Rap, rp representing the resistance of the magnetic tunnel junction in the parallel state and Rap representing the resistance of the magnetic tunnel junction in the anti-parallel state.
6. The memory read circuit according to claim 4, wherein the reference array and the reference cells are implemented by a column redundancy column of the memory array, the redundancy column including the same number of memory cells as the read array and having the same structure, any one of the memory cells of the redundancy column being the reference cell, and the memory cells of the redundancy column other than the reference cell constituting the reference array.
7. The memory read circuit of claim 4, further comprising:
The first branch switch is connected between the clamping control MOS tube and a bit line of the read array;
The second branch switch is connected between a source line and a ground line of the read array;
and the third branch switch is connected between the bit line of the reference array and the reference control MOS tube.
8. The memory read circuit of claim 3 wherein the reference resistor comprises a second resistor connected between the reference control MOS transistor and ground to form a reference resistor for a read operation.
9. The memory read circuit of claim 8 wherein the second resistance has a resistance between Rp and Rap, rp representing the resistance of the magnetic tunnel junction in the parallel state and Rap representing the resistance of the magnetic tunnel junction in the anti-parallel state.
10. The memory read circuit of claim 8, further comprising:
the fourth branch switch is connected between the clamping control MOS tube and the bit line of the read array;
a fifth branch switch connected between a source line and a ground line of the read array;
the sixth branch switch is connected between the bit line of the reference array and the reference control MOS tube;
And the seventh branch switch is connected between the second resistor and the reference control MOS tube.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211463550.8A CN118057530A (en) | 2022-11-21 | 2022-11-21 | Reading circuit of memory |
| PCT/CN2023/133022 WO2024109750A1 (en) | 2022-11-21 | 2023-11-21 | Read circuit for memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211463550.8A CN118057530A (en) | 2022-11-21 | 2022-11-21 | Reading circuit of memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118057530A true CN118057530A (en) | 2024-05-21 |
Family
ID=91069505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211463550.8A Pending CN118057530A (en) | 2022-11-21 | 2022-11-21 | Reading circuit of memory |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN118057530A (en) |
| WO (1) | WO2024109750A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100295361B1 (en) * | 1998-12-30 | 2001-07-12 | 윤종용 | Nonvolatile Semiconductor Memory Devices |
| KR101194933B1 (en) * | 2010-12-08 | 2012-10-25 | 에스케이하이닉스 주식회사 | Nonvolatile memory device |
| CN105931665B (en) * | 2016-04-19 | 2020-06-09 | 中国科学院上海微系统与信息技术研究所 | Phase change memory reading circuit and method |
| CN114639410A (en) * | 2020-12-15 | 2022-06-17 | 浙江驰拓科技有限公司 | Magnetic random access memory and reading circuit thereof |
| CN114664343A (en) * | 2020-12-23 | 2022-06-24 | 中芯国际集成电路制造(上海)有限公司 | Magnetic random access memory, memory array and electronic equipment |
-
2022
- 2022-11-21 CN CN202211463550.8A patent/CN118057530A/en active Pending
-
2023
- 2023-11-21 WO PCT/CN2023/133022 patent/WO2024109750A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024109750A1 (en) | 2024-05-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1612801B1 (en) | Power-saving reading of magnetic memory devices | |
| US7974121B2 (en) | Write current compensation using word line boosting circuitry | |
| US7649792B2 (en) | Sense amplifier | |
| US20100110785A1 (en) | Memory Cell With Proportional Current Self-Reference Sensing | |
| US8363449B2 (en) | Floating source line architecture for non-volatile memory | |
| KR101674907B1 (en) | Random access memory architecture including midpoint reference | |
| US7936625B2 (en) | Pipeline sensing using voltage storage elements to read non-volatile memory cells | |
| EP3975185A1 (en) | Non-volatile memory having virtual ground circuitry | |
| WO2020251699A1 (en) | Narrow range sense amplifier with immunity to noise and variation | |
| JP5077646B2 (en) | Semiconductor memory device and method for operating semiconductor memory device | |
| US11289144B1 (en) | Non-volatile memory with virtual ground voltage provided to unselected column lines during memory write operation | |
| CN113129953B (en) | Read circuit of magnetic random access memory | |
| US11250898B2 (en) | Non-volatile memory with multiplexer transistor regulator circuit | |
| CN118057530A (en) | Reading circuit of memory | |
| US11521665B2 (en) | Non-volatile memory having write detect circuitry | |
| KR20200134144A (en) | Input circuit devices for sense amplifier circuits | |
| KR102204667B1 (en) | Magnetoresistive random access memory for performing write operation with low power and method of controlling the write operation | |
| CN118116428A (en) | Reading circuit of memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |