CN118054777A - Reset circuit and electronic chip - Google Patents

Abstract

The invention provides a reset circuit and an electronic chip, wherein the reset circuit comprises: the device comprises a voltage detection module, a reset triggering module and a reset output module; the voltage detection module is connected between the power supply voltage and the ground and is used for detecting the power supply voltage and generating a voltage signal output; the reset trigger module is connected with the output end of the voltage detection module and is used for generating a reset trigger signal according to a voltage signal to output when the power supply voltage rises from zero voltage to steady-state voltage or is powered down from the steady-state voltage to be less than or equal to low-voltage reset point voltage; the reset output module is connected with the output end of the reset trigger module and is used for generating a reset signal for output according to the reset trigger signal. The reset circuit and the electronic chip provided by the invention solve the problems that the existing reset circuit is not provided with a power-on reset function and a low-voltage reset function at the same time and has low reliability.

Description

Reset circuit and electronic chip

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a reset circuit and an electronic chip.

Background

With the advancement of technology, integrated circuits have evolved very rapidly, and in particular for system-in-a-chip (SoC), reset circuits are an essential module. The existing reset circuits are roughly divided into two kinds according to functions: one is POR (Power On Reset) circuit, i.e., a power-on reset circuit, and the other is LVR (Low Voltage Reset) circuit, i.e., a low-voltage reset circuit.

The POR circuit is used for providing a reset level voltage value for each circuit in the chip when the power supply voltage is smaller than a set threshold value in the process that the system power supply for supplying power to the whole chip gradually rises from the initial zero potential until reaching a fixed high potential, and providing a reset signal generated by the POR circuit for a period of time and initializing the logic state of the digital circuit in the chip when the power supply voltage is larger than the set threshold value, so that the digital circuit in the chip can normally work, and the circuit cannot generate a logic chaotic state, and the POR circuit is very important for the chip, particularly the digital circuit in the chip. The LVR circuit is used for feeding back the working state of the system power supply in the working process of the chip, and can be used for directly resetting the chip when the power supply of the system power supply is insufficient.

With the reduction of chip size, the reset circuit is required to occupy a smaller chip area as much as possible, and meanwhile, high reliability is required, so that the reset circuit can generate a reset signal when being powered on rapidly. For a complete chip, the power-on reset function and the low-voltage reset function are required to be simultaneously provided, the power-on reset is performed to ensure that the logic of an internal digital circuit is normal in the power-on process of a system power supply, and the low-voltage reset is performed to ensure that a reset signal is generated when the power supply of the system power supply is insufficient and is truly fed back to the working state of the power supply.

However, the existing reset circuit often has a power-on reset function and a low-voltage reset function at the same time, and a POR circuit and a LVR circuit are required to be respectively and independently designed, so that the area of a chip occupied by the reset circuit is increased, and the cost is increased; on the other hand, the existing reset circuit is low in reliability, and is easy to reset and lose efficacy when a system power supply is powered on rapidly.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a reset circuit and an electronic chip, which are used for solving the problem that the existing reset circuit does not have a power-on reset function and a low-voltage reset function at the same time and has low reliability.

To achieve the above and other related objects, the present invention provides a reset circuit comprising: the device comprises a voltage detection module, a reset triggering module and a reset output module; wherein,

The voltage detection module is connected between the power supply voltage and the ground and is used for detecting the power supply voltage and generating a voltage signal output;

The reset trigger module is connected with the output end of the voltage detection module and is used for generating a reset trigger signal for output according to the voltage signal when the power supply voltage rises from zero voltage to steady-state voltage or is powered down from the steady-state voltage to a voltage less than or equal to a low-voltage reset point;

The reset output module is connected with the output end of the reset trigger module and is used for generating a reset signal for output according to the reset trigger signal.

Optionally, the voltage detection module includes: at least one first PMOS tube, a first NMOS tube, a first resistor, a second resistor and a third resistor; the gate end of the first PMOS tube is grounded through the first resistor, the source end is connected with the power supply voltage, and the drain end is connected with the first end of the second resistor and the gate end of the first NMOS tube; the second end of the second resistor is connected with the first end of the third resistor; the second end of the third resistor is connected with the drain end of the first NMOS tube and is used as the output end of the voltage detection module; and the source end of the first NMOS tube is grounded.

Optionally, when the number of the first PMOS transistors is greater than 1, gate ends of the first PMOS transistors after cascade connection are grounded through the first resistor, a source end is connected to the power supply voltage, and a drain end is connected to a first end of the second resistor and the gate end of the first NMOS transistor.

Optionally, the voltage detection module further includes: and the MOS capacitor is connected between the gate end of the first NMOS tube and the ground.

Optionally, the reset triggering module includes: the second PMOS tube, the third PMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first inverter and the capacitor; the grid end of the second PMOS tube is connected with the grid end of the second NMOS tube and the output end of the voltage detection module, the source end of the second PMOS tube is connected with the power supply voltage, and the drain end of the second PMOS tube is connected with the drain end of the second NMOS tube and the input end of the first inverter; the source end of the second NMOS tube is grounded; the output end of the first inverter is connected with the gate end of the third NMOS tube; the source end of the third NMOS tube is grounded, and the drain end of the third NMOS tube is connected with the source end of the fourth NMOS tube and the first end of the capacitor; the gate end of the fourth NMOS tube is connected with the power supply voltage, and the drain end of the fourth NMOS tube is connected with the drain end of the third PMOS tube; the first end of the capacitor is used as the output end of the reset triggering module, and the second end of the capacitor is grounded; and the gate end of the third PMOS tube is connected with the gate end of the second PMOS tube, and the source end of the third PMOS tube is connected with the power supply voltage.

Optionally, the reset output module includes: an inverting schmitt trigger and a second inverter; the input end of the inverted schmitt trigger is connected with the output end of the reset trigger module, the output end of the inverted schmitt trigger is connected with the input end of the second inverter, and the output end of the second inverter is used as the output end of the reset output module.

Optionally, the voltage detection module further includes: and the gate end of the fifth NMOS tube is connected with the output end of the reversed phase Schmidt trigger, and the source end and the drain end of the fifth NMOS tube are correspondingly connected with the two ends of the third resistor.

Optionally, the reset output module includes: a non-inverting schmitt trigger, a second inverter and a third inverter; the input end of the non-inverting schmitt trigger is connected with the output end of the reset trigger module, the output end of the non-inverting schmitt trigger is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter, and the output end of the third inverter is used as the output end of the reset output module.

Optionally, the voltage detection module further includes: and the gate end of the fifth NMOS tube is connected with the output end of the second phase inverter, and the source end and the drain end of the fifth NMOS tube are correspondingly connected with the two ends of the third resistor.

The invention also provides an electronic chip, comprising: a reset circuit as claimed in any one of the preceding claims.

As described above, the reset circuit and the electronic chip have the advantages that the design of the voltage detection module, the reset triggering module and the reset output module enables the reset circuit to have the power-on reset function and the low-voltage reset function at the same time, the power-on reset circuit and the low-voltage reset circuit do not need to be designed independently, the area of the chip occupied by the reset circuit is reduced to a certain extent, and the circuit cost is reduced; moreover, the reset circuit has high reliability, can output stable and effective reset signals when the power supply is powered on quickly and powered on quickly for the second time after the power supply is powered off, and can avoid the phenomenon of burrs of the reset signals caused by power supply noise or other interference; in addition, the overall current of the reset circuit is small, so that the overall power consumption of the reset circuit is low.

Drawings

Fig. 1 is a schematic diagram of a power-on reset circuit.

Fig. 2 is a schematic diagram of a low voltage reset circuit.

Fig. 3 shows a schematic diagram of a reset circuit of the present invention, wherein the reset output module includes an inverted schmitt trigger.

Fig. 4 is a schematic diagram showing that the voltage detection module in the reset circuit shown in fig. 3 includes a plurality of first PMOS transistors.

Fig. 5 shows a schematic diagram of a reset circuit of the present invention, wherein the reset output module includes a non-inverting schmitt trigger.

Fig. 6 shows waveforms of the power supply voltage and the reset signal in the reset circuit of the present invention.

Description of element reference numerals

100. Reset circuit

101. Voltage detection module

102. Reset trigger module

103. Reset output module

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Fig. 1 shows a power-on reset circuit comprising: NMOS tubes MN1 and MN2, a PMOS tube MP1, a resistor R1 and a buffer B1; the gate end of the NMOS tube MN1 is connected with the gate end of the PMOS tube MP1 and the gate end of the NMOS tube MN2, the source end is grounded, and the drain end is connected with the gate end thereof and is connected with the power supply voltage VDD through a resistor R1; the source end of the PMOS tube MP1 is connected with the power supply voltage VDD, and the drain end of the PMOS tube MP1 is connected with the drain end of the NMOS tube MN2 and the input end of the buffer B1; the source end of the NMOS tube is grounded; the output end of the buffer B1 is used as the output end of the power-on reset circuit for outputting the reset signal RST.

The working principle of the power-on reset circuit is as follows:

The power supply voltage VDD is lower, the on threshold of the NMOS transistor MN1 is not reached, the NMOS transistor MN1 is not turned on, and at this time, the node voltage V1 is the power supply voltage VDD; as the power supply voltage VDD gradually rises, the turn-on threshold of the NMOS transistor MN1 is reached, and the NMOS transistor MN1 is turned on; the divided node voltage V1 is gradually increased, when the divided node voltage V1 reaches the starting threshold value of the NMOS tube MN2, the NMOS tube MN2 is started, the PMOS tube MP1 is turned off, the node voltage V2 is pulled down, a reset signal for stabilizing low potential is output through the buffer B1, and the system is in a reset state;

As the power supply voltage VDD continues to rise, as the NMOS tube MN1 adopts the diode connection method, the node voltage V1 is basically unchanged due to the nonlinear characteristic of the diode, the gate-source voltage of the NMOS tube MN2 is basically unchanged, the absolute value of the gate-source voltage of the PMOS tube MP1 is increased, at the moment, the PMOS tube MP1 and the NMOS tube MN2 are simultaneously started, when the power supply voltage VDD rises to a certain value, the pull-up capacity of the PMOS tube MP1 is stronger than the pull-down capacity of the NMOS tube MN2, the node voltage V2 is pulled up, a stable high potential is output through the buffer B1, and the system is in a reset state and enters a normal working state.

The power-on reset circuit shown in fig. 1 has a power-on reset function, but does not have a low-voltage reset function; moreover, when the power supply is powered on quickly, the power-on reset circuit is likely to cause that the node voltage V1 cannot rise in time to turn on the NMOS transistor MN2 due to the fact that the node voltage V1 charges the parasitic capacitance of the second NMOS transistor MN2 to the ground, and the reset failure problem occurs, so that the reliability is low.

Fig. 2 shows a low voltage reset circuit comprising: resistors R1 and R2, a comparator CMP1, and an inverter INV1; the resistors R1 and R2 are cascaded between the power supply voltage VDD and the ground, and the connection nodes of the two resistors are connected with the inverting input end of the comparator CMP 1; the non-inverting input end of the comparator CMP1 is connected with the reference voltage VREF, and the output end of the comparator CMP1 is connected with the input end of the inverter INV1; an output terminal of the inverter INV1 serves as an output terminal of the low voltage reset circuit for outputting the reset signal RST.

The working principle of the low-voltage reset circuit is as follows: when the power supply voltage VDD drops, the node voltage V1 drops linearly along with the power supply voltage VDD until the reference voltage VREF is reached, the comparator CMP1 outputs an inversion (from low potential to high potential), a reset signal RST of low potential is output through the inverter INV1, and the system is in a reset state; during secondary power-up, the node voltage V1 rises linearly along with the power supply voltage VDD until the output of the comparator CMP1 is inverted again (changed from high potential to low potential) when reaching the reference voltage VREF, the high potential is output through the inverter INV1, and the system is in a reset state and enters a normal working state.

Although the low-voltage reset circuit shown in fig. 2 has a low-voltage reset function, the circuit structure is often complex; in addition, the circuit architecture generally has longer band gap reference establishment time, when a power supply is powered on rapidly, the rising speed of the node voltage V1 generated by the voltage division of the power supply voltage VDD through a resistor is faster than the establishment speed of the reference voltage VREF, so that the value of the node voltage V1 is always larger than the reference voltage VREF, and a reset signal with low potential cannot be generated, and the reliability is low; the common solution is to add other circuit modules, but the newly added circuit modules not only increase the power consumption and the area of the whole circuit, but also introduce other circuit defects to a certain extent; in addition, the reset circuit with the structure cannot be used as a power-on reset function, on one hand, the reference voltage VREF is not established yet, and on the other hand, the comparator is unstable.

Therefore, the reset circuit shown in fig. 1 and fig. 2 cannot have the power-on reset function and the low-voltage reset function at the same time, and the reset failure problem easily occurs when the power supply is powered on rapidly, so that the reliability is low. In view of this, the applicant has proposed the scheme of the present application, and the reset circuit according to the scheme of the present application has both a power-on reset function and a low-voltage reset function, and is highly reliable, and can stably output a reset signal when the power supply is rapidly powered on.

As shown in fig. 3, the present embodiment provides a reset circuit 100, the reset circuit 100 including: the device comprises a voltage detection module 101, a reset triggering module 102 and a reset output module 103.

The voltage detection module 101 is connected between the power supply voltage VDD and ground, and is used for detecting the power supply voltage VDD and generating a voltage signal output.

As an example, the voltage detection module 101 includes: the first PMOS tube MP1, the first NMOS tube MN1, the first resistor R1, the second resistor R2 and the third resistor R3; the gate end of the first PMOS tube MP1 is grounded through a first resistor R1, the source end is connected with a power supply voltage VDD, and the drain end is connected with the first end of a second resistor R2 and the gate end of a first NMOS tube MN 1; the second end of the second resistor R2 is connected with the first end of the third resistor R3; the second end of the third resistor R3 is connected with the drain end of the first NMOS tube MN1 and is used as the output end of the voltage detection module 101; the source terminal of the first NMOS transistor MN1 is grounded, as shown in fig. 3.

The number of the first PMOS tubes MP1 is not limited to one, but may be two, three, or even more, which is determined by specific requirements; when the number of the first PMOS transistors MP1 is greater than 1, the gate ends of the first PMOS transistors MP1 after being cascaded are grounded through the first resistor R1, the source end is connected to the power supply voltage VDD, and the drain end is connected to the first end of the second resistor R2 and the gate end of the first NMOS transistor MN1, as shown in fig. 4.

The cascade connection of the plurality of first PMOS tubes MP1 means that the drain ends and the source ends of two adjacent first PMOS tubes MP1 are connected, the source end of the first PMOS tube MP1 is used as the source end after cascade connection, the drain end of the last first PMOS tube MP1 is used as the drain end after cascade connection, and the gate ends of all the first PMOS tubes MP1 are connected with each other and are used as the gate ends after cascade connection; taking three first PMOS tubes MP1 as an example, the three first PMOS tubes MP1 are cascaded, the drain end of the first PMOS tube MP1 is connected with the source end of the second first PMOS tube MP1, the drain end of the second first PMOS tube MP1 is connected with the source end of the third first PMOS tube MP1, the source end of the first PMOS tube MP1 is used as the source end after the cascade, the drain end of the last first PMOS tube MP1 is used as the drain end after the cascade, and the gate ends of the three first PMOS tubes are mutually connected and used as the gate ends after the cascade.

In practical application, the first PMOS transistor MP1 generally selects a PMOS transistor with a larger on-resistance, such as a large inverted ratio transistor, so that when a power supply to ground is formed, the current I1 of the channel is smaller, the power consumption of the circuit is reduced, and meanwhile, the circuit area is saved; and through selecting the first PMOS tube MP1 with proper quantity, the channel current I1 with proper size can be designed, thereby reaching the expected circuit power consumption. Wherein,I1 is a path current, VDD is a value of a power supply voltage, R2 is a value of a second resistor, R3 is a value of a third resistor, R_Mp1 is a value of an on-resistance of the first PMOS tube MP1, and R_Mn1 is a value of an on-resistance of the first NMOS tube MN 1; the first PMOS transistor MP1 is designed as a large-inversion-ratio transistor, the first NMOS transistor MN1 is an inversion-ratio transistor, and if rjp1+rjm1+_10mΩ, vdd=5v, r2+r3=2.5mΩ, i1=5v/(2.5mΩ+10mΩ) =0.4 uA, lower power consumption is achieved with a smaller path current.

Further, the voltage detection module 101 further includes: the MOS capacitor C1 is connected between the gate end of the first NMOS tube MN1 and the ground; the MOS capacitor C1 is implemented by an NMOS tube, wherein a gate end of the NMOS tube is used as a first end of the MOS capacitor C1 to be connected with a gate end of the first NMOS tube MN1, and a source end and a drain end of the NMOS tube are connected with each other to be used as a second end of the MOS capacitor C1 to be grounded, as shown in fig. 3-5.

Further, when the reset output module 103 is implemented using the inverted schmitt trigger smit_n and an inverter (e.g., the second inverter INV 2), the voltage detection module 101 further includes: the gate end of the fifth NMOS transistor MN5 is connected to the output end of the inverted schmitt trigger smit_n, and the source end and the drain end are correspondingly connected to two ends of the third resistor R3, for example, the drain end is connected to the first end of the third resistor R3, and the source end is connected to the second end of the third resistor R3, as shown in fig. 3 and fig. 4. When the reset output module 103 is implemented by using the non-inverting schmitt trigger smit_p and two inverters (e.g., the second inverter INV2 and the third inverter INV 3), the gate end of the fifth NMOS transistor MN5 is connected to the output end of the second inverter INV2, and the source end and the drain end are connected unchanged, as shown in fig. 5.

The reset trigger module 102 is connected to the output end of the voltage detection module 101, and is configured to generate a reset trigger signal according to a voltage signal when the power supply voltage VDD rises from a zero voltage to a steady-state voltage or drops from the steady-state voltage to a voltage less than or equal to a low-voltage reset point.

As an example, the reset triggering module 102 includes: the second PMOS tube MP2, the third PMOS tube MP3, the second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, the first inverter INV1 and the capacitor C2; the gate end of the second PMOS tube MP2 is connected with the gate end of the second NMOS tube MN2 and the output end of the voltage detection module 101, the source end is connected with the power supply voltage VDD, and the drain end is connected with the drain end of the second NMOS tube MN2 and the input end of the first inverter INV 1; the source end of the second NMOS tube MN2 is grounded; the output end of the first inverter INV1 is connected with the gate end of the third NMOS transistor MN 3; the source end of the third NMOS tube MN3 is grounded, and the drain end of the third NMOS tube MN3 is connected with the source end of the fourth NMOS tube MN4 and the first end of the capacitor C2; the gate end of the fourth NMOS tube MN4 is connected with the power supply voltage VDD, and the drain end of the fourth NMOS tube MN4 is connected with the drain end of the third PMOS tube MP 3; the first end of the capacitor C2 is used as the output end of the reset triggering module 102, and the second end is grounded; the gate end of the third PMOS transistor MP3 is connected to the gate end of the second PMOS transistor MP2, and the source end is connected to the power supply voltage VDD, as shown in fig. 3-5.

The reset output module 103 is connected to the output end of the reset trigger module 102, and is configured to generate a reset signal for output according to the reset trigger signal.

As an example, the reset output module 103 includes: an inverting schmitt trigger smit_n and a second inverter INV2; the input end of the inverted schmitt trigger smit_n is connected to the output end of the reset trigger module 102, the output end is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is used as the output end of the reset output module 102, as shown in fig. 3 and fig. 4.

As another example, the reset output module 103 includes: a non-inverting schmitt trigger smit_p, a second inverter INV2, and a third inverter INV3; the input end of the non-inverting schmitt trigger smit_p is connected to the output end of the reset trigger module 102, the output end is connected to the input end of the second inverter IVN2, the output end of the second inverter INV2 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is used as the output end of the reset output module 103, as shown in fig. 5.

Referring to fig. 3, the operation principle of the reset circuit in the present embodiment will be described in detail, which includes two processes of power-on reset and low-voltage reset.

And (5) power-on reset:

The power supply voltage VDD is raised from zero voltage to reach the starting threshold value of the first PMOS tube MP1, the first PMOS tube MP1 is started, and the node voltage V1 can not be raised in time to start the second NMOS tube MN2 after being divided by the second resistor R2 due to the parasitic capacitance of the first NMOS tube MN1 and the second NMOS tube MN2 to the ground, but the node voltage V1 charges the MOS capacitor C1; because the on-resistance of the first PMOS transistor MP1 is very large, when the power supply voltage VDD increases to the first PMOS transistor MP1, the first PMOS transistor MP1 will divide most of the voltage and charge the MOS capacitor C1, so that the gate-source voltage of the first NMOS transistor MN1 is less than the on threshold value within a certain time, and the first NMOS transistor MN1 is not turned on. Because the node voltage V2 is connected to the gate ends of the second PMOS transistor MP2 and the third PMOS transistor MP3, the sum of the parasitic capacitance of the second PMOS transistor MP2 to the power supply voltage VDD and the parasitic capacitance of the third PMOS transistor MP3 to the power supply voltage VDD is stronger than the parasitic capacitance of the second NMOS transistor MN2 to the ground, which couples the node voltage V2 to a high potential, so as to turn on the second NMOS transistor MN2; because the second PMOS transistor MP2 is in the weak conduction state and the second NMOS transistor MN2 is in the full conduction state, the pull-down capability of the second NMOS transistor MN2 is stronger than the pull-up capability of the second PMOS transistor MP2, so that the node voltage V3 is pulled down, the third NMOS transistor MN3 is turned on after passing through the first inverter INV1, the node voltage V4 is pulled down, and then the low-potential reset signal RST is output after passing through the inverted schmitt trigger smit_n and the second inverter INV 2.

In the process, the MOS capacitor C1 is charged by the node voltage V1, so that the first NMOS tube MN1 can not reach the starting threshold value rapidly, the pull-up coupling capacity of the parasitic capacitance of the second PMOS tube MP2 and the third PMOS tube MP3 can be improved by the parallel design of the second PMOS tube MP2 and the third PMOS tube MP3 at the initial stage of power-up, the problem that the node voltage V2 cannot be coupled to a high potential is avoided, the problem of reset failure is avoided, stable reset signals are generated during the rapid power-up of a power supply, and the reliability of a circuit is improved.

Along with the gradual rise of the power supply voltage VDD, the node voltage V1 is also gradually increased, and the MOS capacitor C1 is continuously charged, when the MOS capacitor C1 is charged to the on threshold value of the first NMOS tube MN1, the first NMOS tube MN1 is turned on, a power supply to ground channel (channel current is I1) is generated at the moment, the node voltage V2 is pulled to a low potential from the original high potential, the second PMOS tube MP2 and the second NMOS tube MN2 are turned off, the inverted Schmidt trigger SMIT_N does not generate output inversion, and the circuit outputs a reset signal RST kept at the low potential; along with the continuous rising of the power supply voltage VDD, the node voltage V2 gradually rises from the low potential to the on threshold of the second NMOS transistor MN2, the first NMOS transistor MN1 and the second NMOS transistor MN2 are simultaneously turned on, the second PMOS transistor MP2 and the third PMOS transistor MP3 are not turned on, the node voltage V3 is pulled down, the third NMOS transistor MN3 is turned on after passing through the first inverter INV1, the node voltage V4 is pulled down, and then a low-potential reset signal RST is output after passing through the inverting schmitt trigger smit_n and the second inverter INV 2. Since the inverted schmitt trigger smit_n outputs a high voltage, the fifth NMOS transistor MN5 is turned on, and the third resistor R3 is shorted, so v2=v1-r2×i1.

As the power supply voltage VDD continues to rise, the first NMOS transistor MN1 adopts a diode connection method, the rising amount of the node voltage V2 is small due to the nonlinear characteristic of the diode, so that the gate source voltage of the second NMOS transistor MN2 is basically unchanged, but the absolute values of the gate source voltages of the second PMOS transistor MP2 and the third PMOS transistor MP3 are increased, the second PMOS transistor MP2 and the second NMOS transistor MN2 are simultaneously started at a certain moment, as the absolute value of the gate source voltage of the second PMOS transistor MP2 continues to be increased, the pull-up capability of the second PMOS transistor MP2 is stronger than the pull-down capability of the second NMOS transistor MN2, the node voltage V3 is pulled to a high potential, the third NMOS transistor MN3 is turned off after passing through the first inverter INV1, the capacitor C2 is charged by the power supply voltage VDD through the third PMOS transistor MP3 and the fourth NMOS transistor MN4, the node voltage V4 is charged to the high potential, when the inversion threshold of the inversion flip-flop SMIT_N is reached, the inversion flip-flop T_N outputs the low potential, and the state SMI is finished after the inversion of the flip-flop T_N is finished through the second inverter INV 2. Since the inverted schmitt trigger smit_n outputs a low voltage, the fifth NMOS transistor MN5 is turned off, and the third resistor R3 and the second resistor R2 are cascaded, so v2=v1- (r2+r3) ×i1.

In this process, the power supply voltage VDD charges the capacitor C2 to the inversion threshold of the inverted schmitt trigger smit_n, so that the node voltage V4 is still at a low potential before the inversion threshold of the inverted schmitt trigger smit_n is charged, and the reset signal RST of the low potential is still output after passing through the second inverter INV2, thereby further increasing the reliability of the reset circuit that can be normally reset when the power supply is rapidly powered on.

Low voltage reset:

With the power supply voltage VDD gradually decreasing, the inverted schmitt trigger smit_n outputs a low level when the power supply is in a steady state, the fifth NMOS transistor MN5 is turned off, the second resistor R2 is cascaded with the third resistor R3, so that the pull-down current of the second NMOS transistor MN2 decreases, the pull-down capability of the second NMOS transistor MN2 decreases compared with the pull-up capability of the second NMOS transistor MN2, so that the pull-up capability of the second PMOS transistor MP2 is lower than the pull-down capability of the second NMOS transistor MN2, thereby pulling down the node voltage V3, then the first NMOS transistor MN 1 turns into a high potential to turn on the third NMOS transistor MN3, the capacitor C2 discharges through the third NMOS transistor MN3, the node voltage V4 is discharged to a low potential, and when the pull-down capability of the inverted schmitt trigger smit_n reaches the turn-over threshold value of the inverted schmitt trigger smit_n, the inverted schmitt trigger smit_n outputs a high potential, and the second NMOS transistor smit_n outputs a low potential through the second inverter inv_2, thereby completing the low voltage reset function.

In this process, due to the feedback design of the fifth NMOS MN5, the fifth NMOS MN5 is turned off, the second resistor R2 and the third resistor R3 are cascaded, and compared with the power-on reset, the resistance between the node voltage V1 and the node voltage V2 is increased during the low-voltage reset, and the pull-down current of the second NMOS MN2 is reduced, so that the node voltage V3 needs to be lowered to a lower potential when the power supply voltage VDD is powered down from a high potential, thereby forming the hysteresis of the voltage values (i.e., the steady-state voltage v_up and the low-voltage reset point voltage v_down) corresponding to the power-on reset and the low-voltage reset, effectively avoiding the phenomenon of burrs on the reset signal caused by the power supply noise or other interference, and greatly increasing the circuit reliability, as shown in fig. 6.

When the power is turned on for the second time, since the gate end of the fourth NMOS tube MN4 is connected with the power supply voltage VDD, the instant on-resistance of the fourth NMOS tube MN4 is very large, so that the voltage for charging the capacitor C2 after the power supply voltage VDD is divided by the fourth NMOS tube MN4 is very small, the node voltage V4 cannot be quickly charged to the turning threshold value of the inverted Schmitt trigger SMIT_N, therefore, the node voltage V4 can still keep low potential in a period of time, the output of the second inverter INV2 can keep low potential, and the reset circuit can still be reset successfully when the power supply voltage VDD is quickly turned on.

Correspondingly, the embodiment also provides an electronic chip, which comprises the reset circuit 100 described above and is used for performing power-on reset and low-voltage reset on the electronic chip. Of course, the electronic chip should also include other functional circuits, which are determined by the functions of the electronic chip, and the present embodiment is not limited thereto.

In summary, according to the reset circuit and the electronic chip provided by the invention, through the design of the voltage detection module, the reset triggering module and the reset output module, the reset circuit has the power-on reset function and the low-voltage reset function at the same time, and the power-on reset circuit and the low-voltage reset circuit do not need to be independently designed, so that the area of the chip occupied by the reset circuit is reduced to a certain extent, and the circuit cost is reduced; moreover, the reset circuit has high reliability, can output stable and effective reset signals when the power supply is powered on quickly and powered on quickly for the second time after the power supply is powered off, and can avoid the phenomenon of burrs of the reset signals caused by power supply noise or other interference; in addition, the overall current of the reset circuit is small, so that the overall power consumption of the reset circuit is low. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A reset circuit, the reset circuit comprising: the device comprises a voltage detection module, a reset triggering module and a reset output module; wherein,

The voltage detection module is connected between the power supply voltage and the ground and is used for detecting the power supply voltage and generating a voltage signal output;

The reset trigger module is connected with the output end of the voltage detection module and is used for generating a reset trigger signal for output according to the voltage signal when the power supply voltage rises from zero voltage to steady-state voltage or is powered down from the steady-state voltage to a voltage less than or equal to a low-voltage reset point;

The reset output module is connected with the output end of the reset trigger module and is used for generating a reset signal for output according to the reset trigger signal.

2. The reset circuit of claim 1 wherein the voltage detection module comprises: at least one first PMOS tube, a first NMOS tube, a first resistor, a second resistor and a third resistor; the gate end of the first PMOS tube is grounded through the first resistor, the source end is connected with the power supply voltage, and the drain end is connected with the first end of the second resistor and the gate end of the first NMOS tube; the second end of the second resistor is connected with the first end of the third resistor; the second end of the third resistor is connected with the drain end of the first NMOS tube and is used as the output end of the voltage detection module; and the source end of the first NMOS tube is grounded.

3. The reset circuit of claim 2, wherein when the number of the first PMOS transistors is greater than 1, the gate terminals of the plurality of first PMOS transistors after cascade connection are grounded through the first resistor, the source terminal is connected to the power supply voltage, and the drain terminal is connected to the first terminal of the second resistor and the gate terminal of the first NMOS transistor.

4. The reset circuit of claim 2 wherein the voltage detection module further comprises: and the MOS capacitor is connected between the gate end of the first NMOS tube and the ground.

5. The reset circuit of claim 1 wherein the reset trigger module comprises: the second PMOS tube, the third PMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the first inverter and the capacitor; the grid end of the second PMOS tube is connected with the grid end of the second NMOS tube and the output end of the voltage detection module, the source end of the second PMOS tube is connected with the power supply voltage, and the drain end of the second PMOS tube is connected with the drain end of the second NMOS tube and the input end of the first inverter; the source end of the second NMOS tube is grounded; the output end of the first inverter is connected with the gate end of the third NMOS tube; the source end of the third NMOS tube is grounded, and the drain end of the third NMOS tube is connected with the source end of the fourth NMOS tube and the first end of the capacitor; the gate end of the fourth NMOS tube is connected with the power supply voltage, and the drain end of the fourth NMOS tube is connected with the drain end of the third PMOS tube; the first end of the capacitor is used as the output end of the reset triggering module, and the second end of the capacitor is grounded; and the gate end of the third PMOS tube is connected with the gate end of the second PMOS tube, and the source end of the third PMOS tube is connected with the power supply voltage.

6. The reset circuit of any one of claims 1-5 wherein the reset output module comprises: an inverting schmitt trigger and a second inverter; the input end of the inverted schmitt trigger is connected with the output end of the reset trigger module, the output end of the inverted schmitt trigger is connected with the input end of the second inverter, and the output end of the second inverter is used as the output end of the reset output module.

7. The reset circuit of claim 6 wherein the voltage detection module further comprises: and the gate end of the fifth NMOS tube is connected with the output end of the reversed phase Schmidt trigger, and the source end and the drain end of the fifth NMOS tube are correspondingly connected with the two ends of the third resistor.

8. The reset circuit of any one of claims 1-5 wherein the reset output module comprises: a non-inverting schmitt trigger, a second inverter and a third inverter; the input end of the non-inverting schmitt trigger is connected with the output end of the reset trigger module, the output end of the non-inverting schmitt trigger is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter, and the output end of the third inverter is used as the output end of the reset output module.

9. The reset circuit of claim 8 wherein the voltage detection module further comprises: and the gate end of the fifth NMOS tube is connected with the output end of the second phase inverter, and the source end and the drain end of the fifth NMOS tube are correspondingly connected with the two ends of the third resistor.

10. An electronic chip, the electronic chip comprising: a reset circuit as claimed in any one of claims 1 to 9.