CN118039568A

CN118039568A - Preparation method of semiconductor structure, semiconductor structure and semiconductor device

Info

Publication number: CN118039568A
Application number: CN202410034012.XA
Authority: CN
Inventors: 吴恒; 葛延栋; 卢浩然; 孙嘉诚; 王润声; 黎明; 黄如
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2024-01-09
Filing date: 2024-01-09
Publication date: 2024-05-14

Abstract

The application provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor device, wherein the method comprises the following steps: providing a substrate, and etching the substrate to form an active structure; the active structure includes a first end and a second end, the first end of the active structure being remote from the substrate compared to the second end of the active structure; forming a first material layer on a first region of a substrate; forming a first dummy gate structure crossing the active structure on the first material layer; rewinding the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer; etching the semiconductor structure by using the first material layer as an etching mask until reaching a preset height; depositing a semiconductor material on the semiconductor structure to form a second pseudo gate structure; etching the second pseudo gate structure until the active structure of the source drain region is exposed to form a third pseudo gate structure; and removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure respectively.

Description

Preparation method of semiconductor structure, semiconductor structure and semiconductor device

Technical Field

The present application relates to the field of semiconductors, and more particularly, to a method for manufacturing a semiconductor structure, and a semiconductor device.

Background

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors further increase transistor integration density by integrating two or more layers of transistors in vertical space is one of the important technologies continuing the scaling of integrated circuits.

When the stacked transistor stacked transistor is fabricated using a conventional sequential scheme, the gate structure between the upper and lower transistors is difficult to self-align and the fabrication process is complicated.

Disclosure of Invention

The application provides a preparation method of a semiconductor structure, the semiconductor structure and a semiconductor device, which are used for realizing self-alignment of a grid structure between upper and lower layers of transistors.

The method comprises the following steps: providing a substrate, and etching the substrate to form an active structure; wherein the active structure includes a first end and a second end, the first end of the active structure being remote from the substrate compared to the second end of the active structure; forming a first material layer on a first region of a substrate, wherein the first region is positioned at grid regions at two sides of an active structure; forming a first dummy gate structure crossing the active structure on the first material layer; rewinding the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer; etching the semiconductor structure by using the first material layer as an etching mask until reaching a preset height; depositing a semiconductor material on the semiconductor structure to form a second pseudo gate structure; the height of the second dummy gate structure in the gate region is higher than that of the second dummy gate structure in the source drain region; etching the second pseudo gate structure until the active structure of the source drain region is exposed to form a third pseudo gate structure; and removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure respectively.

In some possible embodiments, etching the semiconductor structure using the first material layer as an etching mask until a predetermined height is reached, including: and selectively etching the second end of the active structure in the gate region, the second end of the active structure in the source-drain region and the shallow trench structure surrounding the active structure by using the first material layer as an etching mask until the height difference between the active structure and the first dummy gate structure reaches a preset height, and forming a first groove in the gate region.

In some possible embodiments, depositing a semiconductor material on the semiconductor structure to form a second dummy gate structure, comprising: depositing semiconductor materials on the source drain region and the grid region with the first groove in an isotropic deposition mode until the first groove is filled; etching the second dummy gate structure until the active structure of the source drain region is exposed to form a third dummy gate structure, comprising: and etching the second dummy gate structure by adopting an anisotropic etching mode until the active structure of the source drain region is exposed, and forming a third dummy gate structure in the gate region.

In some possible embodiments, removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure, respectively, includes: removing the first dummy gate structure and the third dummy gate structure; depositing a first metal material at the removed first dummy gate structure to form a first gate structure; the height of the first gate structure wraps around the first portion of the active structure; the first end is positioned at the first part; a second metal material is deposited over the first gate structure until covering the removed third dummy gate structure to form a second gate structure.

In some possible embodiments, forming a first material layer on a first region of a substrate includes: depositing a hard mask material on the etched substrate until a second groove formed by the active structure is filled up, and removing the hard mask material on the active structure by adopting a back etching process to form a second material layer; the active structure protrudes out of the second material layer; the second material layer on the source drain region is removed to form a first material layer on the first region of the substrate.

In some possible embodiments, before depositing the hard mask material on the etched substrate until the second recess formed by the active structure is filled, the method further comprises: depositing a first oxide material on the etched substrate to form an oxide layer; reversing the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer in the gate region, comprising: removing the substrate by adopting a planarization process until the second end of the active structure and the oxide layer are exposed; the oxide layer of the gate region is removed to expose the first material layer of the gate region.

In some possible embodiments, after forming a first dummy gate structure across the active structure on the first material layer, the method further comprises: depositing a second oxide material in the source drain region to form a shallow trench isolation structure, wherein the shallow trench isolation structure covers a second part of the active structure and exposes the first part of the active structure; forming a first source drain structure, a first source drain metal and a first interlayer dielectric layer in the source drain region based on the first part; etching the second dummy gate structure until the active structure of the source drain region is exposed to form a third dummy gate structure, and then the method further comprises: thinning the shallow trench isolation structure in the source drain region to expose a second portion of the active structure; and forming a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer in the source-drain region based on the second part of the active structure.

In some possible embodiments, the substrate comprises: the first substrate layer, the second substrate layer and the buried oxide layer are arranged in a stacked mode, and the buried oxide layer is located between the first substrate layer and the second substrate layer; etching the substrate to form an active structure, comprising: etching the first substrate layer, the buried oxide layer and the first part of the second substrate layer, and reserving the second part of the second substrate layer to form an active structure; wherein the first substrate layer forms a first portion of the active structure and the first portion of the second substrate layer forms a second portion of the active structure.

In a second aspect, embodiments of the present application provide a semiconductor structure that may be fabricated using the fabrication method as in any of the embodiments of the first aspect. Comprising the following steps: a first transistor; the first transistor and the second transistor are arranged in a back-to-back manner; the first active structure of the first transistor and the second active structure of the second transistor form an active structure, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

In some possible embodiments, an isolation layer is formed between the first active structure and the second active structure, the isolation layer being used to electrically isolate the first active structure and the second active structure; the isolation layer is created by a buried oxide layer in the substrate.

In a third aspect, an embodiment of the present application provides a semiconductor device including: such as the semiconductor structures of the above embodiments.

In the embodiment of the application, in the preparation process of the lower first transistor, the first material layer is arranged in the gate region, so that the gate region of the second transistor can be determined based on the position of the first material layer after rewinding, thereby realizing the self alignment of the gate structures of the upper transistor and the lower transistor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a first structure of a semiconductor structure according to an embodiment of the present application;

FIGS. 3-21 are schematic diagrams illustrating a process for fabricating a semiconductor structure according to embodiments of the present application;

FIG. 22 is a second schematic diagram of a semiconductor structure according to an embodiment of the present application;

FIG. 23 is a third schematic diagram of a semiconductor structure according to an embodiment of the present application;

Fig. 24 is a schematic view of a fourth structure of a semiconductor structure according to an embodiment of the present application;

FIGS. 25-30 are schematic diagrams illustrating another process for fabricating a semiconductor structure according to embodiments of the present application;

fig. 31 to 34 are schematic views illustrating a further process for fabricating a semiconductor structure according to an embodiment of the present application.

The figures above: 10. a semiconductor structure; 11. a first transistor; 12. a second transistor; 13. an active structure; 131. a first active structure; 132. a second active structure; 21. a substrate; 211. a fin structure; 2111. a first portion of the fin structure; 2112. a second portion of the fin structure; 22. an oxide layer; 23. a silicon nitride material layer; 24. a first dummy gate structure; 25. a first material layer; 26. shallow trench isolation structures; 27. a first spacer; 28. a first source drain structure; 29. a first interlayer dielectric layer; 30. a first source drain metal; 31. a first metal interconnect layer; 32. a first insulating layer; 33. a slide; 34. a first groove; 35. a second dummy gate structure; 36. a third dummy gate structure; 37. a second spacer; 38. a second source drain structure; 39. a second interlayer dielectric layer; 40. a metal gate structure; 401. a metal gate dielectric layer; 402. a metal gate electrode layer; 41. a first gate structure; 42. a second insulating layer; 43. a second gate structure; 44. a second source drain metal; 45. a second metal interconnect layer; 46. burying an oxide layer; 47. a nanoplatelet structure.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application.

While moore's law is continually deepening, the continued push to transistor scaling is a hot spot problem currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits.

In one embodiment, the fabrication process of the stacked transistor (stacked transistors) has two schemes, a single-chip scheme and a sequential scheme.

In the first approach, N-channel field effect transistors (N FIELD EFFECT transistors, NFETs) and P-channel field effect transistors (P FIELD EFFECT transistors, PFETs) are fabricated on the same substrate, and wafer bonding techniques are not used. This determines that the same layer transistors must be of the same type, i.e., NFET or PFET. And the transistors on the upper layer and the lower layer are strictly in the same plane space, and no alignment deviation exists. The advantage of this solution is a better integration density. Drawbacks of this approach include the following two points: (1) The process is complex, and a large number of process technologies need to be developed and optimized; (2) Each layer of transistors has a fixed polarity, and two layers of transistors must be relied upon to form a basic Complementary Metal Oxide Semiconductor (CMOS) circuit, which has poor design flexibility.

The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, the two transistors are stacked vertically by bonding a wafer on top of the fabricated lower transistor to prepare the upper transistor. However, this approach requires tight temperature control during the thermal process of processing the upper layer transistors, avoiding affecting the lower layer transistors and the interconnect lines. The scheme has the advantages that the device structure, the channel crystal orientation and even the channel material adopted by the upper layer transistor and the lower layer transistor can be correspondingly optimized to obtain better and more matched device performance due to wafer bonding.

The above-described solution currently presents challenges: because the preparation process is fixed, the alignment between the upper layer transistor and the lower layer transistor is difficult.

In order to solve the above technical problems, an embodiment of the present application provides a method for manufacturing a semiconductor structure, so as to realize self-alignment of a gate structure between an upper transistor and a lower transistor.

In the embodiment of the application, the semiconductor structure can be applied to semiconductor devices such as memories, processors and the like.

In an embodiment, the semiconductor structure may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged opposite to each other. The first active structure in the first transistor and the second active structure in the second transistor are formed through the same process, and at this time, it can be understood that the first transistor is self-aligned with the second transistor.

In the embodiment of the application, the first transistor and the second transistor in the semiconductor structure may be transistors of the same type, such as any one of the following: fin field effect transistors, fully surrounding gate transistors and planar transistors.

Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a semiconductor structure according to an embodiment of the present application, and referring to fig. 1, the method for manufacturing a semiconductor structure may include:

s101, providing a substrate and etching the substrate to form an active structure.

Wherein the active structure includes a first end and a second end, the first end of the active structure being remote from the substrate compared to the second end of the active structure.

It should be noted that, when the transistor in the semiconductor structure is a fin field effect transistor, the active structure is a fin structure; when the transistor in the semiconductor structure is a fully-surrounding gate transistor, the active structure is a nano-sheet structure; when the transistors in the semiconductor structure are planar transistors, the active structure is a bulk structure.

In an embodiment, the substrate may be a silicon (Si) substrate, or may be a silicon-on-insulator (SOI) substrate, or may be a substrate made of other semiconductor materials, which is not limited in particular by the embodiment of the present application.

It will be appreciated that when the types of semiconductor structures are different, the arrangement of the substrates is correspondingly different. For example, when the semiconductor structure is a fin field effect transistor or a planar transistor, the semiconductor substrate may be a single-layer structure, i.e., a substrate made of one semiconductor material is used; when the semiconductor structure is a fully-around gate transistor, the semiconductor substrate may be a stacked structure, i.e., a stack in which a Si material and a silicon germanium (SiGe) material are stacked.

In some embodiments, when the semiconductor structure is a finfet, the S101 may include: and etching the substrate to form a plurality of fin structures.

In other embodiments, when the semiconductor structure is a fully-around gate transistor, the S101 may include: the substrate is etched to form a columnar structure, wherein the substrate may be formed of alternately deposited silicon layers and silicon germanium layers.

In still other embodiments, when the semiconductor structure is a planar transistor, the S101 may include: and etching the substrate to form a block structure.

In the embodiment of the application, since the semiconductor structure comprises two transistors, and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be adopted when the semiconductor substrate is etched. For example, the height of the etched fin structure (which may also be a columnar structure or a bulk structure) may be greater than 100nm. It should be noted that the height of the fin structure may be set according to practical situations, which is not particularly limited in the embodiment of the present application.

In an embodiment, the substrate may be an SOI substrate comprising: the first substrate layer, the second substrate layer and the buried oxide layer are stacked, and the buried oxide layer is located between the first substrate layer and the second substrate layer. The S101 may include: and etching the first substrate layer, the buried oxide layer and the first part of the second substrate layer, and reserving the second part of the second substrate layer to form an active structure.

Wherein the first substrate layer forms a first portion of the active structure (i.e., a first active structure of the first transistor) and the first portion of the second substrate layer forms a second portion of the active structure (i.e., a second active structure of the second transistor). The first portion of the active structure is remote from the substrate than the second portion of the active structure, the first end of the active structure is at an end of the first portion, and the second end of the active structure is at an end of the second portion.

In one embodiment, the SOI substrate comprising the buried oxide layer may be formed by a variety of fabrication processes, as embodiments of the present application are not limited in detail. For example, the SOI substrate with the buried oxide layer is prepared by sequentially carrying out preparation of the buried oxide layer, hydrogen ion implantation, bonding and splitting processes on a monocrystalline silicon wafer; or by implanting oxygen ions to a depth below the wafer surface. And after ion implantation, forming a layer of buried silicon dioxide (buried oxide layer) in the silicon wafer through high-temperature annealing.

S102, forming a first material layer on a first area of a substrate.

The first region is located in the grid regions on two sides of the active structure.

It is understood that after etching the substrate to form the active structure, the first material layer may be formed based on the etched substrate. Wherein the first material layer is located in the first region, that is, the first material layer is located in the gate region in the semiconductor structure, and the first material layer does not cover the active structure but is located at two sides of the active structure.

It should be noted that the semiconductor structure includes a gate structure crossing the active structure, and the location of the gate structure may be divided into gate regions of the semiconductor structure. The semiconductor structure further comprises source and drain structures located on two sides of the gate structure, and the position of the source and drain structures can be divided into source and drain regions of the semiconductor structure. The gate region and the source and drain region may be disposed at intervals.

In some embodiments, the step S102 may include: depositing a hard mask material on the etched substrate until a second groove formed by the active structure is filled up, and removing the hard mask material on the active structure by adopting a back etching process to form a second material layer; the second material layer on the source drain region is removed to form a first material layer on the first region of the substrate.

The active structure protrudes from the second material layer, which is also understood to be a second material layer surrounding the second end of the active structure but not covering the active structure.

It can be appreciated that after the second material layer located on the source drain region is removed, the second material layer remains in the gate region on the semiconductor structure, and the remaining second material layer is the first material layer.

In one embodiment, the first material layer may be used as a hard mask in a subsequent etching process. The hard mask material forming the first material layer may be a material having high corrosion resistance and hardness, for example, silicon nitride (SiN), silicon dioxide (SiO ₂), or the like.

In other embodiments, the step S102 may include: depositing a first oxide material on the etched substrate to form an oxide layer; and depositing a hard mask material on the oxide layer until filling up a second groove formed by the active structure, and removing the hard mask material on the active structure by adopting a back etching process to form the second material layer.

It will be appreciated that the first oxide material may be deposited to form the oxide layer prior to forming the first material layer. The oxide layer can protect the active structure, so that on one hand, the first material layer is prevented from being in direct contact with the substrate to generate larger stress; for example, when the active structure is a fin structure, the oxide layer can avoid stress between the first material layer and the substrate from collapsing the fin structure; on the other hand, the oxide layer can also protect the surface (such as interface state and the like) of the active structure.

The first oxide material may be silicon dioxide (SiO 2), silicon oxycarbide (SiCO), or the like, which is not particularly limited in the embodiment of the present application.

S103, forming a first pseudo gate structure crossing the active structure on the first material layer.

It is understood that a first dummy gate structure may be formed by depositing a semiconductor material on the first material layer. Wherein the first dummy gate structure spans the active structure and encapsulates the active structure.

In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon.

In some embodiments, after forming the first dummy gate structure, spacers may be formed on both sides of the first dummy gate structure.

In some embodiments, after S103 above, it may include: depositing a second oxide material in the source drain region to form a shallow trench isolation structure, wherein the shallow trench isolation structure covers a second part of the active structure and exposes the first part of the active structure; and forming a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer in the source-drain region based on the first part.

It is appreciated that after formation of the dummy gate structure, a second oxide material may be deposited within the source and drain regions to form shallow trench isolation structures (shallow trench isolation, STI). The height of the shallow trench isolation structure is such that the shallow trench isolation structure covers the second portion of the active structure, exposing the first portion of the active structure.

It will be appreciated that for subsequent fabrication of the semiconductor structure on the active structure, such as for the fabrication of the first source drain structure, etc., the shallow trench isolation structure may be etched such that a first portion of the active structure is exposed for subsequent fabrication processes.

In the embodiment of the present application, the second oxide material forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, si ₃N₄), silicon dioxide (SiO ₂), silicon oxycarbide (SiCO), or the like.

It should be noted that, the etching process mentioned in the embodiment of the present application may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal processes, to which embodiments of the present application are not limited.

In some embodiments, after exposing the first portion of the active structure, ion implantation may be performed at the junction of the first portion of the active structure and the second portion of the active structure to form an electrical isolation layer for electrically isolating the first portion of the active structure (first active structure) and the second portion of the active structure (second active structure).

Wherein the ion implanted ions comprise P-type ions, N-type ions or oxygen ions. The P-type ion may be one of: boron (B), gallium (Ga), aluminum (Al). The N-type ion may be one of: phosphorus (P), arsenic (As), antimony (Sb).

It should be noted that when the buried oxide layer is provided in the substrate, the buried oxide layer may form a natural electrical isolation between the first portion and the second portion, thereby eliminating the need for ion implantation at the junction of the first portion and the second portion.

It is appreciated that after exposing the first portion of the active structure, a first source drain metal, and a first interlayer dielectric layer may be formed in the source drain region based on the first portion of the active structure.

The first interlayer dielectric layer can wrap the first active structure, the first source drain structure and the first source drain metal.

It should be noted that, the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer may be formed by standard steps of a semiconductor manufacturing process, which is not limited in particular in the embodiment of the present application.

Illustratively, a source drain recess may be formed in the first portion of the exposed active structure. And (3) carrying out source-drain epitaxial growth at the source-drain groove to obtain a first source-drain structure. And depositing a metal material above the first source drain structure to obtain the first source drain metal. And depositing a semiconductor material above the first active structure to obtain a first interlayer dielectric layer.

Illustratively, the source-drain recess of the first semiconductor structure may be provided by etching away a portion of the first active structure. And forming a strained material such as silicon germanium or silicon carbide in the source-drain grooves by selective epitaxial growth to fill the source-drain grooves of the first semiconductor structure, and then forming the first source-drain structure on the strained material by a heavy doping process.

It should be noted that, for convenience of description, the first source-drain structure in the embodiment of the present application is referred to as simply, and specifically refers to a first source structure and/or a first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove and the like are similar to those of the first source-drain structure, wherein 'source-drain' is abbreviated as 'source electrode and/or drain electrode'.

In some embodiments, after the step S103, the method further includes: and finishing the subsequent structure through standard steps of a semiconductor preparation process, and bonding the formed semiconductor structure with a wafer carrier.

It will be appreciated that subsequent processing (e.g., dielectric deposition between interconnect lines, metal line formation, formation of an extraction pad, etc.) may be performed on top of the first interlayer dielectric layer and the first dummy gate structure after forming the first interlayer dielectric layer to form a first metal interconnect layer of the first transistor. An insulating material (e.g., silicon oxide) is deposited over the first metal interconnect layer to form a first insulating layer and the first insulating layer is bonded to the carrier wafer.

In the embodiment of the application, the first semiconductor structure is bonded with the carrier wafer, so that physical support can be provided for the inverted semiconductor structure after the carrier wafer is inverted, and the situation that the first semiconductor structure is broken due to external force in the process of preparing the second transistor is effectively prevented.

S104, rewinding the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer.

It will be appreciated that the semiconductor structure formed in S103 above may be reworked such that the substrate of the semiconductor structure is placed upwards, and then the substrate is removed by etching. After the substrate is removed, the second end of the active structure and the first material layer formed at S102 may be exposed.

Wherein the first material layer is located on two sides of the active structure of the gate region.

In some implementations, when an oxide layer is formed on the substrate, S104 may include: removing the substrate by adopting a planarization process until the second end of the active structure and the oxide layer are exposed; the oxide layer of the gate region is removed to expose the first material layer of the gate region.

It will be appreciated that the second end of the active structure and the oxide layer may be exposed by subjecting the substrate to a chemical-mechanical planarization (CMP) process, followed by etching the oxide layer of the gate region, which may expose the first material layer.

And S105, etching the semiconductor structure by using the first material layer as an etching mask until the preset height is reached.

It can be appreciated that the first material layer is used as an etching mask, so that the first dummy gate structure at the bottom of the first material layer can be protected from being etched, and the rest of structures which are not covered by the first material layer can be etched to a preset height.

Here, the preset height is smaller than the height of the second portion of the active structure. The predetermined height is correlated to the width of the active region to ensure that a recess having a predetermined aspect ratio is formed in the gate region and to ensure that the second portion of the active structure is high enough for the back side transistor to be used.

Illustratively, when preparing a 10nm wide fin transistor, the predetermined height is 5-10nm.

In an embodiment, the step S105 may include: and selectively etching the second end of the active structure in the gate region, the second end of the active structure in the source-drain region and the shallow trench structure surrounding the active structure by using the first material layer as an etching mask until the height difference between the active structure and the first dummy gate structure reaches a preset height, and forming a first groove in the gate region.

It will be appreciated that by selectively etching the second end of the active structure in the gate region, the height of the first dummy gate structure in the gate region may be made constant, and the active structure of the gate region is etched away by a predetermined height, thereby forming a first recess in the gate region. The position of the first groove corresponds to the position of the active structure. The second end of the active structure in the source-drain region and the shallow trench structure surrounding the active structure are selectively etched, so that the whole structure in the source-drain region is etched to a preset height, and the height of the source-drain region is the same as the height of the bottom of the first groove.

In the semiconductor structure formed in S105, the first dummy gate structure of the gate region has a height higher than that of the other structures.

In some embodiments, after S105 above, the method may further include: the first material layer is removed.

It will be appreciated that the first material layer is used to locate the gate region and as an etch mask in an etching process. After the etching is completed in S105, the first dummy gate structure of the gate region has a height higher than that of the source/drain region, and the gate region may be initially located, at this time, the first material layer may be removed.

And S106, depositing a semiconductor material on the semiconductor structure to form a second pseudo gate structure.

Wherein the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source drain region.

It will be appreciated that by depositing semiconductor material on the semiconductor where the height of the first dummy gate is higher in the gate region of the semiconductor structure formed at S105 than elsewhere, the height of the second dummy gate structure formed must be higher in the gate region than in the source drain region.

Here, the semiconductor material of the second dummy gate structure formed may be the same as that of the first dummy gate structure, and may be, for example, polysilicon, silicon nitride, or amorphous carbon.

In some embodiments, S106 may include: depositing semiconductor materials on the source drain region and the grid region with the first groove in an isotropic deposition mode until the first groove is filled; and etching the polysilicon by adopting an anisotropic etching mode until the active structure of the source drain region is exposed, and forming a third pseudo gate structure in the gate region.

It will be appreciated that since the semiconductor material is deposited using an isotropic process, polysilicon will also be deposited on the sidewalls of the first recess formed in the gate region, and thus the deposition rate at the first recess will be higher than the deposition rate at the source and drain regions. Thus, after the first groove is filled, the height of the second dummy gate structure at the first groove is higher than that of the source-drain region, namely the second dummy gate structure of the gate region is higher than that of the source-drain region.

Further, based on the characteristic that the second pseudo gate structure of the gate region is higher than the second pseudo gate structure of the source drain region, the gate region and the source drain region can be distinguished, and the position of the gate region can be acquired in a self-aligned manner, so that the self-aligned pseudo gate structure can be formed in a subsequent step.

And S107, etching the second pseudo gate structure until the active structure of the source drain region is exposed, so as to form a third pseudo gate structure.

It will be appreciated that, since the height of the second dummy gate structure in the gate region is higher than that in the source drain region, etching S106 the second dummy gate structure will first expose the active structure of the source drain region. When the active structure of the source drain region is exposed, etching can be stopped, and the second dummy gate structure of the gate region is reserved at this time, namely, a third dummy gate structure is formed.

In some embodiments, the step S107 may include: and etching the second dummy gate structure by adopting an anisotropic etching mode until the active structure of the source drain region is exposed, and forming a third dummy gate structure in the gate region.

It can be appreciated that the second dummy gate structure is etched by adopting an anisotropic etching process, and the height difference of the second dummy gate structure of the gate region and the source drain region is not changed, so that the second dummy gate structure of the source drain region can be removed, and the crystalline silicon structure (third dummy gate structure) of the gate region is reserved, thereby forming a dummy gate structure with self-aligned semiconductor structure, namely, the first dummy gate structure and the third dummy gate structure are self-aligned.

In some embodiments, after S107 above, it may include: thinning the shallow trench isolation structure in the source drain region to expose a second portion of the active structure; and forming a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer in the source-drain region based on the second part of the active structure.

Here, the process of forming the second source-drain structure, the second source-drain metal and the second interlayer dielectric layer may refer to the process of forming the first source-drain structure, the first source-drain metal and the first interlayer dielectric layer, which are not described herein for brevity of the description.

S108, removing the first pseudo gate structure and the third pseudo gate structure to form a first gate structure and a second gate structure respectively.

It will be appreciated that after forming the self-aligned first and third dummy gate structures, the first and third dummy gate structures may be removed and a metal material deposited to form the first and second gate structures, respectively.

It should be noted that the first gate structure and the second gate structure may be formed by standard steps of a semiconductor manufacturing process, which is not particularly limited in the embodiment of the present application.

In the embodiment of the present application, the metal materials of the first gate structure and the second gate structure may be any of the following: the materials of the tantalum nitride (TaN), the titanium nitride (TiN), the aluminum nitride (AlN), the titanium aluminum carbide (TiAlC), the titanium aluminum nitride (TiAlN), the first gate structure and the second gate structure may be selected according to actual situations, and are not limited to the above listed metal materials.

In the embodiment of the present application, the materials of the first gate structure and the second gate structure may be made of the same or different metal materials according to practical situations, which is not particularly limited in the embodiment of the present application.

In some embodiments, S108 may include: removing the first dummy gate structure and the third dummy gate structure, and depositing a first metal material at the removed first dummy gate structure to form a first gate structure; the height of the first gate structure wraps around the first portion of the active structure; a second metal material is deposited over the first gate structure until covering the removed third dummy gate structure to form a second gate structure.

Wherein the first end of the active structure is located at the first portion. The first portion of the active structure is used to form a first transistor.

It will be appreciated that depositing a first metal material at the first dummy gate structure, forming the first gate structure, and wrapping the first gate structure around the first portion of the active structure, exposing the second portion of the active structure, may enable the formation of the first transistor based on the first portion of the active structure. A second metal material is deposited over the first gate structure until the second metal material covers the removed third gate structure, forming a second gate structure such that the second gate structure wraps around a second portion of the active structure, thereby enabling formation of a second transistor based on the second portion of the active structure. In the above process, the first dummy gate structure and the third dummy gate structure are self-aligned, so that the first gate structure and the second gate structure are self-aligned.

Here, the first metal material is different from the second metal material.

In an embodiment, the step S108 may include: removing the first dummy gate structure and the third dummy gate structure to form a metal gate; and selectively etching the upper half metal gate, and reserving the lower half metal gate to form a first gate structure. An insulating medium is deposited over the first gate structure to form an insulating layer. The insulating layer is used for isolating the first gate structure of the first transistor and the second gate structure of the second transistor. A metal material is deposited over the insulating layer to form a second gate structure.

Wherein, the metal gate may include: a gate dielectric layer and a gate electrode layer.

In one embodiment, etching the upper half metal gate may include: the gate electrode layer of the upper half is etched. The gate dielectric layer and the gate electrode layer in the lower half form a first gate structure. The gate dielectric layer of the upper half and the metal material deposited on the upper half form a second gate structure.

In an embodiment, etching the upper half metal gate may further include: and etching the upper gate dielectric layer and the upper gate electrode layer. And directly forming a second gate structure when a metal material is deposited on the insulating layer.

In some embodiments, after S108 above, the method further comprises: and finishing the subsequent structure through standard steps of a semiconductor preparation process to form the semiconductor structure in the embodiment of the application.

It will be appreciated that subsequent processing (e.g., dielectric deposition between interconnect lines, metal line formation, bond pad formation, etc.) may be performed on top of the second source drain metal and the second gate structure after forming the first gate structure and the second gate structure to form a second metal interconnect layer for the second transistor.

In the embodiment of the application, the active structures of the two transistors can be formed by one process by providing a substrate and forming the active structures on the substrate; the first transistor is formed by using the first part of the active structure, and the second transistor is formed by using the second part of the active structure after rewinding, so that the upper layer transistor and the lower layer transistor are self-aligned.

In addition, in the preparation process of the lower first transistor, the first material layer is arranged in the gate region, so that the gate region of the second transistor can be determined based on the position of the first material layer after rewinding, and the self-alignment of the gate structures of the upper transistor and the lower transistor is realized.

The following describes a method for manufacturing a semiconductor structure according to the embodiment of the present application, taking an active structure in the semiconductor structure as a fin structure as an example. Fig. 2 is a schematic diagram of a first structure of a semiconductor structure according to an embodiment of the present application. In fig. 2 (a) is a top view of the semiconductor structure, it should be noted that, for ease of understanding, only fin structures, gate structures, and source/drain structures are shown in the top view; fig. 2 (b) is a cross-sectional view of the semiconductor structure taken along the tangential direction (i.e., the A-A' direction) of the gate structure; fig. 2 (c) is a cross-sectional view of the semiconductor structure taken along the tangential direction (i.e., the B-B' direction) of the source-drain structure; fig. 2 (d) is a cross-sectional view of the semiconductor structure taken along the tangential direction (i.e., the C-C' direction) of the fin structure.

Referring to fig. 2, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin structures. The fin structure is divided into an upper and a lower part, denoted as a first part, which serves as a first active structure in the first transistor 11, and a second part, which serves as a second active structure in the second transistor 12. Self-alignment between the first gate structure 41 in the first transistor 11 and the second gate structure 43 in the second transistor 12.

Here, self-alignment refers to the alignment of the first gate structure 41 and the second gate structure 43 during the fabrication process.

The process of fabricating the semiconductor structure shown in fig. 2 will be described below in conjunction with the above-described fabrication method. Fig. 3 to 21 are schematic views illustrating a process for fabricating a semiconductor structure according to an embodiment of the present application, wherein (a) in fig. 3 to (a) are cross-sectional views of the semiconductor structure along a tangential direction (i.e., A-A 'direction) of the gate structure, and (B) in fig. 3 to (B) in fig. 21 are cross-sectional views of the semiconductor structure along a tangential direction (i.e., B-B' direction) of the source/drain structure; fig. 3 (C) to 21 (C) are sectional views of the semiconductor structure along the sectional direction (i.e., C-C') of the fin structure.

In one example, one fabrication process of semiconductor structure 10 may include the steps of:

the first step: the fin structure 211 is patterned and etched on the silicon substrate 21 by standard steps of a semiconductor fabrication process to obtain the structure shown in fig. 3.

It is noted that the fin structure 211 may have a height greater than 100nm.

And a second step of: depositing an oxide material over the structure shown in fig. 3 to form an oxide layer 22 of the fin structure; silicon nitride is then deposited over oxide layer 22 and etched back to form a layer of silicon nitride material over the substrate, resulting in the structure shown in fig. 4.

And a third step of: the gate region of the structure shown in fig. 4 is opened by photolithographic development and polysilicon is deposited over the gate region as a first dummy gate structure 24 to obtain the structure shown in fig. 5.

Here, the first dummy gate structure 24 spans the plurality of fin structures 211 in the A-A' direction; in the direction of C-C', are distributed at intervals.

Fourth step: the silicon nitride material layer 23 is removed in the areas not covered by the dummy gate, resulting in the structure shown in fig. 6.

It will be appreciated that the layer of silicon nitride material that is not removed forms the first material layer 25 and that the first material layer 25 covers the first region.

Here, the first region is located at the gate region at both sides of the fin structure 211.

Fifth step: depositing an oxide material in a source-drain region in the structure shown in fig. 6 to form a first shallow trench isolation layer; the first shallow trench isolation layer is etched to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The upper surface of the shallow trench isolation structure 26 is lower in height than the first portion 2111 (top) of the fin structure 211, resulting in the structure shown in fig. 7.

Sixth step: in the gate region of the structure shown in fig. 7, the formation of the first spacers 27 of the first transistor 11 is completed by standard steps of the semiconductor fabrication process; in the source-drain region in the structure shown in fig. 7, the first source-drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are completed by standard steps of a semiconductor manufacturing process, resulting in the structure shown in fig. 8.

Seventh step: the source and drain regions in the structure shown in fig. 8 complete the first source and drain metal 30 of the first transistor 11 and the subsequent interconnect process of the first transistor 11 is completed over the source and drain regions and the gate region, forming a first metal interconnect layer 31. The first metal interconnection layer 31 communicates with the first source drain metal 30, resulting in the structure shown in fig. 9.

Eighth step: depositing an insulating oxide over the structure shown in fig. 9, forming a first insulating layer 32; over the first insulating layer 32, a carrier 33 is bonded to the first transistor 11, followed by rewinding, resulting in the structure shown in fig. 10.

Ninth step: wafer thinning is performed and a chemical mechanical planarization process is used to selectively stop over oxide layer 22, thereby exposing the ends of second portions 2112 of fin structure 211, resulting in the structure shown in fig. 11.

Tenth step: the oxide layer 22 and fin structure 211 are etched using a selective etch process to etch away at least a predetermined height to obtain the structure shown in fig. 12.

Here, the first material layer 25 of the first region may serve as an etching mask to protect the first dummy gate structure 24 at the bottom of the first material layer 25 from being etched. So that the gate region forms a plurality of first recesses 34 in the A-A' direction. The groove depth of the first groove 34 is equal to the preset height.

Eleventh step: polysilicon is deposited on the structure shown in fig. 12 using isotropic deposition to obtain the structure shown in fig. 13.

It should be noted that, since the deposition manner is isotropic deposition, the deposition is also performed on the sidewall of the first recess 34 in the gate region, and thus the deposition thickness at the first recess 34 (as shown by the solid arrow in fig. 13) is higher than that at the source-drain region (as shown by the dashed arrow in fig. 13). The polysilicon of the gate region may be higher than the polysilicon of the source drain region when viewed in cross-section of the fin structure (fig. 13 (c)).

Further, the deposition of polysilicon is continued until the first recess 34 of the gate region is filled to obtain the structure shown in fig. 14.

Note that, after the first recess 34 of the gate region is filled, the second dummy gate structure 35 is formed. The height of the second dummy gate structure 35 in the gate region (as indicated by the solid arrows in fig. 14) is higher than the height of the second dummy gate structure 35 in the source drain region (as indicated by the broken arrows in fig. 14) when viewed in the cross section of the fin structure (fig. 14 (c)).

Twelfth step: the second dummy gate structure 35 in the structure shown in fig. 14 is etched by anisotropic etching until the polysilicon in the source and drain regions is completely removed, leaving only the polysilicon in the gate region, resulting in the structure shown in fig. 15.

It should be noted that, since an anisotropic etching manner is adopted, the height difference between the polysilicon in the gate region and the polysilicon in the source/drain region will not change, and when the polysilicon in the source/drain region is etched, the polysilicon still exists in the gate region. The polysilicon of the gate region may constitute a third dummy gate structure 36.

Note that the third dummy gate structure 36 is located in the gate region so as to be self-aligned with the first dummy gate structure 24.

Thirteenth step: the first material layer 25 over the structure shown in fig. 15 is removed and the shallow trench isolation structure 26 is selectively etched, thereby exposing the second portion 2112 of the fin structure 211, resulting in the structure shown in fig. 16.

It should be noted that the second portion 2112 of the exposed fin structure 211 is formed by the same process as the first portion 2111 of the fin structure 211, so that the fin structures 211 of the first transistor 11 and the second transistor 12 are homologous, and thus the active structure is formed to be self-aligned without additional photolithography during the process of forming the second transistor 12.

In an embodiment, the first material layer 25 may be removed prior to the eleventh step.

Fourteenth step: in the gate region of the structure shown in fig. 16, the formation of the second spacer 37 of the second transistor 12 is completed by standard steps of the semiconductor fabrication process; in the source and drain regions of the structure shown in fig. 15, the second source and drain structure 38 and the second interlayer dielectric layer 39 of the second transistor 12 are completed by standard steps of the semiconductor fabrication process, resulting in the structure shown in fig. 17.

Fifteenth step: the first 24 and third 36 dummy gate structures are removed and a metal material is deposited at the locations of the first 24 and third 36 dummy gate structures to form a metal gate structure 40, resulting in the structure shown in fig. 18.

Note that the metal gate structure 40 may include a metal gate dielectric layer 401 and a metal gate electrode layer 402.

Sixteenth step: the metal gate structure 40 in the structure shown in fig. 18 is selectively etched to remove the metal gate structure 40 in the region of the second transistor 12, resulting in the structure shown in fig. 19.

It should be noted that, this step may only etch the metal gate electrode layer 402 in the metal gate structure 40.

In some embodiments, metal gate dielectric layer 401 and metal gate electrode layer 402 in metal gate structure 40 may be etched.

Note that the metal gate structure 40 in the region of the first transistor 11 that is left may form the first gate structure 41.

Seventeenth step: an insulating material is deposited over the first gate structure 41 to form a second insulating layer 42, resulting in the structure shown in fig. 20.

Eighteenth step: a metal material is deposited over the second insulating layer 42 forming a second gate structure 43 of the second transistor 12 resulting in the structure shown in fig. 21.

Here, the first gate structure 41 of the first transistor 11 and the second gate structure 43 of the second transistor 12 may be self-aligned.

Note that the second insulating layer 42 is used for electrical isolation of the first gate structure 41 and the second gate structure 43.

Nineteenth step: the source and drain regions in the structure shown in fig. 21 complete the second source and drain metal 44 of the second transistor 12 and the subsequent interconnect process of the second transistor 12 is completed over the source and drain regions and the gate region, forming a second metal interconnect layer 45. The second metal interconnection layer 45 communicates with the second source drain metal 44, resulting in the structure shown in fig. 2.

Thus, the first transistor and the second transistor are completed and the alignment of the first gate structure 41 and the second gate structure 43 is achieved.

In one example, fig. 22 is a second structural schematic diagram of a semiconductor structure in an embodiment of the present application. Wherein (a) in fig. 22 is a cross-sectional view of the semiconductor structure along a cross-sectional direction (i.e., A-A 'direction) of the gate structure, and (B) in fig. 22 is a cross-sectional view of the semiconductor structure along a cross-sectional direction (i.e., B-B' direction) of the source/drain structure; fig. 22 (C) is a cross-sectional view of the semiconductor structure along the cross-sectional direction (i.e., the C-C' direction) of the fin structure.

The second semiconductor structure differs from the first semiconductor structure in that the substrate 21 in the second semiconductor structure 10 may include: the first substrate layer, the second substrate layer, and the buried oxide layer 46 are stacked. Wherein buried oxide layer 46 is located between the first substrate layer and the second substrate layer. Such as a silicon-on-insulator (SOI) substrate.

A first substrate layer in a second semiconductor structure may be used to form a first portion 2111 of the fin structure and a second portion in the second substrate layer may form a second portion 2112 that may be used for the fin structure, such that electrical isolation may be achieved with buried oxide layer 46 between first portion 2111 of the fin structure and second portion 2112 of the fin structure.

In an example, fig. 23 is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application. Fig. 24 is a schematic view of a fourth structure of a semiconductor structure according to an embodiment of the present application. Wherein (a) in fig. 23 to (24) is a cross-sectional view of the semiconductor structure along a cross-sectional direction (i.e., A-A 'direction) of the gate structure, and (B) in fig. 23 to (24) is a cross-sectional view of the semiconductor structure along a cross-sectional direction (i.e., B-B' direction) of the source/drain structure; fig. 23 (C) to 24 (C) are sectional views of the semiconductor structure along the tangential direction (i.e., the C-C' direction) of the active structure.

As shown in fig. 23 and 24, the first transistor 11 and the second transistor 12 are disposed opposite to each other. The first active structure 131 of the first transistor 12 and the second active structure 132 of the second transistor 12 constitute the active structure 13, and the first gate structure 41 of the first transistor 11 and the second gate structure 43 of the second transistor 12 are self-aligned. Wherein the active structure in fig. 23 may be a nano-sheet structure, and the active structure in fig. 24 may be a bulk structure.

It should be noted that the semiconductor structures shown in fig. 22 to 24 may be prepared by steps in one or more embodiments corresponding to fig. 1, which are not repeated for brevity of description.

The fabrication process of the semiconductor structure shown in fig. 23 is briefly described below in connection with the steps in one or more embodiments corresponding to fig. 1. Fig. 25 to 30 are schematic views illustrating another process for fabricating a semiconductor structure according to an embodiment of the present application, wherein (a) in fig. 25 to (a) in fig. 30 are cross-sectional views of the semiconductor structure along a cross-sectional direction (i.e., A-A 'direction) of the gate structure, and (B) in fig. 25 to (B) in fig. 30 are cross-sectional views of the semiconductor structure along a cross-sectional direction (i.e., B-B' direction) of the source/drain structure; fig. 25 (C) to 30 (C) are sectional views of the semiconductor structure along the sectional direction (i.e., C-C' direction) of the nano-sheet structure.

In one example, another process for fabricating semiconductor structure 10 may include the steps of:

The first step: patterning and etching to form nanoplatelet structures 47 on silicon substrate 21 by standard steps of a semiconductor fabrication process; depositing silicon nitride on the substrate 21 with the nanoplatelet structures 47 formed thereon, and back-etching the silicon nitride so that a layer of silicon nitride material is formed on the substrate; depositing polysilicon on the gate region of the semiconductor structure 10 as a first dummy gate structure 24; removing the silicon nitride material layer of the region (source drain region) not covered by the first dummy gate structure 24 to form a first material layer 25; depositing oxide materials in the source-drain region to form a first shallow trench isolation layer; the first shallow trench isolation layer is etched to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The upper surface of the shallow trench isolation structure 26 is lower in height than the first portion of the nano-sheet structure 47 (the first active structure 131 in fig. 23 is subsequently formed), resulting in the structure shown in fig. 25.

And a second step of: in the gate region in the structure shown in fig. 25, the formation of the first spacer 27 of the first transistor 11 is completed by standard steps of the semiconductor manufacturing process; in the source drain region, the first source drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are completed by standard steps of a semiconductor manufacturing process. Subsequently, the first source-drain metal 30 of the first transistor 11 is completed in the source-drain region, and the subsequent interconnection process of the first transistor 11 is completed over the source-drain region and the gate region, forming the first metal interconnection layer 31. The first metal interconnection layer 31 communicates with the first source drain metal 30, resulting in the structure shown in fig. 26.

And a third step of: depositing an insulating oxide over the structure shown in fig. 26, forming a first insulating layer 32; over the first insulating layer 32, a carrier 33 is bonded to the first transistor 11. And then rewound and wafer thinning is performed, stopping over the first material layer 25 using a chemical mechanical planarization process, thereby exposing the end of the second portion of the nanoplatelet structure 47, resulting in the structure shown in fig. 27.

Fourth step: the nanoplatelet structures 47 not covered by the first material layer 25 are etched using a selective etching process, at least to a predetermined height, resulting in the structure shown in fig. 28.

Here, the first material layer 25 of the first region may serve as an etching mask to protect the first dummy gate structure 24 at the bottom of the first material layer 25 from being etched. So that the gate region forms a first recess 34 in the A-A' direction. The groove depth of the first groove 34 is equal to the preset height.

Fifth step: the first material layer 25 is removed and polysilicon is deposited using an isotropic deposition process to obtain the structure shown in fig. 29.

It should be noted that, since the deposition manner is isotropic deposition, the deposition is also performed on the sidewall of the first recess 34 in the gate region, and thus the deposition thickness at the first recess 34 is higher than that at the source-drain region. The polysilicon of the gate region may be higher than the polysilicon of the source drain region when viewed in cross-section of the fin structure. Further, the deposition of polysilicon is continued until the first recess 34 of the gate region is filled to obtain the structure shown in fig. 29.

Note that, after the first recess 34 of the gate region is filled, the second dummy gate structure 35 is formed. The height of the second dummy gate structure 35 in the gate region is higher than the height of the second dummy gate structure 35 in the source drain region when viewed in the cross section of the fin structure (fig. 29 (c)).

Sixth step: the second dummy gate structure 35 in the structure shown in fig. 29 is etched by anisotropic etching until the polysilicon in the source and drain regions is completely removed, leaving only the polysilicon in the gate region, and forming a third dummy gate structure 36, resulting in the structure shown in fig. 30.

Seventh step: in the gate region of the structure shown in fig. 30, the formation of the second spacer 37 of the second transistor 12 is completed by standard steps of the semiconductor fabrication process; in the source drain region of the structure shown in fig. 15, the second source drain structure 38 and the second interlayer dielectric layer 39 of the second transistor 12 are completed based on the second portion of the nano-sheet structure 47 (the second active structure 132 in fig. 23 is subsequently formed) by standard steps of the semiconductor manufacturing process. Subsequently, the first and third dummy gate structures 24 and 36 are removed, and first and second gate structures are formed at the positions of the first and third dummy gate structures 24 and 36. Subsequently, the second source-drain metal 44 of the second transistor 12 is completed in the source-drain region, and a subsequent interconnection process of the second transistor 12 is completed over the source-drain region and the gate region, forming a second metal interconnection layer 45. The second metal interconnection layer 45 communicates with the second source drain metal 44, resulting in the structure shown in fig. 23.

In some possible embodiments, when the active structure is a nano-sheet structure, the semiconductor material forming the nano-sheet structure and the semiconductor material forming the first dummy gate structure may be materials with high etching selectivity, so that the first material layer is not required to be formed in the preparation process of the semiconductor structure, and only after rewinding, the nano-sheet structure is etched by adopting a selective etching process, without etching the first dummy gate structure, so that a first groove is formed at the nano-sheet structure, and further, a second dummy gate structure which is self-aligned with the first dummy gate structure is formed.

In this process, the first material layer does not need to be formed as a hard mask, so that the complexity of the manufacturing process of the semiconductor structure is reduced.

In an embodiment, the nanoplatelet structure may be formed of a first semiconductor material (e.g., silicon (Si), silicon carbide (SiC), etc.) or a second semiconductor material (e.g., silicon germanium (SiGe), etc.). The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. The first semiconductor material or the second semiconductor material may also be a material having a high etching selectivity to each other with a material forming the first gate structure.

Illustratively, when the semiconductor material of the nanoplatelet structure that is contiguous with the substrate is silicon germanium, the first gate structure is of polysilicon, and there is a high etch selectivity between silicon germanium and polysilicon.

Fig. 31 to 34 are schematic views illustrating a further process for fabricating a semiconductor structure according to an embodiment of the present application. Wherein (a) in fig. 31 to (34) are sectional views of the semiconductor structure along a sectional direction (i.e., A-A 'direction) of the gate structure, and (B) in fig. 31 to (34) are sectional views of the semiconductor structure along a sectional direction (i.e., B-B' direction) of the source/drain structure; fig. 31 (C) to 34 (C) are sectional views of the semiconductor structure along the sectional direction (i.e., C-C' direction) of the nano-sheet structure.

In one example, yet another fabrication process of semiconductor structure 10 may include the steps of:

The first step: patterning and etching to form nanoplatelet structures 47 on silicon substrate 21 by standard steps of a semiconductor fabrication process; depositing polysilicon on the gate region of the semiconductor structure 10 as a first dummy gate structure 24; depositing oxide materials in the source-drain region to form a first shallow trench isolation layer; the first shallow trench isolation layer is etched to form a second shallow trench isolation layer (i.e., shallow trench isolation structure 26). The upper surface of the shallow trench isolation structure 26 is lower in height than the first portion of the nano-sheet structure 47 (the first active structure 131 in fig. 23 is subsequently formed), resulting in the structure shown in fig. 31.

And a second step of: in the gate region in the structure shown in fig. 31, the formation of the first spacer 27 of the first transistor 11 is completed by standard steps of the semiconductor manufacturing process; in the source drain region, the first source drain structure 28 and the first interlayer dielectric layer 29 of the first transistor 11 are completed by standard steps of a semiconductor manufacturing process. Subsequently, the first source-drain metal 30 of the first transistor 11 is completed in the source-drain region, and the subsequent interconnection process of the first transistor 11 is completed over the source-drain region and the gate region, forming the first metal interconnection layer 31. The first metal interconnection layer 31 communicates with the first source drain metal 30, resulting in the structure shown in fig. 32.

And a third step of: depositing an insulating oxide over the structure shown in fig. 32, forming a first insulating layer 32; over the first insulating layer 32, a carrier 33 is bonded to the first transistor 11. And then rewound, wafer thinning is performed to remove the substrate 21, thereby exposing the end of the second portion of the nanoplatelet structure 47, resulting in the structure shown in fig. 33.

Fourth step: the nanoplatelet structures 47 are etched using a selective etching process to at least etch away a predetermined height to obtain the structure shown in fig. 34.

Here, the nano-sheet structure 47 and the first gate structure 24 have a high etching selectivity with each other so that the first dummy gate structure 24 is not etched. So that the gate region forms a first recess 34 in the A-A' direction. The groove depth of the first groove 34 is equal to the preset height.

Fifth step: polysilicon is deposited using an isotropic deposition process to obtain the structure shown in fig. 29.

It will be appreciated that the subsequent steps are the same as those corresponding to fig. 29 to 30 until the structure shown in fig. 23 is obtained. For brevity of the description, the description is not repeated here.

So far, when the active structure is a nano-sheet structure, the first material layer 25 is not required to be formed, the first transistor and the second transistor can be prepared and finished, the preparation steps are effectively reduced, and the preparation complexity is reduced.

In one or more embodiments for fabricating semiconductor structures, not only can the process flow of stacking transistors be greatly simplified, but also the consistency of the active structures and the gate structures of the upper and lower transistors can be compromised. In particular, the grid electrode structure and the active structure of the upper and lower layers of transistors are self-aligned and stacked, so that the problems of complex process, difficult alignment and the like in the existing mainstream technical scheme of stacked transistors are solved, and the promotion of the industrialization of transistor stacking technology is realized. On the other hand, by the self-aligned back-to-back active structure and grid structure, the upper transistor and the lower transistor can have independent signal and power supply network and are connected through local interconnection, and under the condition of not changing the design of the extremely miniature 4T track unit, the metal wiring resource is greatly released.

Finally, the scheme of realizing the upper and lower transistors through the rewinding is compatible with the existing mainstream device architecture, and the front and back stacking comprising a planar transistor, a FinFET, GAA Nanosheet and even a vertical transistor (VTFET) can be realized without special process development aiming at a specific device architecture, so that the flexibility is high, and the extensibility is high from the iteration point of a semiconductor processing node. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicability and wide expansion prospect.

An embodiment of the present application provides a semiconductor device including: such as the semiconductor structures of the above embodiments. The specific limitation of the semiconductor structure may be referred to the semiconductor structures shown in fig. 2 and fig. 22 to 24, and will not be described herein.

An embodiment of the present application provides an electronic device, including: the circuit board and the semiconductor device of the above embodiment are provided on the circuit board. The semiconductor device comprises the semiconductor structure. The specific limitation of the semiconductor structure may be referred to the semiconductor structures shown in fig. 2 and fig. 22 to 24, and will not be described herein.

In the description of the present application, a description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily for the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples described in the present application and the features of the various embodiments or examples may be combined by those skilled in the art without contradiction.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor structure, comprising:

Providing a substrate, and etching the substrate to form an active structure; wherein the active structure includes a first end and a second end, the first end of the active structure being remote from the substrate compared to the second end of the active structure;

Forming a first material layer on a first region of the substrate, wherein the first region is positioned in grid regions at two sides of the active structure;

forming a first dummy gate structure on the first material layer across the active structure;

rewinding the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer;

etching the semiconductor structure by using the first material layer as an etching mask until reaching a preset height;

Depositing a semiconductor material on the semiconductor structure to form a second pseudo gate structure; the height of the second dummy gate structure in the gate region is higher than the height of the second dummy gate structure in the source drain region;

etching the second pseudo gate structure until the active structure of the source drain region is exposed, so as to form a third pseudo gate structure;

And removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure respectively.

2. The method of claim 1, wherein said etching the semiconductor structure using the first material layer as an etching mask until a predetermined height is reached, comprises:

And selectively etching the second end of the active structure in the gate region, the second end of the active structure in the source-drain region and a shallow trench structure surrounding the active structure by using the first material layer as an etching mask until the height difference between the active structure and the first dummy gate structure reaches a preset height, and forming a first groove in the gate region.

3. The method of manufacturing of claim 2, wherein depositing semiconductor material on the semiconductor structure forms a second dummy gate structure, comprising:

depositing a semiconductor material on the source-drain region and the gate region with the first groove in an isotropic deposition mode until the first groove is filled;

The etching the second dummy gate structure until the active structure of the source drain region is exposed to form a third dummy gate structure, comprising:

And etching the second dummy gate structure by adopting an anisotropic etching mode until the active structure of the source-drain region is exposed, and forming the third dummy gate structure in the gate region.

4. The method of manufacturing of claim 1, wherein the removing the first dummy gate structure and the third dummy gate structure to form a first gate structure and a second gate structure, respectively, comprises:

Removing the first dummy gate structure and the third dummy gate structure;

Depositing a first metal material at the removed first dummy gate structure to form the first gate structure; the first gate structure wraps around a first portion of the active structure; the first end is located at the first portion;

a second metal material is deposited over the first gate structure until covering the removed third dummy gate structure to form the second gate structure.

5. The method of manufacturing of claim 1, wherein forming a first material layer on the first region of the substrate comprises:

Depositing a hard mask material on the etched substrate until a second groove formed by the active structure is filled up, and removing the hard mask material on the active structure by adopting a back etching process to form a second material layer; the active structure protrudes from the second material layer;

And removing the second material layer on the source-drain region to form the first material layer on the first region of the substrate.

6. The method of manufacturing of claim 5, wherein the depositing a hard mask material on the etched substrate until the second recess formed by the active structure is filled, the method further comprising:

Depositing a first oxidation material on the etched substrate to form an oxidation layer;

The rewinding the semiconductor structure and removing the substrate to expose the second end of the active structure and the first material layer in the gate region, comprising:

Removing the substrate by adopting a planarization process until the second part of the active structure and the oxide layer are exposed;

the oxide layer of the gate region is removed to expose the first material layer of the gate region.

7. The method of manufacturing of claim 5, wherein after forming a first dummy gate structure across the active structure on the first material layer, the method further comprises:

depositing a second oxide material in the source-drain region to form a shallow trench isolation structure, wherein the shallow trench isolation structure covers a second part of the active structure and exposes a first part of the active structure;

Forming a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer in the source-drain region based on the first part;

The second dummy gate structure is etched until the active structure of the source drain region is exposed, so that a third dummy gate structure is formed, and the method further comprises:

thinning the shallow trench isolation structure in the source-drain region to expose a second portion of the active structure;

and forming a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer in the source-drain region based on the second part of the active structure.

8. The method of manufacturing according to claim 1, wherein the substrate comprises: the semiconductor device comprises a first substrate layer, a second substrate layer and a buried oxide layer which are stacked, wherein the buried oxide layer is positioned between the first substrate layer and the second substrate layer;

The etching the substrate to form an active structure comprises the following steps:

etching a first part of the first substrate layer, the buried oxide layer and the second substrate layer, and reserving a second part of the second substrate layer to form the active structure;

Wherein the first substrate layer forms a first portion of the active structure and the first portion of the second substrate layer forms a second portion of the active structure.

9. A semiconductor structure prepared using the preparation method according to any one of claims 1 to 8, comprising:

A first transistor;

A second transistor, the first transistor and the second transistor being disposed opposite to each other;

The first active structure of the first transistor and the second active structure of the second transistor form the active structure, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

10. The semiconductor structure of claim 9, wherein an isolation layer is formed between the first active structure and the second active structure, the isolation layer for electrically isolating the first active structure and the second active structure;

The isolation layer is created by a buried oxide layer in the substrate.

11. A semiconductor device, comprising: the semiconductor structure of any one of claims 9 to 10.