CN118035158A

CN118035158A - Use method of storage device and storage device

Info

Publication number: CN118035158A
Application number: CN202410199644.1A
Authority: CN
Inventors: 贾秋伶
Original assignee: Lenovo Kaitian Technology Co Ltd
Current assignee: Lenovo Kaitian Technology Co Ltd
Priority date: 2024-02-22
Filing date: 2024-02-22
Publication date: 2024-05-14

Abstract

The invention provides a use method of a storage device and the storage device, wherein the use method comprises the steps of selecting part of pins in general input/output pins in the storage device as target pins of a target data line; initializing a target pin; defining time sequence parameters and data sampling points according to SPI protocol used by the storage device so as to maintain the relative position between a data signal on a target data line and a reference clock signal thereof; setting a transmission function to transmit data to be transmitted in the storage device bit by bit; the receiving function is set to read, store and manage data from the partial data line of the target data line so that the target pin of the storage device is used as an SPI bus to enable the storage device to support an SPI protocol. Because SPI does not need the response mechanism to confirm whether to receive the data, so can carry on the data transmission before the initialization of the apparatus is finished, solve the problem that the storage device can't carry on the data transmission in the initialization stage of the apparatus based on SATA or NVMe agreement in the prior art.

Description

Use method of storage device and storage device

Technical Field

The present invention relates to the field of storage devices, and in particular, to a method for using a storage device and a storage device.

Background

The storage device generally uses high-speed interfaces such as SATA (SERIAL ADVANCED Technology Attachment: serial hard disk) or NVMe (Nonvolatile memory express: nonvolatile flash memory) to perform data transmission, for example, the storage device is an SSD (solid state disk), and when in use, the solid state disk can transmit data, but because SATA or NVMe protocols all need a response mechanism, the SATA or NVMe protocols need to be initialized and then the data transmission can be performed, and in the initialization stage of the device, the SSD based on the existing SATA or NVMe protocols cannot realize data transmission.

Disclosure of Invention

An embodiment of the invention aims to provide a use method of a storage device and the storage device, which are used for solving the problem that the storage device cannot perform data transmission in an equipment initialization stage based on SATA or NVMe protocols in the prior art.

The embodiment of the invention adopts the following technical scheme: a method of using a storage device, comprising:

selecting part of pins in the general input/output pins in the storage device as target pins of the target data line;

initializing a target pin;

defining time sequence parameters and data sampling points according to SPI protocol used by the storage device so as to maintain the relative position between a data signal on a target data line and a reference clock signal thereof;

Setting a transmission function to transmit data to be transmitted in the storage device bit by bit;

The receiving function is set to read, store and manage data from a portion of the target data line on a portion of the data line such that the target pin of the memory device acts as an SPI bus.

In some embodiments, the selecting a portion of the pins of the universal input output pins of the memory device as target pins of the target data line includes:

Six independent pins among the general input output pins in the memory device are selected as target pins of a master input and slave output data line, a master output and slave input data line, a serial clock line, a slave device select line, a write protection line, and a communication hold line.

In some embodiments, the initializing the target pin includes:

Configuring a target pin as an output mode;

setting an initial state of a target pin, wherein the initial state of the target pin corresponding to the serial clock line is set to be a low level; the initial state of the target pin corresponding to the slave select line is set to a high level.

In some embodiments, defining timing parameters and data sampling points according to the SPI protocol used by the memory device includes:

the high and low levels of the serial clock line, as well as the data sampling points, are defined according to the SPI protocol used by the memory device, wherein,

When the clock polarity is 0 and the clock phase is 0, the data is sampled at the first edge of the serial clock line and changed at the next edge;

when the clock polarity is 0 and the clock phase is 1, the data is sampled at the second edge of the serial clock line and changed at the next edge;

When the clock polarity is 1 and the clock phase is 0, the clock is in a high level in an idle state of the serial clock line, the data is sampled at the first falling edge of the serial clock line, and the data is changed at the next rising edge;

When the clock polarity is 1 and the clock phase is 1, the clock is at a high level in the idle state of the serial clock line, the data is sampled at the second rising edge of the SCK, and the data is changed at the next falling edge.

In some embodiments, the setting a transmission function to transmit data to be transmitted in the storage device bit by bit includes:

shifting data to be transmitted in the storage device into a register;

The level of the clock signal is changed bit by bit, and data on the master input and slave output data lines and the master output and slave input data lines are read or written by the master of the memory device during the pulse period of each clock signal.

In some embodiments, the setting a receive function to read, store, and manage data on a portion of the data lines from the target data line includes:

When the master device initiates a data exchange request to the slave device through a clock signal, the slave device outputs data to the master input and slave output data lines at each clock edge;

the master device synchronously shifts the data read in from the output data line to a register according to the clock edge specified by the SPI protocol;

After all the data bits are shifted into the register, the data bits are reassembled into complete bytes according to the order in which the SPI protocol is transmitted.

In some embodiments, the method further comprises:

When the slave devices comprise at least two slave devices, the master device requests to communicate with one target slave device, and the signal corresponding to the target slave device is pulled down to a low level;

the target slave device receives signals on the master input and slave output data line, the master output and slave input data line and the serial clock line and executes corresponding read-write operation;

The master device transmits data to the target slave device through the master output and slave input data line, and receives data from the target slave device on the master input and slave output data line through the serial clock line so as to exchange data between the master device and the target slave device.

In some embodiments, the method further comprises:

After the data exchange between the master device and the target slave device is completed, the master device pulls up the level of the target pin corresponding to the slave device selection line to a high level so as to enable all the slave devices to be in a non-selected state.

In some embodiments, a reserved space of flash particles in the storage device reserves a space of a set capacity for the SPI bus.

The embodiment of the invention also discloses a storage device, which comprises:

a main control part and a storage part;

An interface section configured to implement an SPI protocol;

wherein:

The main control part of the storage device is embedded with an SPI controller, wherein the SPI controller is configured to be connected with the storage part of the storage device and the interface part of the storage device respectively.

The embodiment of the invention has the beneficial effects that:

The method comprises the steps of initializing part of pins of the storage device, carrying out definition setting of time sequence parameters, namely data sampling points, according to an SPI protocol used by the storage device, enabling the storage device to support the SPI protocol, and carrying out bit-by-bit transmission and reception of data based on the SPI protocol through a transmission function and a reception function. Because SPI does not need the response mechanism to confirm whether to receive the data, so can carry on the data transmission before the initialization of the apparatus is finished, solve the problem that the storage device can't carry on the data transmission in the initialization stage of the apparatus based on SATA or NVMe agreement in the prior art.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow chart of a method of using a memory device according to an embodiment of the present invention;

FIG. 2 is a flowchart illustrating an embodiment of step S200 in FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating an embodiment of step S400 in FIG. 1 according to an embodiment of the present invention;

FIG. 4 is a flow chart of one embodiment of step 5200 of FIG. 1 in accordance with an embodiment of the present invention;

FIG. 5 is a block diagram illustrating a storage device and a host according to an embodiment of the present invention.

Reference numerals: 1. a storage device; 101. a main control part; 102. a storage unit; 103. an interface part; 104. an SPI controller; 105. an OP portion; 2. and a host.

Detailed Description

Various aspects and features of the present invention are described herein with reference to the accompanying drawings.

It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of the invention will occur to persons of ordinary skill in the art.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description of the embodiments given below, serve to explain the principles of the invention.

These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.

It is also to be understood that, although the invention has been described with reference to some specific examples, a person skilled in the art will certainly be able to achieve many other equivalent forms of the invention, having the characteristics as set forth in the foregoing summary of the invention and hence all coming within the field of protection defined thereby.

The above and other aspects, features and advantages of the present invention will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.

Specific embodiments of the present invention will be described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the invention in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely as a basis for the "summary of the invention" and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed structure.

The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the invention.

To solve the problems in the background art, an embodiment of the present invention provides a method for using a storage device, and in combination with fig. 1, the method includes the following steps:

S100, selecting part of pins in the general input/output pins in the storage device as target pins of the target data line.

For example, according to the SPI protocol used by the memory device, the number of target data lines may be plural, and the target pins are GPIO pins corresponding to the number and functional implementation of the target data lines in the general purpose input/output pins (GPIO pins) of the memory device.

S200, initializing a target pin.

Illustratively, these target pins are set to output mode and their initial state is set. Typically, SCK is typically initialized low and CS is pulled high to indicate that no slave device is selected, where a slave device is the device selected by the master device for communication.

S300, defining time sequence parameters and data sampling points according to SPI (SERIAL PERIPHERAL INTERFACE ) protocol used by the storage device so as to maintain the relative position between the data signal on the target data line and the reference clock signal thereof.

Illustratively, the SCK is defined as high and low levels and data sampling points according to the SPI protocol used by the memory device. In SPI communication, timing parameters are critical to ensure proper data transmission. The SPI has four operation modes, which are determined by two parameters, i.e., CPOL (Clock Polarity) and CPHA (Clock Phase), respectively. Specifically, CPOL (clock polarity):

cpol=0: when the SPI is in the idle state, the level of the SCK line is low.

Cpol=1: when the SPI is in the idle state, the level of the SCK line is high.

CPHA (clock phase):

Cpha=0: the data is sampled on a first clock edge (rising or falling, depending on the CPOL) and changed on a second clock edge.

Cpha=1: the data is sampled at the second clock edge and changed at the first clock edge.

S400, setting a transmission function to transmit data to be transmitted in the storage device bit by bit.

Illustratively, in the transmit function, the data to be transmitted is shifted into one register. In the transmission function of SPI communication, the purpose of shifting data to be transmitted into one register is to perform bit-by-bit transmission as prescribed by the SPI protocol. The SPI communication adopts a serial data transmission mode, that is, only one bit of data is transmitted at a time, and the rhythm of data transmission is controlled by a clock signal SCK. The design aims to realize efficient serial data transmission by using hardware, ensure the sequence and accuracy of data transmission and meet the requirements of SPI communication standards. The level of the SCK signal can then be changed bit by bit and the data on MISO and MOSI read or written during each SCK pulse.

S500, setting a receiving function to read, store and manage data on a part of the data lines from the target data lines, so that the target pins of the storage device serve as SPI buses.

Illustratively, the receive function is similar to the transmit function, but focuses on reading data on the MISO and shifting it into one register, and in SPI communication, the receive function, although similar in principle to the transmit function, is primarily concerned with reading data from the MISO and shifting it into one register. The register here is typically a hardware unit that is independent of the shift register used when transmitting the data.

The execution reading or writing of the transmission function and the reception function may be realized by the same piece of code, and both are executed by a main Control Portion (CPU) of the storage device.

According to the embodiment of the invention, the partial pins of the storage device are initialized, the definition setting of time sequence parameters, namely data sampling points, is carried out according to the SPI protocol used by the storage device, so that the storage device supports the SPI protocol, and then the data is transmitted and received bit by bit based on the SPI protocol through the transmitting function and the receiving function. Because SPI does not need the response mechanism to confirm whether to receive the data, so can carry on the data transmission before the initialization of the apparatus is finished, solve the problem that the storage device can't carry on the data transmission in the initialization stage of the apparatus based on SATA or NVMe agreement in the prior art.

In the use method disclosed by the embodiment of the invention, the GPIO pin is reprogrammed to simulate the SPI bus, but not the original function of the GPIO pin. The software on the controller is then modified to implement the operation of the SPI protocol. Namely, an SPI function is added on the storage device, and a corresponding SPI signal is added on an interface of the SSD by utilizing unused pins and used for supporting the SPI function. A main Control Part (CPU) of the storage device controls the GPIO pin through software to realize SPI protocol. The method has the advantages that the hardware of the storage equipment is not required to be changed, only the software level is required to be modified, and the design cost and the production cost for redesigning the hardware of the storage equipment are reduced.

In one embodiment of the present invention, the selecting a portion of the pins of the common input/output pins of the memory device as the target pins of the target data line includes:

Namely, the target data lines are MISO (master input slave output data line), MOSI (master output slave input data line), SCK (clock control line), CS (slave select line), WP (write protect line) and hold (communication hold line), and six independent pins out of the GPIO pins are used as the target pins of the six target data lines. If there are multiple slaves, the target device needs to be selected according to the different states of the CS signal. In SPI communications, if multiple slaves are connected to the same master, a slave select line (also called a chip select line, CS/SS: CHIP SELECT/SLAVE SELECT) is used to distinguish and select the particular slave with which to communicate. The target pin corresponding to WP is a write protection pin outside the SPI flash (serial flash), which does not directly protect the data content on the SPI flash, but protects the status register from being abnormally rewritten. Content write protection on SPI flash is achieved through different combinations of status registers BPxbit. For relatively bad use situations (unstable power supply, etc.) in the environment, the content on the SPI flash needs to be protected, and the whole design thinking is that the BPx bit combination of the status register is used for realizing the local or whole write protection of the data content on the SPI flash, and the level state of the external WP pin is combined with the SRP (Secure Remote Password ) bit of the status register to realize the protection of the status register so as to indirectly protect the protected data content on the SPI flash. The communication maintaining line can maintain the correspondence when the storage device performs data transmission so as to ensure the normal transmission of the data. It will of course be appreciated that other data lines or control lines may be selected as the target data line according to the SPI protocol used by the memory device, and this is merely an example and does not limit the scope of the claims.

In one embodiment of the present invention, in conjunction with fig. 2, the initializing the target pin includes:

s201, the target pin is configured to be in an output mode, so that the storage device can output (issue) the content to be transmitted through the target pin.

S202, setting an initial state of a target pin, wherein the initial state of the target pin corresponding to a serial clock line is set to be a low level; the initial state of the target pin corresponding to the slave select line is set to a high level.

Specifically, an initial state of the target pin is set, wherein the initial state of the target pin corresponding to the serial clock line (SCK) is set to a low level, so that the target pin corresponding to the SCK can be pulled to a high level when data is transmitted, and the SCK is enabled to maintain a working state. Setting an initial state of a target pin of a corresponding slave select line to a high level to indicate that any slave is not selected; when the master device wants to communicate with one of the slave devices, the master device pulls down the CS signal corresponding to the slave device to a low level, and after the selected slave device recognizes that the CS signal of the master device is changed to the low level, the master device determines the current communication time of the master device and starts to monitor signals on MOSI, SCK and MISO lines to execute corresponding read-write operation. The master device sends data to the slave device through the MOSI while also receiving data on the MISO from the slave device through the SCK clock. While the CS signals of other non-selected slaves remain high, these non-selected slaves ignore the data transmission on the SPI bus at this time.

Once the data exchange is complete, the master releases the CS signal pulling it high back to high. All slave devices are again in the unselected state, waiting for the next communication request. In this way, one SPI master device can control a plurality of slave devices and perform independent serial communication with the plurality of slave devices, respectively, thereby realizing the function of multipoint communication. Errors that may occur, such as time-out or parity errors, are checked during transmission. It is also contemplated that the code may be optimized using assembly language or preprocessor instructions to increase the data transfer rate.

In one embodiment of the present invention, defining timing parameters and data sampling points according to an SPI protocol used by a memory device includes:

When the clock polarity is 0 and the clock phase is 0, the data is sampled at the first edge of the serial clock line and changed at the next edge. The first operating Mode of SPI is SPI Mode 0 (cpol=0, cpha=0): the data is sampled at the first edge (rising edge) of the SCK and then changed at the next edge (falling edge).

When the clock polarity is 0 and the clock phase is 1, the data is sampled at the second edge of the serial clock line and changed at the next edge. The second Mode of operation of SPI is SPI Mode 1 (cpol=0, cpha=1) where data is sampled on the second edge (falling edge) of SCK and then changed on the next edge (rising edge).

When the clock polarity is 1 and the clock phase is 0, the clock is at a high level in the idle state of the serial clock line, the data is sampled at the first falling edge of the serial clock line, and the data is changed at the next rising edge. The third operating Mode of SPI is SPI Mode 2 (cpol=1, cpha=0): in the idle state of the SCK, high, the data is sampled on the first falling edge of the SCK and changed on the next rising edge.

When the clock polarity is 1 and the clock phase is 1, the clock is at a high level in the idle state of the serial clock line, the data is sampled at the second rising edge of the SCK, and the data is changed at the next falling edge. The fourth operating Mode of SPI is SPI Mode 3 (cpol=1, cpha=1): in the idle state of the SCK, high, the data is sampled on the second rising edge of the SCK and changed on the next falling edge.

In some embodiments, in conjunction with fig. 3, the setting a transmission function to transmit data to be transmitted in the storage device bit by bit includes:

S401, shifting data to be transmitted in the storage device into a register.

In the transmission function of SPI communication, the purpose of shifting the data to be transmitted into a register, which can be denoted as the first register, is to be transmitted bit by bit as specified by the SPI protocol. The SPI communication adopts a serial data transmission mode, that is, only one bit of data is transmitted at a time, and the rhythm of data transmission is controlled by a clock signal SCK. The design aims to realize efficient serial data transmission by using hardware, ensure the sequence and accuracy of data transmission and meet the requirements of SPI communication standards.

S402, changing the level of the clock signal bit by bit, and reading or writing data on the master input/slave output data line and the master output/slave input data line by the master of the memory device during the pulse period of each clock signal.

That is, after S401 is completed, the level of the SCK signal is changed bit by bit, and data on MISO and MOSI is read or written during each SCK pulse, so that data on MISO and MOSI is accurately read or written in cooperation with a clock signal.

In some embodiments, in conjunction with FIG. 4, the setting of the receive function to read, store and manage data from a portion of the target data line on the data line includes:

S501, when the master device initiates a data exchange request to the slave device through a clock signal, the slave device outputs data onto the master input/slave output data line at each clock edge.

Specifically, this step may store the received data: when a master initiates a data exchange request to a slave via an SCK signal, the slave will output data onto the MISO line at each SCK clock edge. The host device needs to read this data in real time and store it for later processing or use.

S502, the master device synchronously shifts the data read in from the output data line by the master input to a register according to the clock edge specified by the SPI protocol.

Specifically, this step may perform a synchronous shift operation: as well as shifting out data bit by bit as it is being sent, the master device also needs to synchronize shift operations on the data read in from the MISO line according to the clock edges specified by the SPI protocol. I.e. the data read in from the MISO line, is put one bit into one register, which here may be denoted as second register, in order to distinguish it from the register of the transmit function. This step can ensure that each data bit is captured correctly to ensure accuracy of the data transmission.

S503, after all data bits are shifted to the register, the data bits are recombined into complete bytes according to the SPI protocol transmission sequence.

Specifically, this step may enable reconstruction of complete bytes: after all data bits are shifted to the second register, they can be recombined into a complete byte according to the order of SPI transmission (e.g., MSB priority or LSB priority).

Therefore, this second register for receiving data is an important component for storing and managing information received from the SPI slave device, and is different from the first register used when transmitting data, but operates in a similar manner, and is based on a serial shift register mechanism to achieve data transmission and reception.

In some embodiments, the method further comprises:

When the slave device includes at least two slave devices, the master device requests communication with one of the target slave devices, the signal corresponding to the target slave device is pulled low. The CS signals of other non-selected slave devices remain high and they ignore the data transfer on the SPI bus at this time.

The target slave device receives signals on the master input and slave output data lines, the master output and slave input data lines and the serial clock line and performs corresponding read-write operations. Namely, after the selected slave device recognizes that the CS signal of the slave device is changed into low level, the slave device knows the current communication time of the slave device and the master device, starts to monitor signals on MOSI, SCK and MISO lines, and executes corresponding read-write operation.

The master device transmits data to the target slave device through the master output and slave input data line, and receives data from the target slave device on the master input and slave output data line through the serial clock line so as to exchange data between the master device and the target slave device. I.e. the master device may send data to the slave device via the MOSI while also receiving data on the MISO from the slave device via the SCK clock.

In some embodiments, the method further comprises:

after the data exchange between the master device and the target slave device is completed, the master device pulls up the level of the target pin corresponding to the slave device selection line to a high level so as to enable all the slave devices to be in a non-selected state. To wait for the next data to be ready for the next data transmission.

When the storage device is an SSD, some flash memory particles in the SSD are OP (reserved space) parts, the capacity of the flash memory particles is generally 7% of that of a solid state disk, the capacity of the SPI device is generally 8M/16M/32M, the capacity reserved for 32M from the OP space is used as an SPI bus, and the service life and the performance of the SSD are not affected.

With reference to fig. 5, an embodiment of the present invention further discloses a storage device 1, including:

a main control unit 101 and a storage unit 102;

an interface section 103 configured to implement the SPI protocol;

wherein:

the main control portion 101 of the memory device 1 is embedded with an SPI controller 104, wherein the SPI controller 104 is configured to be connected to the memory portion 102 of the memory device 1 and the interface portion 103 of the memory device 1, respectively.

For example, in the initial stage of the design of the main control part 101 of the storage device 1, the SPI controller 104 may be added, a space with 32M capacity is reserved in the OP part 105 of the flash memory granule (NAND granule), the capacity of 32M has no influence on the life and performance of the storage device 1, the SPI controller 104 is connected to the NAND granule, and meanwhile, the SPI controller 104 is connected to the interface part 103 of the storage device 1 to realize interaction with the host 2 of the electronic device. The storage device 1 has SPI function, and can realize data transmission through SPI protocol, so that the problem that the storage device cannot perform data transmission in the device initialization stage based on SATA or NVMe protocol in the prior art is solved.

The storage device 1 employing the SPI protocol can realize some advanced functions such as security encryption or fault diagnosis through the SPI; the security module connected through the SPI interface may perform encryption operations on the drive to protect stored data from unauthorized access, etc. Likewise, SPI can also be used to monitor and report the status of the hard disk to take timely action in the event of a failure. SPI can also be used for secure boot of BIOS (basic input output System).

While various embodiments of the present invention have been described in detail, the present invention is not limited to these specific embodiments, and various modifications and embodiments can be made by those skilled in the art on the basis of the inventive concept, and these modifications and modifications should be included in the scope of the claimed invention.

Claims

1. A method of using a memory device, comprising:

initializing a target pin;

2. The method of claim 1, wherein selecting a portion of the common input output pins in the memory device as target pins of the target data line comprises:

3. The method of claim 2, wherein initializing the target pin comprises:

Configuring a target pin as an output mode;

4. The method of claim 2, wherein defining timing parameters and data sampling points according to an SPI protocol used by the memory device comprises:

5. The method of claim 2, wherein the setting a transmit function to transfer data to be transmitted in the storage device bit by bit comprises:

shifting data to be transmitted in the storage device into a register;

6. The method of claim 2, wherein the setting a receive function to read, store, and manage data from a portion of the data lines on the target data line comprises:

7. The method according to claim 2, wherein the method further comprises:

8. The method of claim 7, wherein the method further comprises:

9. The method of claim 1, wherein a reserved space of flash memory particles in the memory device reserves a space of a set capacity for the SPI bus.

10. A memory device, comprising:

a main control part and a storage part;

An interface section configured to implement an SPI protocol;

wherein: