CN118012804A

CN118012804A - Control circuit and slave device

Info

Publication number: CN118012804A
Application number: CN202410411363.8A
Authority: CN
Inventors: 谢尚记; 张枫轩; 何振; 刘奇
Original assignee: Zhejiang Huashi Zhijian Technology Co ltd
Current assignee: Zhejiang Huashi Zhijian Technology Co ltd
Priority date: 2024-04-07
Filing date: 2024-04-07
Publication date: 2024-05-10
Anticipated expiration: 2044-04-07
Also published as: CN118012804B

Abstract

The invention discloses a control circuit and slave equipment, wherein the control circuit comprises a power-on circuit and a power-off circuit, the power-on circuit outputs effective enabling signals to a power module when an SPI_CS signal is high level, an SPI_MOSI signal is low level and an SPI_CLK signal is low level based on input voltage, so that the power module provides power supply voltage for the slave equipment, and the slave equipment is started; and in the normal working process of the slave device, when the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal are all low, the power-down circuit outputs an effective power-off signal, and after receiving the effective power-off signal, the power-up circuit outputs an invalid enabling signal to the power module so as to enable the power module to stop providing power supply voltage for the slave device, and the slave device is powered off. Because the control circuit controls the on/off of the slave device through the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal in SPI communication, the pins of the controller are not required to be used when the slave device is on/off, so that the pins of the controller can be reduced, the operation pressure of the controller is reduced, and the performance of the slave device is improved.

Description

Control circuit and slave device

Technical Field

The invention relates to the technical field of power supply control, in particular to a control circuit and slave equipment.

Background

For the on-off of the slave device in the SPI communication, the on-off of the slave device is controlled by a controller in the slave device, and an additional controller pin is needed by the controller to control the on-off of the slave device, so that the problem of resource shortage of the controller pin is caused.

Disclosure of Invention

The invention provides a control circuit and slave equipment, which are used for solving the problem of shortage of pin resources of a controller in the slave equipment in the prior art.

In a first aspect, the present application provides a control circuit for use with a slave device in an SPI communications device, comprising:

The power-on circuit is used for outputting a valid enabling signal to the power module when the SPI_CS signal is in a high level, the SPI_MOSI signal is in a low level and the SPI_CLK signal is in a low level based on the input voltage, and outputting an invalid enabling signal to the power module after receiving a valid shutdown signal sent by the power-off circuit, wherein the power module provides a power supply voltage for the slave device when receiving the valid enabling signal so as to start the slave device, and the power module stops providing the power supply voltage for the slave device when receiving the invalid enabling signal so as to shut down the slave device;

And the power-down circuit is used for sending the effective shutdown signal to the power-up circuit based on the power supply voltage when the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal are all in a low level in the normal working process of the slave equipment.

In one possible implementation, the power-on circuit includes a power-on unit and a signal latch unit;

The startup unit is used for conducting a path between the input voltage and the enabling signal under the control of the SPI_CS signal of a high level so as to output the effective enabling signal;

the signal latch unit is used for controlling the starting-up unit to keep conducting a channel between the input voltage and the enabling signal when the shutdown signal is invalid, and controlling the starting-up unit to disconnect the channel between the input voltage and the enabling signal when the shutdown signal is valid, so that the starting-up unit outputs the invalid enabling signal.

In one possible implementation manner, the power-on unit includes a first diode, a first resistor, a second resistor, a first switching tube and a second switching tube;

The anode of the first diode inputs the SPI_CS signal, and the cathode of the first diode is electrically connected with the control end of the first switch tube and the first end of the first resistor;

the second end of the first resistor and the second end of the first switch tube are grounded;

the first end of the first switch tube is electrically connected with the first end of the second resistor, the control end of the second switch tube and the signal latch unit;

the second end of the second resistor is electrically connected with the first end of the second switching tube, and the input voltage is input;

and the second end of the second switching tube is electrically connected with the signal latching unit and outputs the enabling signal.

In one possible implementation manner, the signal latching unit includes a third resistor, a fourth resistor, a fifth resistor and a third switching tube;

The first end of the third resistor is electrically connected with the control end of the second switching tube, and the second end of the third resistor is electrically connected with the first end of the third switching tube;

the second end of the third switching tube is electrically connected with the first end of the fifth resistor and grounded, and the control end of the third switching tube is electrically connected with the second end of the fifth resistor and the first end of the fourth resistor and inputs the shutdown signal;

and the second end of the fourth resistor is electrically connected with the second end of the second switching tube.

In one possible implementation manner, the lower circuit comprises a first isolation unit, a charge-discharge unit and a first on-off unit;

the first isolation unit is used for isolating and transmitting the SPI_CLK signal and the SPI_MOSI signal;

The charging and discharging unit is used for charging based on the SPI_CLK signal and the SPI_MOSI signal in the normal working process of the slave device, and discharging when the SPI_MOSI signal and the SPI_CLK signal are both at low level;

The first on-off unit is used for outputting the invalid shutdown signal based on the power supply voltage after the charging process and the charging of the charging and discharging unit are completed, and outputting the valid shutdown signal based on the power supply voltage after the discharging of the charging and discharging unit is completed.

In one possible implementation, the first isolation unit includes a second diode and a third diode;

the anode of the second diode inputs the SPI_MOSI signal, and the cathode of the second diode is electrically connected with the cathode of the third diode and the charging and discharging unit;

An anode of the third diode inputs the SPI_CLK signal.

In one possible implementation, the charge-discharge unit includes a capacitor and a sixth resistor;

The first end of the capacitor is electrically connected with the first end of the sixth resistor, the cathode of the second diode and the first on-off unit;

the second end of the capacitor and the second end of the sixth resistor are grounded.

In one possible implementation manner, the first switching unit includes a seventh resistor, a fourth switching tube and a fifth switching tube;

The control end of the fourth switching tube is electrically connected with the first end of the capacitor, the first end of the fourth switching tube is electrically connected with the first end of the seventh resistor and the control end of the fifth switching tube, and the second end of the fourth switching tube is grounded;

The first end of the fifth switching tube is used for outputting the shutdown signal, and the second end of the fifth switching tube is grounded;

the second terminal of the seventh resistor receives the supply voltage.

In one possible implementation, the circuit further comprises a reset circuit;

And the reset circuit is used for sending a reset signal to the slave device when the SPI_CS signal and the SPI_CLK signal are both in a high level in the normal working process of the slave device so as to reset the slave device.

In one possible implementation manner, the reset circuit includes a second isolation unit, an on-off control unit and a second on-off unit;

the second isolation unit is used for isolating and transmitting the SPI_CLK signal and the SPI_CS signal;

The on-off control unit is used for conducting a passage between a power supply voltage end and a grounding end when the received SPI_CLK signal and the received SPI_CS signal are at high levels so as to output the reset signal, wherein the power supply voltage end is used for outputting the power supply voltage.

In one possible implementation, the second isolation unit includes a fourth diode and a fifth diode;

The anode of the fourth diode is input with the SPI_CLK signal, and the cathode of the fourth diode is electrically connected with the on-off control unit;

And the anode of the fifth diode is input with the SPI_CS signal, and the cathode of the fifth diode is electrically connected with the on-off control unit.

In one possible implementation manner, the on-off control unit includes an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a sixth diode;

The first end of the eighth resistor is electrically connected with the cathode of the fourth diode and the first end of the ninth resistor, and the second end of the eighth resistor is grounded;

The second end of the ninth resistor is electrically connected with the first end of the tenth resistor, the anode of the sixth diode and the second switching-on and switching-off unit;

The cathode of the sixth diode is electrically connected with the cathode of the fifth diode, the first end of the eleventh resistor and the second end of the tenth resistor;

the second end of the eleventh resistor is grounded.

In one possible implementation, the second switching unit includes a twelfth resistor and a sixth switching tube;

the first end of the twelfth resistor is electrically connected with the power supply voltage end, and the second end of the twelfth resistor is electrically connected with the first end of the sixth switching tube and outputs the reset signal;

the control end of the sixth switching tube is electrically connected with the second end of the ninth resistor, and the second end of the sixth switching tube is grounded.

In a second aspect, the present application provides a slave device, including a power module and the control circuit of any one of the first aspects, wherein the control circuit includes a power-up circuit and a power-down circuit;

the power-on circuit is respectively and electrically connected with the SPI_CS signal end, the input voltage end, the enabling end of the power supply module and the power-off circuit;

The power-down circuit is also electrically connected with the SPI_CLK signal end, the SPI_MOSI signal end and the power supply voltage end;

The power module is configured to output a power supply voltage through the power supply voltage terminal under control of an effective enabling signal output by the power-on circuit, so that the slave device is turned on, and stop outputting the power supply voltage under control of an ineffective enabling signal output by the power-on circuit, so that the slave device is turned off, where the ineffective enabling signal is output by the power-on circuit based on an effective shutdown signal output by the power-off circuit.

The invention has the following beneficial effects:

The embodiment of the application provides a control circuit and slave equipment, wherein the control circuit comprises a power-on circuit and a power-off circuit, wherein the power-on circuit outputs effective enabling signals to a power module when an SPI_CS signal is high level, an SPI_MOSI signal is low level and an SPI_CLK signal is low level based on input voltage, so that the power module provides power supply voltage for the slave equipment, and the slave equipment is started; and in the normal working process of the slave device, when the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal are all low, the power-down circuit outputs an effective power-off signal, and after receiving the effective power-off signal, the power-up circuit outputs an invalid enabling signal to the power module so as to enable the power module to stop providing power supply voltage for the slave device, and the slave device is powered off. Because the control circuit provided by the embodiment of the application controls the on/off of the slave device through the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal in SPI communication, the pins of the controller are not required to be used when the slave device is on/off, so that the pins of the controller can be reduced, the operation pressure of the controller is reduced, and the performance of the slave device is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a control circuit according to an embodiment of the present application;

Fig. 2 is a schematic circuit diagram of a power-on circuit according to an embodiment of the present application;

Fig. 3 is a schematic circuit diagram of a lower circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another control circuit according to an embodiment of the present application;

FIG. 5 is a schematic circuit diagram of a reset circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a control circuit according to an embodiment of the present application;

Fig. 7 is a schematic circuit diagram of another lower circuit according to an embodiment of the present application;

fig. 8 is a timing chart according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the related art, a pin of a controller of a slave device in an SPI communication device is generally adopted to control the switching on and switching off of the slave device, and the problem of shortage of pin resources of the controller exists in the mode.

The embodiment of the application provides a control circuit applied to slave equipment in SPI communication equipment, which comprises a power-on circuit and a power-off circuit, wherein the power-on circuit outputs effective enabling signals to a power module when an SPI_CS signal is high level, an SPI_MOSI signal is low level and an SPI_CLK signal is low level based on input voltage, so that the power module provides power supply voltage for the slave equipment, and the slave equipment is started; and in the normal working process of the slave device, when the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal are all low, the power-down circuit outputs an effective power-off signal, and after receiving the effective power-off signal, the power-up circuit outputs an invalid enabling signal to the power module so as to enable the power module to stop providing power supply voltage for the slave device, and the slave device is powered off. Because the control circuit provided by the embodiment of the application controls the on/off of the slave device through the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal in SPI communication, the pins of the controller are not required to be used when the slave device is on/off, so that the pins of the controller can be reduced, the operation pressure of the controller is reduced, and the performance of the slave device is improved.

The following describes embodiments of the present application in detail.

As shown in fig. 1, a schematic structural diagram of a control circuit provided in an embodiment of the present application is applied to a slave device in an SPI communication device, and as can be seen from fig. 1, the control circuit includes a power-up circuit 11 and a power-down circuit 12;

A power-up circuit 11, configured to output a valid enable signal pwr_on to the power module when the spi_cs signal is at a high level, the spi_mosi signal is at a low level, and the spi_clk signal is at a low level, and output an invalid enable signal pwr_on to the power module after receiving a valid shutdown signal pwr_off sent by the power-down circuit 12, where the power module provides a power supply voltage pwr_out to the slave device when receiving the valid enable signal pwr_on, so that the slave device is turned ON, and the power module stops providing the power supply voltage pwr_out to the slave device when receiving the invalid enable signal pwr_on, so that the slave device is turned OFF;

the power-down circuit 12 is configured to send an active power-down signal pwr_off to the power-up circuit 11 based on the power supply voltage pwr_out when the spi_cs signal, the spi_mosi signal, and the spi_clk signal are all low during normal operation of the slave device.

In one embodiment, as shown in fig. 2, the power-on circuit 11 includes a power-on unit 111 and a signal latch unit 112;

A power-ON unit 111 for turning ON a path between the input voltage terminal and the enable signal terminal under the control of the high-level spi_cs signal to output an effective enable signal pwr_on;

The signal latch unit 112 is configured to control the power-ON unit 111 to keep ON a path between the input voltage terminal and the enable signal terminal when the power-OFF signal pwr_off is inactive, and to control the power-ON unit 111 to disconnect the path between the input voltage terminal and the enable signal terminal when the power-OFF signal pwr_off is active, so that the power-ON unit 111 outputs the inactive enable signal pwr_on.

IN the embodiment of the present application, the input voltage terminal is used for outputting the input voltage pwr_in, the enable signal terminal is used for outputting the enable signal pwr_on, when the spi_cs signal is at a high level, the power-ON unit 111 outputs the valid enable signal pwr_on, the slave device is turned ON, after the slave device is turned ON, when the power-OFF signal pwr_off is invalid, the power-ON unit 111 is controlled to keep ON the path between the input voltage terminal and the enable signal terminal, that is, the power-ON unit 111 keeps outputting the valid enable signal pwr_on even if the spi_cs signal is converted from a high level to a low level, and the power-ON unit 111 keeps outputting the valid enable signal pwr_on, thereby locking the enable signal pwr_on valid and putting the slave device into a power-ON state.

Specifically, as shown in fig. 2, the power-on unit 111 includes a first diode D1, a first resistor R1, a second resistor R2, a first switching tube M1, and a second switching tube M2;

the anode of the first diode D1 inputs SPI_CS signals, and the cathode of the first diode D1 is electrically connected with the control end of the first switch tube M1 and the first end of the first resistor R1;

The second end of the first resistor R1 and the second end of the first switch tube M1 are grounded;

The first end of the first switching tube M1 is electrically connected with the first end of the second resistor R2, the control end of the second switching tube M2 and the signal latching unit 112;

the second end of the second resistor R2 is electrically connected with the first end of the second switch tube M2, and inputs an input voltage PWR_IN;

A second terminal of the second switching tube M2 is electrically connected to the signal latch unit 112, and outputs an enable signal pwr_on.

As shown in fig. 2, the signal latch unit 112 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a third switching transistor M3;

the first end of the third resistor R3 is electrically connected with the control end of the second switching tube M2, and the second end of the third resistor R3 is electrically connected with the first end of the third switching tube M3;

The second end of the third switching tube M3 is electrically connected with the first end of the fifth resistor R5 and grounded, the control end of the third switching tube M3 is electrically connected with the second end of the fifth resistor R5 and the first end of the fourth resistor R4, and a shutdown signal PWR_OFF is input;

the second end of the fourth resistor R4 is electrically connected to the second end of the second switching tube M2.

In one embodiment, as shown in fig. 3, the lower circuit 12 includes a first isolation unit 121, a charge and discharge unit 122, and a first on-off unit 123;

A first isolation unit 121 for isolating and transmitting the SPI_CLK signal and the SPI_MOSI signal;

a charging and discharging unit 122 for charging based on the spi_clk signal and the spi_mosi signal during normal operation of the slave device, and discharging when both the spi_mosi signal and the spi_clk signal are at low level;

The first on-OFF unit 123 is configured to output an invalid shutdown signal pwr_off based on the power supply voltage pwr_out after the charging process and the charging of the charge-discharge unit are completed, and output an valid shutdown signal pwr_off based on the power supply voltage pwr_out after the discharging of the charge-discharge unit 122 is completed.

Specifically, as shown in fig. 3, the first isolation unit 121 includes a second diode D2 and a third diode D3;

the anode of the second diode D2 inputs the spi_mosi signal, and the cathode of the second diode D2 is electrically connected to the cathode of the third diode D3 and the charge/discharge unit 122;

The anode of the third diode D3 inputs the spi_clk signal.

As shown in fig. 3, the charge-discharge unit 122 includes a capacitor C and a sixth resistor R6;

The first end of the capacitor C is electrically connected with the first end of the sixth resistor R6, the cathode of the third diode D3 and the first on-off unit 123;

the second terminal of the capacitor C and the second terminal of the sixth resistor R6 are both grounded.

As shown in fig. 3, the first on-off unit includes a seventh resistor R7, a fourth switching tube M4, and a fifth switching tube M5;

The control end of the fourth switching tube M4 is electrically connected with the first end of the capacitor C, the first end of the fourth switching tube M4 is electrically connected with the first end of the seventh resistor R7 and the control end of the fifth switching tube M5, and the second end of the fourth switching tube M4 is grounded;

The first end of the fifth switching tube M5 is used for outputting a shutdown signal PWR_OFF, and the second end of the fifth switching tube M5 is grounded;

The second end of the seventh resistor R7 receives the power supply voltage pwr_out.

In one embodiment, as shown in fig. 4, the control circuit further includes a reset circuit 13;

and the reset circuit 13 is used for sending a reset signal RST to the slave device to reset the slave device when the SPI_CS signal and the SPI_CLK signal are both in high level during normal operation of the slave device.

Specifically, as shown in fig. 5, the reset circuit 13 includes a second isolation unit 131, an on-off control unit 132, and a second on-off unit 133;

a second isolation unit 131 for isolating and transmitting the SPI_CLK signal and the SPI_CS signal;

The on-off control unit 132 is configured to, when the received spi_clk signal and spi_cs signal are both at a high level, turn on a path between a power supply voltage terminal and a ground terminal to output a reset signal RST, where the power supply voltage terminal is configured to output a power supply voltage pwr_out.

As shown in fig. 5, the second isolation unit 131 includes a fourth diode D4 and a fifth diode D5;

the anode of the fourth diode D4 inputs the spi_clk signal, and the cathode of the fourth diode D4 is electrically connected to the on-off control unit 132;

The anode of the fifth diode D5 inputs the spi_cs signal, and the cathode of the fifth diode D5 is electrically connected to the on-off control unit 132.

The diodes in the first isolation unit and the second isolation unit in the embodiment of the application have the function of level isolation, so that signals at two ends of the diodes do not influence each other and normal communication of SPI (serial peripheral interface) at the speed of 25M and below is not influenced.

As shown in fig. 5, the on-off control unit 132 includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a sixth diode D6;

The first end of the eighth resistor R8 is electrically connected with the cathode of the fourth diode D4 and the first end of the ninth resistor R9, and the second end of the eighth resistor R8 is grounded;

The second end of the ninth resistor R9 is electrically connected to the first end of the tenth resistor R10, the anode of the sixth diode D6, and the second switching unit 133;

The cathode of the sixth diode D6 is electrically connected to the cathode of the fifth diode D5, the first terminal of the eleventh resistor R11, and the second terminal of the tenth resistor R10;

The second terminal of the eleventh resistor R11 is grounded.

As shown in fig. 5, the second switching unit 133 includes a twelfth resistor R12 and a fifth switching tube M5;

The first end of the twelfth resistor R12 is electrically connected with the power supply voltage end, the second end of the twelfth resistor R12 is electrically connected with the first end of the sixth switching tube M6, and a reset signal RST is output;

The control end of the sixth switching tube M6 is electrically connected with the second end of the ninth resistor R9, and the second end of the sixth switching tube M6 is grounded.

Embodiments of the present application are described in detail below with reference to the overall circuit diagram.

Fig. 6 is a complete circuit diagram of a control circuit according to an embodiment of the present application.

The power-ON circuit 11 IN the control circuit provided by the embodiment of the application comprises a power-ON function and a power-ON signal latching function, wherein the power-ON function is realized by a power-ON circuit 131, the power-ON signal latching function is realized by a latch signal unit 132, specifically, when an SPI_CS signal is at a high level, a first switch tube M1 and a second switch tube M2 are conducted, and a power-ON signal PWR_ON=PWR_IN is at a high level, namely the power-ON signal PWR_ON is a valid power-ON signal, so that the power-ON function is realized;

A power-ON signal latch function, when the power-ON signal pwr_on is at a high level, when the fifth switching tube M5 is not turned ON, the power-OFF signal pwr_off is at a high level, that is, the power-OFF signal pwr_off is not turned ON, the third switching tube M3 is turned ON, the control end of the second switching tube M2 is kept pulled down, and the second switching tube M2 is kept turned ON, at this time, even if the spi_cs signal is pulled down, the second switching tube M2 still can be kept at a conductive state, the output power-ON signal pwr_on still is at a high level, and the latch function of pwr_on is realized;

in the embodiment of the application, the power-on signal latching function can ensure the power supply stability of the module, and the influence of the level jump of SPI_CS on a power-on circuit during communication is shielded.

The reset circuit 13 in the control circuit provided by the embodiment of the application has a reset function and a clamping function;

A reset function, which requires that the SPI_CLK signal and the SPI_CS signal be high simultaneously when the reset function is implemented; because the levels of the two are similar, the current flowing through the ninth resistor R9 and the tenth resistor R10 is almost 0 at this moment, and the sixth diode D6 is kept in an off state because the voltage difference does not meet the conducting condition, the high-level spi_clk signal and the high-level spi_cs signal act on the sixth switching tube M6 through the ninth resistor R9 and the tenth resistor R10 respectively, the sixth switching tube M6 is conducted, and the reset signal RST is output, that is, the low level is output, and the reset is realized.

And the clamping function, during the SPI communication period, the SPI_CLK signal is a periodic pulse width signal, the SPI_CS signal is low, as long as the SPI_CS signal is low, the high pulse width of the SPI_CLK signal passes through the fourth diode D4, the ninth resistor R9, the sixth diode D6 and the eleventh resistor R11 to the ground, and the voltage at two ends of the sixth diode D6 is clamped at a level close to about 0.6V after the sixth diode D6 is conducted, so that the high level of the SPI_MOSI signal is divided by the ninth resistor R9 to ensure that the control end of the sixth switching tube M6 is clamped at a level close to about 0.6V, thereby shielding the reset function during the communication period, namely the aim of the clamping function of the reset circuit in the embodiment of the application is to ensure that the level fluctuation of the SPI_CLK signal cannot generate an effective reset signal during the communication period.

It should be noted that, the eleventh resistor R11 and the eighth resistor R8 provide a stable initial level for the control end of the sixth switching tube M6, and simultaneously shield the interference signals of the spi_mosi signal and the spi_cs signal when the conduction condition is not satisfied, so as to improve the anti-interference performance of the reset signal RST.

In the embodiment of the application, the power-down circuit is divided into an energy storage stage and a discharge stage;

In the energy storage stage, the implementation of energy storage needs to depend on the characteristics of an SPI bus, in a bus idle state, an SPI_CLK signal needs to be kept at a stable level, a high level or a low level, and in the embodiment of the application, the high level is taken as an example, when the SPI_CLK signal is at the high level, a capacitor C is charged through a third diode D2, after the capacitor C is full, a control end of a fourth switching tube M4 can be kept at the high level, and due to the energy storage effect of the capacitor C, the high level cannot disappear, even if the SPI_CLK signal is changed to the low level, the fourth switching tube M4 can still be kept to be conducted, the voltage of the control end of the fifth switching tube M5 is pulled down, so that the fifth switching tube M5 is kept to be turned off, and the clamping function of an upper circuit is ensured to be effective;

It should be noted that if the spi_clk signal is maintained at a low level in the bus idle state, an inverter unit may be added, and as shown in fig. 7, the inverter unit 71 includes a thirteenth resistor R13, a fourteenth resistor R14, and a seventh switching tube M7, the control terminal of the seventh switching tube M7 is electrically connected to the anode of the third diode D3 and the first terminal of the thirteenth resistor R13, the first terminal of the seventh switching tube M7 and the second terminal of the thirteenth resistor R13 are connected to the ground, the second terminal of the seventh switching tube M7 is connected to the first terminal of the fourteenth resistor R14, the spi_clk signal is input, and the second terminal of the fourteenth resistor R14 is electrically connected to the power supply voltage terminal pwr_out.

When the spi_clk signal is maintained at a low level, the signal output through the inverting unit 71 is at a high level.

In the discharging stage, to realize the power-down function, the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal need to be pulled down simultaneously; at this time, the capacitor C and the sixth resistor R6 form a discharging loop, in the implementation, the sizes of the resistor and the capacitor depend ON the communication rate, the level of the control end of the fourth switching tube M4 is slowly released, the fourth switching tube M4 is turned OFF, at this time, because the module is not yet powered OFF, the output voltage pwr_out is high, the fifth switching tube M5 is turned ON, the shutdown signal pwr_off is low, i.e. the valid shutdown signal pwr_off, the third switching tube M3 is turned OFF, and because the spi_cs signal is low, the first switching tube M1 is not turned ON, the control end of the second switching tube M2 is high, the second switching tube M2 is turned OFF, the enable signal pwr_on is low, i.e. the invalid enable signal pwr_on, and the slave device is powered OFF.

It should be noted that in the embodiment of the present application, if only one signal of spi_clk is connected, one signal of spi_mosi may be added, and increasing the shutdown condition is helpful for improving the anti-interference performance of the circuit.

The following describes the overall operation flow of the control circuit according to the embodiment of the present application with reference to the timing chart shown in fig. 8:

Stage T0, slave device remains powered off:

When the function of the slave device is not needed, the SPI_CS signal is low, the enable signal PWR_ON and the shutdown signal PWR_OFF are both low, and the slave device does not supply power;

stage T1, slave device power up:

when power is required to be supplied from the equipment, the SPI_CS signal is high level, the SPI_MOSI signal and the SPI_CLK signal are kept low level, the power-ON circuit works at the moment, the enable signal PWR_ON is high level, then the shutdown signal PWR_OFF is high clamp PWR_ON, and the SPI_CS signal is released;

T2 phase, slave reset:

After a period of power-on, simultaneously pulling up an SPI_CS signal and an SPI_MOSI signal, wherein RST is low level, and resetting slave equipment;

T3 phase, normal communication:

After reset, the SPI_MOSI signal is low level, the SPI_CS signal and the SPI_SCL signal are kept high level, and preparation is carried out before communication, when communication is needed, three signals are controlled according to a normal communication flow, as long as the SPI_SCK signal is kept high level or periodically high level in an idle state, and the level changes of the SPI_CS signal, the SPI_MOSI signal and the SPI_SCL signal do not influence the level states of an enable signal PWR_ON, a shutdown signal PWR_OFF and a reset signal RST;

And a T4 stage, wherein the slave device is powered down:

when power-down is needed, power-down can be realized only by keeping the SPI_CS signal, the SPI_MOSI signal and the SPI_CLK signal at low level until the discharge of the energy storage capacitor C in the power-down circuit is completed.

The control circuit provided by the embodiment of the application uses the SPI communication characteristic to carry out time-sharing multiplexing on signals, and realizes more flexible power-on and power-off or reset control on the premise of not adding a new control line; adding a clamping circuit in the control circuit to stabilize the state of the control signal; the diode is added to isolate signals, so that the communication quality of SPI is ensured; the signal filtering and circuit latching are added, so that the stability of a special model is enhanced.

Based on the same inventive concept, the embodiment of the application also provides a slave device, the principle of solving the technical problem of the slave device is similar to that of the control circuit, and the repetition is omitted.

The slave device provided by the embodiment of the application comprises a power supply module and any one of the control circuits, wherein the control circuit comprises a power-on circuit and a power-off circuit;

The power-on circuit is respectively and electrically connected with the SPI_CS signal end, the input voltage end, the enabling end of the power module and the power-off circuit;

The power module is used for outputting a power supply voltage through the power supply voltage end based on the input voltage output by the input voltage end under the control of an effective enabling signal output by the power-on circuit so as to start the slave device, and stopping outputting the power supply voltage under the control of an ineffective enabling signal output by the power-on circuit so as to shut down the slave device, wherein the ineffective enabling signal is output by the power-on circuit based on an effective shutdown signal output by the power-off circuit.

The power supply module IN the embodiment of the application can be a power supply chip, the input end IN of the power supply chip inputs the input voltage pwr_in, the enable end EN of the power supply chip inputs the enable signal pwr_on, and the output end of the power supply chip outputs the supply voltage pwr_out.

The slave equipment provided by the embodiment of the application has the advantages of less control lines and lower connection cost; the control circuit is modularized, supports transplanting and cutting at any position, and is more flexible; the software time sequence is converted into a hardware signal, so that the requirement on the slave equipment is lower, and the compatibility is stronger.

Various modifications and alterations of this invention may be made by those skilled in the art without departing from the spirit and scope of this invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A control circuit for use with a slave device in an SPI communications device, comprising:

2. The control circuit of claim 1, wherein the power-up circuit comprises a power-on unit and a signal latch unit;

3. The control circuit of claim 2, wherein the power-on unit comprises a first diode, a first resistor, a second resistor, a first switching tube, and a second switching tube;

4. The control circuit of claim 3, wherein the signal latching unit comprises a third resistor, a fourth resistor, a fifth resistor, and a third switching tube;

5. The control circuit of claim 1, wherein the power down circuit comprises a first isolation unit, a charge-discharge unit, and a first on-off unit;

6. The control circuit of claim 5, wherein the first isolation unit comprises a second diode and a third diode;

An anode of the third diode inputs the SPI_CLK signal.

7. The control circuit of claim 6, wherein the charge-discharge unit includes a capacitor and a sixth resistor;

8. The control circuit of claim 7, wherein the first on-off unit comprises a seventh resistor, a fourth switching tube, and a fifth switching tube;

the second terminal of the seventh resistor receives the supply voltage.

9. The control circuit according to any one of claims 1 to 8, further comprising a reset circuit;

10. The control circuit of claim 9, wherein the reset circuit comprises a second isolation unit, an on-off control unit, and a second on-off unit;

11. The control circuit of claim 10, wherein the second isolation unit comprises a fourth diode and a fifth diode;

12. The control circuit of claim 11, wherein the on-off control unit comprises an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a sixth diode;

the second end of the eleventh resistor is grounded.

13. The control circuit of claim 12, wherein the second switching unit includes a twelfth resistor and a sixth switching tube;

14. A slave device, comprising a power module and the control circuit according to any one of claims 1 to 13, wherein the control circuit comprises a power-up circuit and a power-down circuit;