CN117997347A - Dynamic comparator circuit applied to wide input common-mode voltage range in SARADC - Google Patents
Dynamic comparator circuit applied to wide input common-mode voltage range in SARADC Download PDFInfo
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- CN117997347A CN117997347A CN202410141483.0A CN202410141483A CN117997347A CN 117997347 A CN117997347 A CN 117997347A CN 202410141483 A CN202410141483 A CN 202410141483A CN 117997347 A CN117997347 A CN 117997347A
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- 239000008186 active pharmaceutical agent Substances 0.000 description 2
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- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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- Theoretical Computer Science (AREA)
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Abstract
The invention discloses a dynamic comparator circuit applied to a wide input common-mode voltage range in SARADC, which comprises: a pre-amplifier and latch, and a power supply terminal VDD; PM1 and PM2 are connected respectively to the both ends of power supply end VDD, PM1 connects input pair pipe NM1, input pair pipe NM1 connects the VINN, PM2 connects input pair pipe NM2, input pair pipe NM2 connects the VINP, the comparator LATCH is connected to the connecting wire between PM1 and the input pair pipe NM1, the comparator LATCH is connected to VOUTN-, voutp+. The novel dynamic comparator circuit applied to SARADC widens the input common-mode voltage of the comparator, weakens the performance reduction caused by input common-mode offset in the practical application of the ADC, and weakens the channel length modulation effect of the MOS device under the PVT condition, so that the performance of the dynamic comparator is more stable under the PVT condition, and has engineering significance.
Description
Technical Field
The invention relates to the technical field of comparators, in particular to a dynamic comparator circuit applied to a wide input common-mode voltage range in SARADC.
Background
The current high-speed dynamic comparator circuit is widely applied to high-precision SARADC, and the performance of the dynamic comparator directly influences the final quantization precision and linearity of the ADC. Under the actual operating condition of the ADC, the conventional high-speed dynamic comparator is very susceptible to the MOS device operating in the unsaturated region due to the offset of the input common-mode voltage of the ADC, thereby causing the performance of the comparator to be degraded.
To sum up, we propose a dynamic comparator circuit for a wide input common-mode voltage range in SARADC.
Disclosure of Invention
The invention aims to provide a dynamic comparator circuit applied to a wide input common-mode voltage range in SARADC, which solves the existing problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a dynamic comparator circuit for a wide input common mode voltage range in SARADC, comprising:
A pre-amplifier and a latch are provided,
A power supply terminal VDD;
PM1 and PM2 are connected respectively to the both ends of power supply end VDD, PM1 connects input pair pipe NM1, input pair pipe NM1 connects the VINN, PM2 connects input pair pipe NM2, input pair pipe NM2 connects the VINP, the comparator LATCH is connected to the connecting wire between PM1 and the input pair pipe NM1, the comparator LATCH is connected to VOUTN-, voutp+.
Preferably, the middle part of the connecting line of the PM1 and the PM2 is connected with a resistor R1 and a resistor R2, and the gate drains of the PM1 and the PM2 are connected through the resistor R1 and the resistor R2.
Preferably, the VFB point intermediate the resistor R1 and the resistor R2 is connected to the source of PM3, and the PM3 is connected to the resistor R3.
Preferably, the gates of PM1 and PM2 are connected to the drain of PM3, and the drain and gate of PM3 are connected through R3.
Preferably, one end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the drains of the first stage NM1 and NM2, and the other end is connected to the input end of the latch.
Preferably, the gates and drains of the PM1, PM2 are cross-connected to PM3, PM4, and the PM3, PM4 are diode-connected.
Preferably, the gate and the drain of PM3 are connected to PM5, and the gate and the drain of PM5 are connected to both ends of the resistor R1.
Preferably, the gate and the drain of the PM4 are connected to the PM6, and the gate and the drain of the PM6 are connected to both ends of the resistor R2.
Preferably, one end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the drains of the first stage NM1 and the second stage NM2, and the other end is connected to the input end of the latch.
Compared with the prior art, the invention has the following beneficial effects:
The novel dynamic comparator circuit applied to SARADC widens the input common-mode voltage of the comparator, weakens the performance reduction caused by input common-mode offset in the practical application of the ADC, and weakens the channel length modulation effect of the MOS device under the PVT condition, so that the performance of the dynamic comparator is more stable under the PVT condition, and has engineering significance.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
Fig. 2 is a schematic circuit diagram of embodiment 2 of the present invention;
fig. 3 is a schematic circuit diagram of embodiment 3 of the present invention;
fig. 4 is a schematic circuit diagram of embodiment 4 of the present invention;
FIG. 5 is a comparative schematic of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The invention widens the input common-mode voltage range of the first-stage pre-amplifier based on the dynamic comparator structure of the traditional pre-amplifier and latch, and avoids the influence of the input common-mode voltage on the second-stage latch by using the Auto-zero technology of capacitive coupling.
Taking an NMOS as an input pair of transistors of a preamplifier as an example, a conventional preamplifier has a load in the form of a diode-like connection (gate-drain self-bias connection), when the diode-connected MOS device is in saturation region operation, its source-drain voltage (V DS) is at least greater than a threshold voltage (V TH), so for the input pair of transistors, in order to keep operating in saturation region, its gate voltage must be lower than the supply voltage (V DD) minus a threshold voltage, which is the upper limit of the input common mode level.
The invention is based on that, the grid electrode and the drain electrode of the MOS device connected with the diode are led to another current branch, the grid electrode and the drain electrode of the MOS device are connected to the source electrode and the drain electrode of the other MOS device, the grid electrode of the MOS device is self-biased through an adjustable resistor connected with the drain electrode, and the drain voltage of the MOS device in the original diode connection form is regulated through designing the current of the branch, the width and the length of the MOS device and the magnitude of the resistance value, so that the V DS of the MOS device in the original diode connection form can normally work only by losing one V DSsat(＝VGS-VTH) voltage, and the upper limit of the common mode level of the input pair tube is also expanded to V DD-VDsat instead of losing one V TH. Under the deep submicron CMOS process, the structure not only widens the common mode input, but also weakens the channel length modulation effect of the MOS device under PVT, so that the performances such as gain bandwidth and the like of the first-stage preamplifier are more stable.
The output of the first stage is capacitively coupled to the latch input of the second stage and a switch controlled Auto-zero technique is used at the latch input such that the offset of the input common mode level of the first stage does not affect the input common mode of the second stage and effectively reduces the offset of the first stage preamplifier.
Example 1:
As shown in fig. 1, a dynamic comparator circuit applied to a wide input common-mode voltage range in SARADC has a common-mode voltage of NM1 and NM2 smaller than V DD-VTH because the gate drains of PM1/PM2 are connected through resistors R1/R2.
Example 2:
As shown in fig. 2, on the basis of embodiment 1, the VFB point between R1 and R2 is connected to the source of PM3, the gate of PM1/PM2 is connected to the drain of PM3, the drain and gate of PM3 are connected through R3, and by adjusting the current of the branch, the size of PM3 and the resistance value of R3, the maximum common mode level of the input pair of transistors NM1/NM2 is effectively increased to V DD-VDSsat on the premise of ensuring the original circuit common mode feedback function to be unchanged. Meanwhile, a circuit in a yellow frame is added in front of the second-stage latch, one end of each capacitor C1 and C2 is connected with the drain electrodes of the first-stage NM1 and NM2, the other end of each capacitor C1 and C2 is connected with the input end of the latch, and a switch-controlled Auto-zero circuit is added, so that the input common-mode level of the latch is independently controlled by VCM_AZ and is not influenced by the input common-mode voltage of the first-stage, and the input common-mode voltage range of the whole dynamic comparator is effectively expanded.
Fig. 5 shows a comparison of the performance of some amplifiers for the conventional and the dynamic comparators of the patent architecture, clearly showing that the performance of the use of the patent is flatter as the input common mode level changes.
Embodiment 3:
As shown in fig. 3, on the basis of embodiment 1, since the gates and drains of PM1, PM2 are cross-connected, and PM3, PM4 are diode-connected, the input common mode voltage of NM1 and NM2 needs to be smaller than V DD-VTH.
Embodiment 4:
As shown in fig. 4, on the basis of embodiment 3, by the same connection method as in fig. 1, PM5 and R1 are added to change the connection mode of the gates and the drains of PM1 and PM3, PM6 and R2 are added to change the connection mode of the gates and the drains of PM2 and PM4, and on the premise of ensuring that the original circuit hysteresis function is unchanged, the maximum common mode level of the input pair transistors NM1/NM2 is effectively increased to V DD-VDSsat.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. A dynamic comparator circuit for a wide input common mode voltage range in SARADC, comprising:
A pre-amplifier and a latch are provided,
A power supply terminal VDD;
PM1 and PM2 are connected respectively to the both ends of power supply end VDD, PM1 connects input pair pipe NM1, input pair pipe NM1 connects the VINN, PM2 connects input pair pipe NM2, input pair pipe NM2 connects the VINP, the comparator LATCH is connected to the connecting wire between PM1 and the input pair pipe NM1, the comparator LATCH is connected to VOUTN-, voutp+.
2. A dynamic comparator circuit for a wide input common mode voltage range in SARADC according to claim 1, wherein the middle part of the PM1 and PM2 connection line is connected to a resistor R1 and a resistor R2, and the gates of PM1 and PM2 are connected through a resistor R1 and a resistor R2.
3. A dynamic comparator circuit for a wide input common mode voltage range for use in SARADC as claimed in claim 1, wherein the VFB point intermediate the resistor R1 and the resistor R2 is connected to the source of PM3, and wherein the PM3 is connected to the resistor R3.
4. A dynamic comparator circuit for a wide input common mode voltage range in SARADC according to claim 3, wherein the gates of PM1 and PM2 are connected to the drain of PM3, the drain and gate of PM3 being connected by R3.
5. A dynamic comparator circuit according to claim 1, applied to a wide input common mode voltage range in SARADC, wherein one end of the capacitor C1 and one end of the capacitor C2 are connected to the drains of the first stage NM1 and NM2, respectively, and the other end is connected to the input of the latch.
6. A dynamic comparator circuit for a wide input common mode voltage range in sardc according to claim 1, characterized in that the gate and drain of PM1, PM2 are cross-connected PM3, PM4, the PM3, PM4 being a diode-formed connection.
7. The dynamic comparator circuit according to claim 6, wherein the gate and drain of PM3 are connected to PM5, and the gate and drain of PM5 are connected across resistor R1.
8. The dynamic comparator circuit according to claim 6, wherein the gate and drain of PM4 are connected to PM6, and the gate and drain of PM6 are connected across resistor R2.
9. The dynamic comparator circuit according to claim 6, wherein one end of the capacitor C1 and one end of the capacitor C2 are respectively connected to the drains of the first stage NM1 and NM2, and the other end is connected to the input end of the latch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410141483.0A CN117997347A (en) | 2024-02-01 | 2024-02-01 | Dynamic comparator circuit applied to wide input common-mode voltage range in SARADC |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410141483.0A CN117997347A (en) | 2024-02-01 | 2024-02-01 | Dynamic comparator circuit applied to wide input common-mode voltage range in SARADC |
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| CN117997347A true CN117997347A (en) | 2024-05-07 |
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| CN202410141483.0A Pending CN117997347A (en) | 2024-02-01 | 2024-02-01 | Dynamic comparator circuit applied to wide input common-mode voltage range in SARADC |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107882A (en) * | 1997-12-11 | 2000-08-22 | Lucent Technologies Inc. | Amplifier having improved common mode voltage range |
| US20120229214A1 (en) * | 2011-03-07 | 2012-09-13 | Nxp B.V. | Amplifier Circuit and Method |
| CN113193870A (en) * | 2021-04-21 | 2021-07-30 | 江苏信息职业技术学院 | SAR ADC with low power consumption and low layout area |
| CN214756299U (en) * | 2021-04-21 | 2021-11-16 | 江苏信息职业技术学院 | 12-bit differential SAR ADC |
| CN114326895A (en) * | 2021-12-16 | 2022-04-12 | 上海川土微电子有限公司 | Comparator circuit capable of expanding input range |
| CN220401729U (en) * | 2023-06-29 | 2024-01-26 | 苏州兆凯电子有限公司 | Dynamic comparator |
-
2024
- 2024-02-01 CN CN202410141483.0A patent/CN117997347A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6107882A (en) * | 1997-12-11 | 2000-08-22 | Lucent Technologies Inc. | Amplifier having improved common mode voltage range |
| US20120229214A1 (en) * | 2011-03-07 | 2012-09-13 | Nxp B.V. | Amplifier Circuit and Method |
| CN102684619A (en) * | 2011-03-07 | 2012-09-19 | Nxp股份有限公司 | Amplifier circuit and method |
| CN113193870A (en) * | 2021-04-21 | 2021-07-30 | 江苏信息职业技术学院 | SAR ADC with low power consumption and low layout area |
| CN214756299U (en) * | 2021-04-21 | 2021-11-16 | 江苏信息职业技术学院 | 12-bit differential SAR ADC |
| CN114326895A (en) * | 2021-12-16 | 2022-04-12 | 上海川土微电子有限公司 | Comparator circuit capable of expanding input range |
| CN220401729U (en) * | 2023-06-29 | 2024-01-26 | 苏州兆凯电子有限公司 | Dynamic comparator |
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