CN117954318A - Preparation method of soft and fast recovery FRD diode chip - Google Patents
Preparation method of soft and fast recovery FRD diode chip Download PDFInfo
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- CN117954318A CN117954318A CN202410010839.7A CN202410010839A CN117954318A CN 117954318 A CN117954318 A CN 117954318A CN 202410010839 A CN202410010839 A CN 202410010839A CN 117954318 A CN117954318 A CN 117954318A
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- 229910052796 boron Inorganic materials 0.000 claims abstract description 41
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- HZAXFHJVJLSVMW-UHFFFAOYSA-N 2-Aminoethan-1-ol Chemical compound NCCO HZAXFHJVJLSVMW-UHFFFAOYSA-N 0.000 claims description 5
- KIZQNNOULOCVDM-UHFFFAOYSA-M 2-hydroxyethyl(trimethyl)azanium;hydroxide Chemical compound [OH-].C[N+](C)(C)CCO KIZQNNOULOCVDM-UHFFFAOYSA-M 0.000 claims description 5
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention relates to the technical field of soft fast recovery diode chips, in particular to a preparation method of a soft fast recovery FRD diode chip, which comprises a diffusion process and a GPP process and is characterized in that the diffusion process comprises the following steps: step one, diffusion pretreatment; step two, phosphorus expansion treatment: performing diffusion treatment on the N surface of the silicon wafer treated in the first step, performing primary diffusion by adopting low-concentration phosphor paper, and performing secondary diffusion by adopting normal-concentration phosphor paper; step three, blowing sand once; step four, boron expansion treatment; step five, secondary sand blowing: and when the diffusion process is completed, the chip manufactured by the silicon chip can obtain higher reverse breakdown voltage under the condition that the forward voltage is not remarkably increased, the newly added base region N is higher than the impurity concentration of the original base region N ‑ by adopting a double-base region diffusion process, and when reverse bias voltage is applied, the time for extracting carriers is prolonged, namely the tb value is increased, the softness factor S value is increased to about 0.65, and the softness of the diode is effectively improved.
Description
Technical Field
The invention relates to the technical field of soft and fast recovery diode chips, in particular to a preparation method of a soft and fast recovery FRD diode chip.
Background
The modern power electronic technology widely uses switching devices such as an IGBT (Insulated Gate Bipolar Transistor, an insulated gate bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor FIELD EFFECT Transistor, a metal oxide semiconductor field effect Transistor) and the like, and has higher requirements on a fast recovery diode (Fast Recovery Diode, abbreviated as FRD) matched with the switching devices, so that the switching devices are required to have high reverse blocking voltage, small forward transient voltage drop and short reverse recovery time, and also have soft recovery characteristics (namely, a softness factor is large), and the fast recovery diode with the characteristics is called a soft fast recovery diode (Soft Fast Recovery Diode, abbreviated as SFRD).
At present, parameters of a domestic fast recovery diode: reverse breakdown voltage 1100V, reverse recovery time 500ns. Softness factor is about 0.35, and the characteristics are very hard. The reverse breakdown voltage of the international fast recovery diode is 1300V, the reverse recovery time is 300ns, and the softness factor is about 0.55. With the deep development of power electronics technology, various semiconductor device technologies are continuously advanced and frequencies are continuously increased, which puts new requirements on a fast recovery diode matched with the semiconductor device technology, namely smaller Trr and larger softness factors.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a preparation method of a soft fast recovery FRD diode chip.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the preparation method of the soft fast recovery FRD diode chip comprises a diffusion process and a GPP process, wherein the diffusion process comprises the following steps of:
step one, diffusion pretreatment: firstly, mechanically polishing a silicon wafer raw material to obtain a polished substrate, and then cleaning the surface of the polished substrate through a silicon wafer cleaning liquid;
Step two, phosphorus expansion treatment: performing diffusion treatment on the N surface of the silicon wafer treated in the first step, performing primary diffusion by adopting low-concentration phosphor paper, and performing secondary diffusion by adopting normal-concentration phosphor paper;
Step three, sand blowing once: the silicon wafer after the phosphorus expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 40-50cm/min, the P surface is upward, and sand blasting is carried out at a pressure of 0.9-1.0Kg/cm 2;
Step four, boron expansion treatment: performing boron surface diffusion on the P surface of the silicon wafer;
Step five, secondary sand blowing: the silicon wafer subjected to boron expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 40-50cm/min, is blown on both sides, and is subjected to sand blasting at a pressure of 0.9-1.0Kg/cm 2, so that a diffusion process is completed.
Preferably, in the first step, a silicon wafer with a resistivity of 45-50Ω·cm and a thickness t=250±5μm is selected.
Preferably, in the first step, the silicon wafer cleaning solution comprises the following components in parts by weight: 80-100 parts of deionized water, 5-8 parts of nano abrasive, 1-3 parts of amphoteric surfactant and 4-6 parts of organic amine; the nanometer abrasive is amino-terminated polyether coated nanometer alumina, the particle size of the nanometer alumina is 20-40nm, and the mass ratio of the nanometer alumina to the amino-terminated polyether is (3-8): 1, one or more of the amphoteric surfactants alkyl amino propionate, alkyl dimethyl betaine, alkyl hydroxy sulfopropyl betaine, alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethyl ammonium hydroxide, tetraethyl ammonium hydroxide, tetrapropyl ammonium hydroxide, tetrabutyl ammonium hydroxide, trimethyl benzyl ammonium hydroxide, trimethyl hydroxyethyl ammonium hydroxide, dimethyl dihydroxyethyl ammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine and diethanolamine.
Preferably, in the second step, the pre-heating treatment of attaching phosphorus is carried out before the first diffusion treatment, the silicon wafer is horizontally placed on a quartz boat with the N face upwards, then the low-concentration phosphorus paper is attached on the N face of the silicon wafer, the silicon wafer is plugged into a low-temperature furnace by a baffle plate, and the silicon wafer is preheated to 280-300 ℃.
Preferably, in the second step, low-concentration phosphor paper is adopted for primary diffusion, the primary diffusion temperature is 1180-1220 ℃, the time is 6-10h, and the final diffusion depth is 80 μm; and then adopting normal-concentration phosphorus paper to carry out secondary diffusion, wherein the temperature of the secondary diffusion is 1230-1280 ℃, the time is 2-4h, and the final diffusion depth is 50 mu m.
Preferably, in the second step, after the primary diffusion is completed, preheating the normal concentration phosphor paper in the cooling process of the diffusion furnace, cooling the diffusion furnace to 250-300 ℃, heating the normal concentration phosphor paper to 250-300 ℃, installing the normal concentration phosphor paper, plugging the normal concentration phosphor paper into the diffusion furnace by using a baffle plate, and performing secondary diffusion treatment.
Preferably, in the fourth step, boron impurities are coated on the P surface of the silicon wafer, the coated silicon wafer is placed on an electric heating plate for drying, then the boron surfaces of the silicon wafer are opposite, the silicon wafers are stacked one by one, the silicon wafer is vertically placed on a quartz boat, and is plugged by a baffle plate, and the boron is carried out in a boron expansion furnace, wherein the boron expansion treatment is carried out at 950-1050 ℃ for 1-3h.
Preferably, in the third step and the fifth step, after the sand blowing is completed, the silicon wafer is cleaned.
The beneficial effects of the invention are as follows:
1. Compared with the traditional FRD chip, the chip manufactured by the silicon chip can obtain higher reverse breakdown voltage under the condition that forward voltage is not remarkably increased by selecting the silicon chip with the resistivity of 45-50Ω & cm and the thickness of T=250+/-5 mu m, and the newly added base region N is higher than the impurity concentration of the original base region N - by adopting a double base region diffusion process, so that the time for extracting carriers is prolonged when reverse bias is applied, namely the tb value is increased, the softness factor S value is increased to about 0.65, and the softness of the diode is effectively improved.
2. In the diffusion process, a double-base region diffusion process is adopted, when reverse bias is applied, the reverse recovery time Trr is also greatly increased, in order to reduce the reverse recovery time to a reasonable range, improve the working frequency of a device, the platinum expansion temperature is improved to about 920 ℃ from 880 ℃, the reverse recovery time of a diode is controlled to be less than 250ns, the platinum expansion temperature is improved, the Trr level is reduced, and passivation protection is carried out according to the traditional GPP process.
3. In the diffusion process, after the primary diffusion is finished, the normal concentration phosphor paper is preheated in the cooling process of the diffusion furnace, so that the operation time can be effectively saved, the energy is saved, and the treatment efficiency is improved.
4. In the diffusion process, the surface of the polishing substrate is cleaned by a silicon wafer cleaning liquid, the cleaning liquid contains a small amount of nano abrasive, the nano abrasive is amino-terminated polyether coated nano alumina, the polishing effect can be further improved, and the nano abrasive has elastic coating, so that scratches on the silicon wafer can be avoided.
Drawings
FIG. 1 is a schematic diagram of a dual base diffusion structure of a soft fast recovery FRD diode chip according to the present invention;
Fig. 2 is a waveform diagram of current and voltage during reverse recovery of a soft fast recovery FRD diode chip according to the present invention.
In the figure:
1. A single base diffusion sheet; 110. original N + region; 111. original N - region; 112. original P + region; 2. a double base diffusion sheet; 220. an N + region; 221. an N region; 222. an N - region; 223. region P +.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
In embodiment 1, a method for manufacturing a soft fast recovery FRD diode chip includes a diffusion process and a GPP process, wherein the diffusion process includes the following steps:
step one, diffusion pretreatment: firstly, mechanically polishing a silicon wafer raw material to obtain a polished substrate, and then cleaning the surface of the polished substrate through a silicon wafer cleaning liquid;
Step two, phosphorus expansion treatment: performing diffusion treatment on the N surface of the silicon wafer treated in the first step, performing primary diffusion by adopting low-concentration phosphor paper, and performing secondary diffusion by adopting normal-concentration phosphor paper;
step three, sand blowing once: the silicon wafer subjected to the phosphorus expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 40cm/min, the P surface is upward, and sand blasting is carried out at a pressure of 0.9Kg/cm 2;
Step four, boron expansion treatment: performing boron surface diffusion on the P surface of the silicon wafer;
Step five, secondary sand blowing: the silicon wafer subjected to boron expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 40cm/min, is blown on both sides, and is subjected to sand blasting at a pressure of 0.9Kg/cm 2, so that a diffusion process is completed.
In the first step, a silicon wafer with the resistivity of 45 Ω·cm and the thickness t=245 μm is selected.
In the first step, the silicon wafer cleaning liquid comprises the following components in parts by weight: 80 parts of deionized water, 5 parts of nano abrasive, 1 part of amphoteric surfactant and 4 parts of organic amine; the nanometer abrasive is amino-terminated polyether coated nanometer alumina, the particle size of the nanometer alumina is 20-40nm, and the mass ratio of the nanometer alumina to the amino-terminated polyether is 3:1, one or more of the amphoteric surfactants alkyl amino propionate, alkyl dimethyl betaine, alkyl hydroxy sulfopropyl betaine, alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethyl ammonium hydroxide, tetraethyl ammonium hydroxide, tetrapropyl ammonium hydroxide, tetrabutyl ammonium hydroxide, trimethyl benzyl ammonium hydroxide, trimethyl hydroxyethyl ammonium hydroxide, dimethyl dihydroxyethyl ammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine and diethanolamine.
In the second step, pre-heating treatment of attaching phosphorus is carried out before primary diffusion treatment, the silicon wafer is horizontally placed on a quartz boat with the N face upwards, then low-concentration phosphorus paper is attached to the N face of the silicon wafer, the silicon wafer is plugged into a low-temperature furnace by a baffle plate, and the silicon wafer is preheated to 280 ℃.
In the second step, low-concentration phosphor paper is adopted for primary diffusion, the primary diffusion temperature is 1180 ℃, the time is 6 hours, and the final diffusion depth is 75 mu m; and then adopting normal-concentration phosphor paper to carry out secondary diffusion, wherein the temperature of the secondary diffusion is 1230 ℃, the time is 2 hours, and the final diffusion depth is 45 mu m.
And in the second step, after the primary diffusion is finished, preheating the normal-concentration phosphor paper in the cooling process of the diffusion furnace, cooling the diffusion furnace to 250 ℃, heating the normal-concentration phosphor paper to 250 ℃, loading the normal-concentration phosphor paper, and plugging the normal-concentration phosphor paper into the diffusion furnace by using a baffle plate to perform secondary diffusion treatment.
In the fourth step, boron impurities are coated on the P surface of the silicon wafer firstly, the coated silicon wafer is placed on an electric heating plate for drying, then the boron surfaces of the silicon wafer are opposite, two silicon wafers are stacked, the silicon wafers are vertically placed on a quartz boat after being stacked, and are plugged by a baffle plate, the silicon wafers are put into a boron expansion furnace for boron expansion, and the boron expansion treatment is carried out at 950 ℃ for 1 hour.
And in the third step and the fifth step, after the sand blowing is finished, cleaning the silicon wafer.
In embodiment 2, a method for manufacturing a soft fast recovery FRD diode chip includes a diffusion process and a GPP process, wherein the diffusion process includes the following steps:
step one, diffusion pretreatment: firstly, mechanically polishing a silicon wafer raw material to obtain a polished substrate, and then cleaning the surface of the polished substrate through a silicon wafer cleaning liquid;
Step two, phosphorus expansion treatment: performing diffusion treatment on the N surface of the silicon wafer treated in the first step, performing primary diffusion by adopting low-concentration phosphor paper, and performing secondary diffusion by adopting normal-concentration phosphor paper;
Step three, sand blowing once: the silicon wafer subjected to the phosphorus expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 50cm/min, the P surface is upwards, and sand blasting is carried out at a pressure of 1.0Kg/cm 2;
Step four, boron expansion treatment: performing boron surface diffusion on the P surface of the silicon wafer;
step five, secondary sand blowing: the silicon wafer subjected to boron expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 50cm/min, is blown on both sides, and is sandblasted at a pressure of 1.0Kg/cm 2, so that the diffusion process is completed.
In the first step, a silicon wafer with resistivity of 50Ω·cm and thickness t=255 μm is selected.
In the first step, the silicon wafer cleaning liquid comprises the following components in parts by weight: 100 parts of deionized water, 8 parts of nano abrasive, 3 parts of amphoteric surfactant and 6 parts of organic amine; the nanometer abrasive is amino-terminated polyether coated nanometer alumina, the particle size of the nanometer alumina is 20-40nm, and the mass ratio of the nanometer alumina to the amino-terminated polyether is 8:1, one or more of the amphoteric surfactants alkyl amino propionate, alkyl dimethyl betaine, alkyl hydroxy sulfopropyl betaine, alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethyl ammonium hydroxide, tetraethyl ammonium hydroxide, tetrapropyl ammonium hydroxide, tetrabutyl ammonium hydroxide, trimethyl benzyl ammonium hydroxide, trimethyl hydroxyethyl ammonium hydroxide, dimethyl dihydroxyethyl ammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine and diethanolamine.
In the second step, pre-heating the phosphorus attached before the first diffusion treatment, horizontally placing the silicon wafer on a quartz boat with the N face upwards, then attaching low-concentration phosphorus paper on the N face of the silicon wafer, plugging the silicon wafer into a low-temperature furnace by a baffle plate, and pre-heating to 300 ℃.
In the second step, low-concentration phosphor paper is adopted for primary diffusion, the primary diffusion temperature is 1220 ℃, the time is 10 hours, and the final diffusion depth is 85 mu m; and then adopting normal-concentration phosphor paper to carry out secondary diffusion, wherein the temperature of the secondary diffusion is 1280 ℃, the time is 4 hours, and the final diffusion depth is 55 mu m.
And in the second step, after the primary diffusion is finished, preheating the normal-concentration phosphor paper in the cooling process of the diffusion furnace, cooling the diffusion furnace to 300 ℃, heating the normal-concentration phosphor paper to 300 ℃, loading the normal-concentration phosphor paper, and plugging the normal-concentration phosphor paper into the diffusion furnace by using a baffle plate to perform secondary diffusion treatment.
In the fourth step, boron impurities are coated on the P surface of the silicon wafer firstly, the coated silicon wafer is placed on an electric heating plate for drying, then the boron surfaces of the silicon wafer are opposite, two silicon wafers are stacked, the silicon wafers are vertically placed on a quartz boat after being stacked, and are plugged by a baffle plate, the silicon wafers are put into a boron expansion furnace for boron expansion, and the boron expansion treatment is carried out at 1050 ℃ for 3 hours.
And in the third step and the fifth step, after the sand blowing is finished, cleaning the silicon wafer.
In embodiment 3, a method for manufacturing a soft fast recovery FRD diode chip includes a diffusion process and a GPP process, the diffusion process includes the steps of:
step one, diffusion pretreatment: firstly, mechanically polishing a silicon wafer raw material to obtain a polished substrate, and then cleaning the surface of the polished substrate through a silicon wafer cleaning liquid;
Step two, phosphorus expansion treatment: performing diffusion treatment on the N surface of the silicon wafer treated in the first step, performing primary diffusion by adopting low-concentration phosphor paper, and performing secondary diffusion by adopting normal-concentration phosphor paper;
Step three, sand blowing once: the silicon wafer subjected to the phosphorus expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 45cm/min, the P surface is upward, and sand blasting is carried out at a pressure of 0.9Kg/cm 2;
Step four, boron expansion treatment: performing boron surface diffusion on the P surface of the silicon wafer;
Step five, secondary sand blowing: the silicon wafer subjected to boron expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 45cm/min, the P surface is upward, and sand blasting is carried out at a pressure of 0.9Kg/cm 2, so that the diffusion process is completed.
In the first step, a silicon wafer with resistivity of 48 Ω·cm and thickness t=250μm is selected.
In the first step, the silicon wafer cleaning liquid comprises the following components in parts by weight: 90 parts of deionized water, 7 parts of nano abrasive, 2 parts of amphoteric surfactant and 5 parts of organic amine; the nanometer abrasive is amino-terminated polyether coated nanometer alumina, the particle size of the nanometer alumina is 20-40nm, and the mass ratio of the nanometer alumina to the amino-terminated polyether is 5:1, one or more of the amphoteric surfactants alkyl amino propionate, alkyl dimethyl betaine, alkyl hydroxy sulfopropyl betaine, alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethyl ammonium hydroxide, tetraethyl ammonium hydroxide, tetrapropyl ammonium hydroxide, tetrabutyl ammonium hydroxide, trimethyl benzyl ammonium hydroxide, trimethyl hydroxyethyl ammonium hydroxide, dimethyl dihydroxyethyl ammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine and diethanolamine.
In the second step, pre-heating the phosphorus attached before the first diffusion treatment, horizontally placing the silicon wafer on a quartz boat with the N face upwards, then attaching low-concentration phosphorus paper on the N face of the silicon wafer, plugging the silicon wafer into a low-temperature furnace by a baffle plate, and pre-heating the silicon wafer to 290 ℃.
In the second step, low-concentration phosphor paper is adopted for primary diffusion, the primary diffusion temperature is 1200 ℃, the time is 8 hours, and the final diffusion depth is 80 mu m; and then adopting normal-concentration phosphor paper to carry out secondary diffusion, wherein the temperature of the secondary diffusion is 12350 ℃, the time is 3 hours, and the final diffusion depth is 50 mu m.
And in the second step, after the primary diffusion is finished, preheating the normal-concentration phosphor paper in the cooling process of the diffusion furnace, cooling the diffusion furnace to 270 ℃, heating the normal-concentration phosphor paper to 270 ℃, loading the normal-concentration phosphor paper, and plugging the normal-concentration phosphor paper into the diffusion furnace by using a baffle plate to perform secondary diffusion treatment.
In the fourth step, boron impurities are coated on the P surface of the silicon wafer firstly, the coated silicon wafer is placed on an electric heating plate for drying, then the boron surfaces of the silicon wafer are opposite, two silicon wafers are stacked, the silicon wafers are vertically placed on a quartz boat after being stacked, and are plugged by a baffle plate, and the silicon wafer is put into a boron expansion furnace for boron expansion, wherein the boron expansion treatment is carried out at the temperature of 1000 ℃ for 2.5 hours.
And in the third step and the fifth step, after the sand blowing is finished, cleaning the silicon wafer.
In embodiment 3, referring to fig. 1-2, a soft fast recovery FRD diode chip includes a silicon wafer, the silicon wafer adopts a double base diffusion sheet 2, the double base diffusion sheet 2 includes a P + region 223, the thickness of the P + region 223 is 90 μm, an N - region 222 is provided on one side of the P + region 223, the thickness of the N - region 222 is 60 μm, an N region 221 is provided on one side of the N - region 222 away from the P + region 223, the thickness of the N region 221 is 30 μm, an N + region 220 is provided on one side of the N region 221, and the thickness of the N + region 220 is 50 μm.
The thickness of the silicon wafer raw material is 250 mu m, the resistivity is 45-50Ω & cm, and the total thickness of the double-base diffusion sheet 2 is 230 mu m.
The N - region 222 of the double-base diffusion sheet 2 is a lightly doped substrate region of the original silicon wafer, the N region 221 is a more heavily doped region, and the doping concentration of the N region 221 is higher than that of the N - region 222 and is far lower than that of the N + region 220.
The softness factor of the double base diffusion sheet 2 is 0.65, the reverse breakdown voltage is 1300V, and the reverse recovery time is 250ns.
In this embodiment, the single-base diffusion process is used instead of the single-base diffusion process, and the single-base diffusion process mainly uses the single-base diffusion sheet 1, where the single-base diffusion sheet 1 is composed of the original N + region 110, the original N - region 111 and the original P + region 112, and since the impurity concentration of the single-base diffusion sheet 1 is lower, it is known from a softness factor formula that the softness factor S value is to be improved, only tb needs to be increased, when a reverse bias is applied, the S value is lower, the reverse recovery characteristic is harder, and when the reverse bias is applied, the newly added N region 221 is higher than the impurity concentration of the original N - region 111, and when the reverse bias is applied, the impurity concentration of the buffer layer is higher than the concentration of the substrate, the expansion of the depletion region after reaching the buffer layer is obviously slowed down in the reverse recovery process, and after the minority carrier storage time, a large number of carriers in the buffer layer are not compounded or pumped away, so that the compounding time is increased accordingly, and the softness factor of the diode is improved. The carrier is pumped out for a longer time, namely the tb value is increased, the softness factor S value is increased, and the carrier is recovered by a reverse recovery time formulaIt can be known that τ p is the lifetime of the large injection carrier, J F is the forward current density, J RM is the reverse peak current density, the reverse recovery time Trr is proportional to the large injection lifetime τ p and inversely proportional to the reverse peak current density J RM, when a double-base diffusion process is adopted and a reverse bias is applied, the reverse recovery time Trr is also greatly increased, in order to reduce the reverse recovery time to a reasonable range, improve the working frequency of the device, and increase the platinum expansion temperature from 880 ℃ to about 920 ℃ to control the reverse recovery time of the diode to below 250 ns;
by the formula (Where W is the base width, τH is the carrier lifetime, DH is the bipolar diffusion coefficient), vm is proportional to the base width W, and Vm is proportional to the silicon wafer resistivity ρ. Therefore, to reduce the forward Vm (i.e., vf), a silicon wafer with a narrower base width and a smaller resistivity needs to be selected; in contrast, if the reverse Vm (i.e., VB) is to be improved, a silicon wafer with a wider base width and a larger resistivity is required, and therefore, the requirements of the forward and reverse electrical parameters on the base width and the resistivity are contradictory to each other, so that the selection of the thickness and the resistivity of the silicon wafer is considered correspondingly, and the silicon wafer with the thickness of about 250 micrometers is adopted for diffusion, and compared with the traditional FRD chip, the silicon wafer can obtain higher reverse breakdown voltage under the condition that the forward voltage is not remarkably increased.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.
Claims (8)
1. The preparation method of the soft fast recovery FRD diode chip comprises a diffusion process and a GPP process, and is characterized in that the diffusion process comprises the following steps:
step one, diffusion pretreatment: firstly, mechanically polishing a silicon wafer raw material to obtain a polished substrate, and then cleaning the surface of the polished substrate through a silicon wafer cleaning liquid;
Step two, phosphorus expansion treatment: performing diffusion treatment on the N surface of the silicon wafer treated in the first step, performing primary diffusion by adopting low-concentration phosphor paper, and performing secondary diffusion by adopting normal-concentration phosphor paper;
Step three, sand blowing once: the silicon wafer after the phosphorus expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 40-50cm/min, the P surface is upward, and sand blasting is carried out at a pressure of 0.9-1.0Kg/cm 2;
Step four, boron expansion treatment: performing boron surface diffusion on the P surface of the silicon wafer;
Step five, secondary sand blowing: the silicon wafer subjected to boron expansion treatment enters a vacuum sand blowing chamber at a transmission speed of 40-50cm/min, is blown on both sides, and is subjected to sand blasting at a pressure of 0.9-1.0Kg/cm 2, so that a diffusion process is completed.
2. The method for manufacturing a soft fast recovery FRD diode chip according to claim 1, wherein in the first step, a silicon wafer having a resistivity of 45-50Ω·cm and a thickness t=250±5 μm is selected.
3. The method for manufacturing the soft and fast recovery FRD diode chip according to claim 1, wherein in the first step, the silicon wafer cleaning solution comprises the following components in parts by weight: 80-100 parts of deionized water, 5-8 parts of nano abrasive, 1-3 parts of amphoteric surfactant and 4-6 parts of organic amine; the nanometer abrasive is amino-terminated polyether coated nanometer alumina, the particle size of the nanometer alumina is 20-40nm, and the mass ratio of the nanometer alumina to the amino-terminated polyether is (3-8): 1, one or more of the amphoteric surfactants alkyl amino propionate, alkyl dimethyl betaine, alkyl hydroxy sulfopropyl betaine, alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethyl ammonium hydroxide, tetraethyl ammonium hydroxide, tetrapropyl ammonium hydroxide, tetrabutyl ammonium hydroxide, trimethyl benzyl ammonium hydroxide, trimethyl hydroxyethyl ammonium hydroxide, dimethyl dihydroxyethyl ammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine and diethanolamine.
4. The method for manufacturing the soft fast recovery FRD diode chip according to claim 1, wherein in the second step, pre-heating treatment of attaching phosphorus is carried out before primary diffusion treatment, the silicon wafer is horizontally placed on a quartz boat with the N face upwards, then low-concentration phosphorus paper is attached to the N face of the silicon wafer, the silicon wafer is plugged into a low-temperature furnace by a baffle plate, and the silicon wafer is preheated to 280-300 ℃.
5. The method for manufacturing the soft and fast recovery FRD diode chip according to claim 4, wherein in the second step, low-concentration phosphor paper is adopted for primary diffusion, the primary diffusion temperature is 1180-1220 ℃, the time is 6-10h, and the final diffusion depth is 75-85 μm; and then adopting normal-concentration phosphorus paper to carry out secondary diffusion, wherein the temperature of the secondary diffusion is 1230-1280 ℃, the time is 2-4h, and the final diffusion depth is 45-55 mu m.
6. The method for manufacturing the soft fast recovery FRD diode chip according to claim 5, wherein in the second step, after the primary diffusion is completed, the diffusion furnace is preheated in the cooling process of the diffusion furnace, the temperature of the diffusion furnace is reduced to 250-300 ℃, the temperature of the normal concentration phosphorus paper is increased to 250-300 ℃, the normal concentration phosphorus paper is loaded, and the diffusion furnace is plugged by a baffle plate to perform the secondary diffusion treatment.
7. The method for manufacturing the soft fast recovery FRD diode chip according to claim 1, wherein in the fourth step, boron impurities are coated on the P surface of a silicon wafer, the coated silicon wafer is placed on an electric heating plate for drying, then the boron surfaces of the silicon wafer are opposite, the silicon wafer is stacked, the silicon wafer is vertically placed on a quartz boat after being stacked, and is plugged by a baffle plate, and the boron expansion treatment is performed in a boron expansion furnace, wherein the boron expansion treatment is performed at 950-1050 ℃ for 1-3 hours.
8. The method for manufacturing the soft and fast recovery FRD diode chip according to claim 1, wherein in the third step and the fifth step, after the sand blowing is finished, the silicon wafer is cleaned.
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