CN117936595A - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure and a method of forming the same, wherein the method of forming comprises: providing a substrate; forming a first dielectric layer on a substrate, wherein a capacitor groove is formed in the first dielectric layer; forming a capacitor structure in the capacitor groove, wherein the capacitor structure comprises a first electrode layer positioned on the side wall and the bottom surface of the capacitor groove, an insulating layer positioned on the first electrode layer, a second electrode layer positioned on the insulating layer, the capacitor groove is filled with the second electrode layer, and the top surface of the second electrode layer is flush with the top surface of the first dielectric layer; a second dielectric layer is formed over the first dielectric layer and the capacitor structure. Because the top surface of the capacitor structure is flush with the top surface of the first dielectric layer, the second dielectric layer can be formed on a flat interface provided by the first dielectric layer and the capacitor structure, so that the flatness of the top surface of the second dielectric layer is improved, the alignment precision of the photoetching process in the subsequent process is further improved, and the reliability of the finally formed semiconductor structure is improved.

Description

Semiconductor structure and method of forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof.

Background technique

Capacitors are passive components commonly used in VLSI, mainly including polysilicon-insulator-polysilicon (PIP) capacitors, metal-insulator-silicon (MIS) capacitors and metal-insulator-metal (MIM) capacitors.

With the rapid development of wireless communication technology, people strongly hope to implant high-performance decoupling and bypass capacitors suitable for system-on-chip (SoC) into the copper interconnect terminal process of integrated circuits to obtain powerful RF systems. This further requires that the implanted capacitors should have high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability; traditional PIP structures, MIS structures, and MOS structures can no longer meet performance requirements.

Since MIM capacitors cause little interference to transistors and can provide better linearity and symmetry, the use of MIM capacitors will be the development trend of RF and analog/mixed signal integrated circuits.

However, there are still many problems in the formation process of MIM capacitors.

Summary of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the reliability of the finally formed semiconductor structure.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer has a capacitor groove; forming a capacitor structure in the capacitor groove, wherein the capacitor structure includes a first electrode layer located on the sidewall and bottom surface of the capacitor groove, an insulating layer located on the first electrode layer, and a second electrode layer located on the insulating layer, wherein the second electrode layer fills the capacitor groove, and the top surface of the second electrode layer is flush with the top surface of the first dielectric layer; and forming a second dielectric layer on the first dielectric layer and the capacitor structure.

Optionally, the method for forming a capacitor structure in the capacitor groove includes: forming a first electrode material layer on the side wall and bottom surface of the capacitor groove, and the top surface of the first dielectric layer; forming an insulating material layer on the first electrode material layer; forming a second electrode material layer on the insulating material layer; performing a first grinding process on the second electrode material layer, the insulating material layer, and the first electrode material layer until the top surface of the first dielectric layer is exposed, so that the first electrode material layer forms an initial first electrode layer, the insulating material layer forms an initial insulating layer, and the second electrode material layer forms an initial second electrode layer; performing a second grinding process on the initial first electrode layer, the initial insulating layer, the initial second electrode layer, and the first dielectric layer until the top surface of the initial second electrode layer located in the capacitor groove is exposed, so that the initial first electrode layer forms the first electrode layer, the initial insulating layer forms the insulating layer, and the initial second electrode layer forms the second electrode layer.

Optionally, the first polishing process includes: a first chemical mechanical polishing process.

Optionally, the process parameters of the first chemical mechanical polishing process include: the polishing solution includes: silicon oxide solution and hydrogen peroxide; the polishing head speed is 100 rpm-110 rpm; and the polishing time is 50 seconds to 100 seconds.

Optionally, the second polishing process includes: a second chemical mechanical polishing process.

Optionally, the process parameters of the second chemical mechanical polishing process include: the polishing solution includes: silicon oxide solution and hydrogen peroxide; the polishing head speed is 100 rpm-110 rpm; and the polishing time is 50 seconds to 100 seconds.

Optionally, the material of the first electrode layer includes: metal; the metal includes: copper, aluminum or tantalum alloy.

Optionally, the material of the second electrode layer includes: metal; the metal includes: copper, aluminum or tantalum alloy.

Optionally, the material of the insulating layer includes: high-K dielectric material; the high-K dielectric material includes: copper, aluminum or tantalum alloy.

Optionally, after forming the second dielectric layer, the method further includes: forming a plurality of first conductive plugs and a plurality of second conductive plugs in the second dielectric layer, wherein the plurality of first conductive plugs are respectively connected to the first electrode layer, and the plurality of second conductive plugs are respectively connected to the second electrode layer.

Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: providing a substrate; a first dielectric layer located on the substrate, the first dielectric layer having a capacitor groove; a capacitor structure located in the capacitor groove, the capacitor structure including a first electrode layer located on the side wall and bottom surface of the capacitor groove, an insulating layer located on the first electrode layer, and a second electrode layer located on the insulating layer, the second electrode layer fills the capacitor groove, and the top surface of the second electrode layer is flush with the top surface of the first dielectric layer; a second dielectric layer located on the first dielectric layer and the capacitor structure.

Optionally, the material of the first electrode layer includes: metal; the metal includes: copper, aluminum or tantalum alloy.

Optionally, the material of the second electrode layer includes: metal; the metal includes: copper, aluminum or tantalum alloy.

Optionally, the material of the insulating layer includes: high-K dielectric material; the high-K dielectric material includes: silicon oxide or silicon nitride.

Optionally, the method further includes: forming a plurality of first conductive plugs and a plurality of second conductive plugs in the second dielectric layer, wherein the plurality of first conductive plugs are respectively connected to the first electrode layer, and the plurality of second conductive plugs are respectively connected to the second electrode layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a semiconductor structure of the technical solution of the present invention, since the capacitor structure is formed in the capacitor groove of the first dielectric layer, and the top surface of the capacitor structure is flush with the top surface of the first dielectric layer, the second dielectric layer is formed on the flat interface provided by the first dielectric layer and the capacitor structure, so as to improve the flatness of the top surface of the second dielectric layer, thereby improving the flatness of the film layer subsequently formed on the second dielectric layer, so as to improve the alignment accuracy of the photolithography process in the subsequent process, so as to improve the reliability of the finally formed semiconductor structure.

In the semiconductor structure of the technical solution of the present invention, since the capacitor structure is located in the capacitor groove of the first dielectric layer and the top surface of the capacitor structure is flush with the top surface of the first dielectric layer, the second dielectric layer is formed on the flat interface provided by the first dielectric layer and the capacitor structure to improve the flatness of the top surface of the second dielectric layer, thereby improving the flatness of the film layer subsequently formed on the second dielectric layer, so as to improve the alignment accuracy of the photolithography process in the subsequent process, thereby improving the reliability of the finally formed semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic structural diagram of various steps of a method for forming a MIM capacitor;

2 to 10 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed ways

As described in the background art, there are still many problems in the formation process of MIM capacitors, which will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of each step of a method for forming a MIM capacitor.

Please refer to Figure 1, providing a substrate 100; forming a first electrode layer 101 on the substrate 100; forming an insulating layer 102 on the first electrode layer 101, the insulating layer 102 exposing a portion of the top surface of the first electrode layer 101; forming a second electrode layer 103 on the insulating layer 102; forming a dielectric layer 104 on the substrate 100, the dielectric layer 104 covering the first electrode layer 101, the insulating layer 102 and the second electrode layer 103; forming a plurality of first conductive plugs 105 and a plurality of second conductive plugs 106 in the dielectric layer 104, the plurality of first conductive plugs 105 are respectively connected to the first electrode layer 101, and the plurality of second conductive plugs 106 are respectively connected to the second electrode layer 103.

In this embodiment, a MIM capacitor is formed by the first electrode layer 101, the insulating layer 102 and the second electrode layer 103, and the first electrode layer 101 and the second electrode layer 103 of the MIM capacitor are respectively led out by a plurality of first conductive plugs 105 and a plurality of second conductive plugs 106.

However, since the MIM capacitor is formed on the substrate 100, when the dielectric layer 104 is formed on the substrate 100, a bulge is formed on the top surface of the dielectric layer 104 corresponding to the position of the MIM capacitor, thereby reducing the flatness of the top surface of the dielectric layer 104. When the top surface of the dielectric layer 104 is uneven, the film layer subsequently deposited on the dielectric layer 104 will also be uneven, thereby causing problems such as reduced alignment accuracy of the subsequent photolithography process, resulting in reduced reliability of the semiconductor structure finally formed.

On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the capacitor structure is formed in a capacitor groove of the first dielectric layer, and the top surface of the capacitor structure is flush with the top surface of the first dielectric layer, so that the second dielectric layer is formed on a flat interface provided by the first dielectric layer and the capacitor structure, so as to improve the flatness of the top surface of the second dielectric layer, thereby improving the flatness of a film layer subsequently formed on the second dielectric layer, so as to improve the alignment accuracy of a photolithography process in a subsequent process, and thereby improve the reliability of the semiconductor structure finally formed.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

2 to 10 are schematic structural diagrams of various steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Please refer to FIG. 2 , a substrate 200 is provided.

In this embodiment, the substrate 200 includes: a base (not shown), a device layer (not shown) located on the base, the device layer having a plurality of device structures, and an electrical interconnection layer (not shown) located on the device layer, the electrical interconnection layer having a plurality of electrical interconnection lines, and the electrical interconnection lines are connected to the device structures.

In this embodiment, the material of the substrate is silicon; in other embodiments, the material of the substrate may also be silicon germanium.

Referring to FIG. 3 , a first dielectric layer 201 is formed on the substrate 200 , and a capacitor groove 202 is formed in the first dielectric layer 201 .

In this embodiment, the method for forming the first dielectric layer 201 includes: forming an initial first dielectric layer (not shown) on the substrate 200; forming a patterned layer (not shown) on the initial first dielectric layer, wherein the patterned layer exposes a portion of the top surface of the initial first dielectric layer; etching the initial first dielectric layer using the patterned layer as a mask to form the first dielectric layer 201, wherein the first dielectric layer 201 has the capacitor groove 202.

In this embodiment, the material of the first dielectric layer 201 is silicon oxide; in other embodiments, the material of the first dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

In this embodiment, after forming the first dielectric layer 201, it further includes: forming a capacitor structure in the capacitor groove 202, the capacitor structure including a first electrode layer located on the sidewall and bottom surface of the capacitor groove 202, an insulating layer located on the first electrode layer, and a second electrode layer located on the insulating layer, the second electrode layer fills the capacitor groove, and the top surface of the second electrode layer is flush with the top surface of the first dielectric layer 201. Please refer to Figures 4 to 8 for the specific formation process of the capacitor structure.

Referring to FIG. 4 , a first electrode material layer 203 is formed on the sidewall and bottom surface of the capacitor groove 202 and the top surface of the first dielectric layer 201 .

In this embodiment, the first electrode material layer 203 is formed by an atomic layer deposition process.

In other embodiments, the formation process of the first electrode material layer may also adopt a chemical vapor deposition process or a physical vapor deposition process.

The material of the first electrode material layer 203 includes metal; the metal includes copper, aluminum or tantalum alloy.

In this embodiment, the material of the first electrode material layer 203 is copper.

Referring to FIG. 5 , an insulating material layer 204 is formed on the first electrode material layer 203 .

In this embodiment, the insulating material layer 204 is formed by an atomic layer deposition process.

In other embodiments, the insulating material layer may be formed by a chemical vapor deposition process or a physical vapor deposition process.

The material of the insulating material layer 204 includes: a high-K dielectric material; the high-K dielectric material includes: silicon oxide or silicon nitride.

In this embodiment, the insulating material layer 204 is made of silicon oxide.

Referring to FIG. 6 , a second electrode material layer 205 is formed on the insulating material layer 204 .

In this embodiment, the second electrode material layer 205 is formed by an atomic layer deposition process.

In other embodiments, the second electrode material layer may be formed by a chemical vapor deposition process or a physical vapor deposition process.

The material of the second electrode material layer 205 includes metal; the metal includes copper, aluminum or tantalum alloy.

In this embodiment, the second electrode material layer 205 is made of copper.

Please refer to Figure 7, the second electrode material layer 205, the insulating material layer 204, and the first electrode material layer 203 are subjected to a first grinding process until the top surface of the first dielectric layer 201 is exposed, so that the first electrode material layer 203 forms an initial first electrode layer 206, the insulating material layer 204 forms an initial insulating layer 207, and the second electrode material layer 205 forms an initial second electrode layer 208.

In this embodiment, the first polishing process adopts a first chemical mechanical polishing process.

In this embodiment, the process parameters of the first chemical mechanical polishing process include: the polishing solution includes: silicon oxide solution and hydrogen peroxide; the polishing head speed is 100 rpm-110 rpm; and the polishing time is 50 seconds to 100 seconds.

Please refer to Figure 8, the initial first electrode layer 206, the initial insulating layer 207, the initial second electrode layer 208 and the first dielectric layer 201 are subjected to a second grinding process until the top surface of the initial second electrode layer 208 located in the capacitor groove 202 is exposed, so that the initial first electrode layer 206 forms the first electrode layer 209, the initial insulating layer 207 forms the insulating layer 210, and the initial second electrode layer 208 forms the second electrode layer 211.

In this embodiment, since the capacitor structure is formed in the capacitor groove 202 of the first dielectric layer 201, and the top surface of the capacitor structure is flush with the top surface of the first dielectric layer 201, the subsequent second dielectric layer will be formed on the flat interface provided by the first dielectric layer 201 and the capacitor structure to improve the flatness of the top surface of the second dielectric layer, thereby improving the flatness of the film layer subsequently formed on the second dielectric layer, so as to improve the alignment accuracy of the photolithography process in the subsequent process, so as to improve the reliability of the finally formed semiconductor structure.

In this embodiment, the second polishing process adopts a second chemical mechanical polishing process.

In this embodiment, the process parameters of the second chemical mechanical polishing process include: the polishing solution includes: silicon oxide solution and hydrogen peroxide; the polishing head speed is 100 rpm-110 rpm; and the polishing time is 50 seconds to 100 seconds.

In this embodiment, the first electrode layer 209 is formed by the first electrode material layer 203, so the material of the first electrode layer 209 is the same as the material of the first electrode material layer 203. Correspondingly, the material of the insulating layer 210 is the same as the material of the insulating material layer 204, and the material of the second electrode layer 211 is the same as the material of the second electrode material layer 205.

Referring to FIG. 9 , a second dielectric layer 212 is formed on the first dielectric layer 201 and the capacitor structure.

In this embodiment, the material of the second dielectric layer 212 is silicon oxide; in other embodiments, the material of the first dielectric layer can also be low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric material (referring to dielectric material with a relative dielectric constant lower than 2.5).

Please refer to Figure 10. After the second dielectric layer 212 is formed, a plurality of first conductive plugs 213 and a plurality of second conductive plugs 214 are formed in the second dielectric layer 212. The plurality of first conductive plugs 213 are respectively connected to the first electrode layer 209, and the plurality of second conductive plugs 214 are respectively connected to the second electrode layer 211.

In this embodiment, the method for forming the plurality of first conductive plugs 213 and the plurality of second conductive plugs 214 includes: forming a plurality of first conductive openings (not labeled) and a plurality of second conductive openings (not labeled) in the second dielectric layer 212, wherein the first conductive openings expose the surface of the first electrode layer 209, and the second conductive openings expose the surface of the second electrode layer 211; forming a conductive material layer (not shown) in the first conductive openings, in the second conductive openings, and on the second dielectric layer 212; and flattening the conductive material layer until the surface of the second dielectric layer 212 is exposed, thereby forming the plurality of first conductive plugs 213 and the plurality of second conductive plugs 214.

Correspondingly, a semiconductor structure is also provided in an embodiment of the present invention, please continue to refer to Figure 10, including: providing a substrate 200; a first dielectric layer 201 located on the substrate 200, and the first dielectric layer 201 has a capacitor groove 202; a capacitor structure located in the capacitor groove 202, the capacitor structure including a first electrode layer 209 located on the side wall and bottom surface of the capacitor groove 202, an insulating layer 210 located on the first electrode layer 209, and a second electrode layer 211 located on the insulating layer 210, the second electrode layer 211 fills the capacitor groove 202, and the top surface of the second electrode layer 211 is flush with the top surface of the first dielectric layer 201; a second dielectric layer 212 located on the first dielectric layer 201 and the capacitor structure.

In this embodiment, since the capacitor structure is located in the capacitor groove 202 of the first dielectric layer 201, and the top surface of the capacitor structure is flush with the top surface of the first dielectric layer 201, the second dielectric layer 212 is formed on the flat interface provided by the first dielectric layer 201 and the capacitor structure to improve the flatness of the top surface of the second dielectric layer 212, thereby improving the flatness of the film layer subsequently formed on the second dielectric layer 212, so as to improve the alignment accuracy of the photolithography process in the subsequent process, so that the reliability of the finally formed semiconductor structure is improved.

The material of the first electrode layer 209 includes metal; the metal includes copper, aluminum or tantalum alloy.

In this embodiment, the material of the first electrode layer 209 is copper.

The material of the insulating layer 210 includes: a high-K dielectric material; the high-K dielectric material includes: silicon oxide or silicon nitride.

In this embodiment, the insulating layer 210 is made of silicon oxide.

The material of the second electrode layer 211 includes metal; the metal includes copper, aluminum or tantalum alloy.

In this embodiment, the second electrode layer 211 is made of copper.

In this embodiment, it also includes: forming a plurality of first conductive plugs 213 and a plurality of second conductive plugs 214 in the second dielectric layer 212 , wherein the plurality of first conductive plugs 213 are respectively connected to the first electrode layer 209 , and the plurality of second conductive plugs 214 are respectively connected to the second electrode layer 211 .

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate;

forming a first dielectric layer on the substrate, wherein a capacitor groove is formed in the first dielectric layer;

Forming a capacitor structure in the capacitor groove, wherein the capacitor structure comprises a first electrode layer positioned on the side wall and the bottom surface of the capacitor groove, an insulating layer positioned on the first electrode layer, a second electrode layer positioned on the insulating layer, the second electrode layer fills the capacitor groove, and the top surface of the second electrode layer is flush with the top surface of the first dielectric layer;

And forming a second dielectric layer on the first dielectric layer and the capacitor structure.

2. The method of forming a semiconductor structure of claim 1, wherein forming a capacitor structure within the capacitor recess comprises: forming a first electrode material layer on the side wall and the bottom surface of the capacitor groove and the top surface of the first dielectric layer; forming an insulating material layer on the first electrode material layer; forming a second electrode material layer on the insulating material layer; performing first grinding treatment on the second electrode material layer, the insulating material layer and the first electrode material layer until the top surface of the first dielectric layer is exposed, so that the first electrode material layer forms an initial first electrode layer, the insulating material layer forms an initial insulating layer, and the second electrode material layer forms an initial second electrode layer; and performing second grinding treatment on the initial first electrode layer, the initial insulating layer, the initial second electrode layer and the first dielectric layer until the top surface of the initial second electrode layer positioned in the capacitor groove is exposed, so that the initial first electrode layer forms the first electrode layer, the initial insulating layer forms the insulating layer, and the initial second electrode layer forms the second electrode layer.

3. The method of forming a semiconductor structure of claim 2, wherein the first polishing process comprises: a first chemical mechanical polishing process.

4. The method of claim 3, wherein the process parameters of the first cmp process comprise: the grinding solution comprises: silicon oxide solution and hydrogen peroxide; the rotation speed of the grinding head is 100-110 rpm; the grinding time is 50-100 seconds.

5. The method of forming a semiconductor structure of claim 2, wherein the second polishing process comprises: and a second chemical mechanical polishing process.

6. The method of claim 5, wherein the process parameters of the second cmp process comprise: the grinding solution comprises: silicon oxide solution and hydrogen peroxide; the rotation speed of the grinding head is 100-110 rpm; the grinding time is 50-100 seconds.

7. The method of forming a semiconductor structure of claim 1, wherein the material of the first electrode layer comprises: a metal; the metal comprises: copper, aluminum or tantalum alloys.

8. The method of forming a semiconductor structure of claim 1, wherein the material of the second electrode layer comprises: a metal; the metal comprises: copper, aluminum or tantalum alloys.

9. The method of forming a semiconductor structure of claim 1, wherein the material of the insulating layer comprises: a high-K dielectric material; the high-K dielectric material includes: silicon oxide or silicon nitride.

10. The method of forming a semiconductor structure of claim 1, further comprising, after forming the second dielectric layer: and forming a plurality of first conductive plugs and a plurality of second conductive plugs in the second dielectric layer, wherein the first conductive plugs are respectively connected with the first electrode layer, and the second conductive plugs are respectively connected with the second electrode layer.

11. A semiconductor structure, comprising:

Providing a substrate;

The first dielectric layer is positioned on the substrate and is internally provided with a capacitor groove;

A capacitor structure located in the capacitor groove, the capacitor structure comprising a first electrode layer located on the side wall and the bottom surface of the capacitor groove, an insulating layer located on the first electrode layer, a second electrode layer located on the insulating layer, the second electrode layer filling the capacitor groove, and the top surface of the second electrode layer being flush with the top surface of the first dielectric layer;

and the second dielectric layer is positioned on the first dielectric layer and the capacitor structure.

12. The semiconductor structure of claim 11, wherein the material of the first electrode layer comprises: a metal; the metal comprises: copper, aluminum or tantalum alloys.

13. The semiconductor structure of claim 11, wherein the material of the second electrode layer comprises: a metal; the metal comprises: copper, aluminum or tantalum alloys.

14. The semiconductor structure of claim 11, wherein the material of the insulating layer comprises: a high-K dielectric material; the high-K dielectric material includes: silicon oxide or silicon nitride.

15. The semiconductor structure of claim 11, further comprising: and forming a plurality of first conductive plugs and a plurality of second conductive plugs in the second dielectric layer, wherein the first conductive plugs are respectively connected with the first electrode layer, and the second conductive plugs are respectively connected with the second electrode layer.