CN1179033A - Gain control circuit and method - Google Patents
Gain control circuit and method Download PDFInfo
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- CN1179033A CN1179033A CN 97120402 CN97120402A CN1179033A CN 1179033 A CN1179033 A CN 1179033A CN 97120402 CN97120402 CN 97120402 CN 97120402 A CN97120402 A CN 97120402A CN 1179033 A CN1179033 A CN 1179033A
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Abstract
A circuit and method for controlling current gain in variable gain and automatic gain control amplifiers or attenuators in high frequency communication systems. A transistor through which the current is provided always operates at the same DC bias, independent of gain control variations. The input signal is provided to a base of the transistor whose collector provides an output current whose gain is to be controlled. An AGC current for adjusting the output current gain and a DC bias current are provided to the base of the transistor through a multi-transistor circuit so that the DC bias is independent of variation of the output current gain.
Description
The present invention relates to circuits for electrically controlling signal levels, and more particularly to a gain control circuit for a variable gain and automatic gain control amplifier or attenuator in a high frequency communication system.
Many circuits in a communication system require means for controlling signal levels. Variable gain and gain control circuits amplifiers and attenuators are used for this purpose.
A well-known device for controlling signal levels in a communication system is a differential pair attenuator. The output from the collector of any one of the transistors in the attenuator is a scaled replica of the emitter current output of the differential pair, where the amount of attenuation is a function of the applied differential voltage. In such an arrangement, the input signal and the DC bias are both proportional. However, with high attenuation, the reduced DC bias affects the operation of the device, resulting in reduced bandwidth and reduced current gain.
Known arrangements avoid this problem by cascading a number of attenuator stages, each stage attenuating less than a single attenuator. Cascading introduces other problems such as the need to string unpaired cascaded stages operating at low supply voltages, or to connect the stages with current mirrors or level shifters, thus requiring increased system supply current and possibly reduced system bandwidth.
The present invention avoids many of the problems of transistors by supplying an input signal via the transistor with a DC bias that is independent of gain control variations to operate the transistor. The input signal is supplied to the base of a transistor whose collector supplies the output current whose gain is controlled. An AGC current for adjusting the gain of an output current and a DC bias current are supplied to the base of a transistor by a multi-transistor circuit that ensures that the DC bias is substantially independent of variations in the gain of the output current.
It is an object of the present invention to provide a gain control circuit and method in which the transistor through which the input signal is provided operates at a DC bias that is substantially independent of gain control variations.
It is another object to provide a gain control circuit and method wherein a unit for the circuit comprises: a 1 st transistor having a collector connected to serve as the cell output, a grounded emitter, and a base connected to serve as the cell input; and an operating circuit having an AGC current source for adjusting an output gain and a DC bias current source for providing a DC bias to the 1 st transistor, and wherein the AGC current source and the DC bias current source are both connected to the base of the 1 st transistor through a multi-transistor circuit such that the DC bias is independent of gain variations.
It is a further object to provide a gain control circuit and method wherein the 1 st transistor has a 1 st terminal connected to the circuit output and a base connected to the circuit input; a 1 st pair of series connected transistors having a 1 st node therebetween, the node being connected to the base of the 1 st transistor; a 2 nd pair of series connected transistors are connected to a bias current source and have an AGC current source connected at a 2 nd junction therebetween, where the base of one transistor of the 2 nd pair is connected to the base of the 1 st transistor of the 1 st pair, and wherein a 6 th transistor is connected to the AGC current source and has its base connected to the base of the 2 nd transistor of the 1 st pair, such that the DC bias supplied to the base of the 1 st transistor is independent of gain variations and wherein a plurality of cells are cascaded, each cell having a transistor providing an input signal therethrough, the crystal operating at a DC bias substantially independent of gain control variations.
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:
fig. 1 is a circuit schematic of an embodiment of the basic cell of the present invention.
Fig. 2 is a circuit schematic diagram of a cascaded unit of an embodiment of the present invention.
Fig. 3 is a circuit schematic diagram of a cascade cell according to another embodiment of the invention.
Fig. 4 is a circuit schematic of embodiment 1 of the invention for a differential device.
Fig. 5 is a circuit schematic of embodiment 2 of the invention for a differencing device.
FIG. 1 shows the basic for a gain control circuitAn embodiment of cell 10, the basic cell 10 includes a 1 st transistor Q1 having an output I connected to serve as the cellOUTAnd a grounded emitter and an input I connected to be used as the cellINThe base of (1). Only a small amount of current applied to the base of transistor Q1 is sunk at the base and mostly sunk by the emitter of transistor Q2 at node N1. Thus, the transistor Q2 converts the input current into a voltage, which in turn converts the voltage into an output current.
The 1 st pair of series-connected transistors Q2 and Q5 may be connected at a potential VDDAnd ground, and between transistors Q2 and Q5, there is a node N1, the node N1 being connected to the base of transistor Q1. AGC current source IAGCCan supply a current for regulating the slave IINTo IOUTGain (two current sources I are shown simultaneously)AGCSuch a current source may already be sufficient), and a bias current source IBIASA DC bias current may be provided.
The 2 nd pair of series connected transistors Q3 and Q4 may be connected at IBIASAnd ground, and each transistor may have its base connected to its collector. Can be handled IAGCIs connected to node N2 between the 2 nd pair of transistors Q3 and Q4, and may connect the base of transistor Q4 to the base of transistor Q2. The 6 th transistor Q6 may be connected at IAGCAnd ground, and has its base connected to its collector and to the base of transistor Q5. In operation, the DC bias supplied to the base of transistor Q1 is independent of variations in current gain.
The transistor may be, for example, a bipolar junction transistor, which is either a PNP or NPN transistor, or perhaps a MOS transistor. The bias current and AGC current may be the same or different and may vary from cell to cell in the case of a cascade of cells.
This can be readily understood by the mathematical description and methodology of operation of the circuit described below.
Assuming that all transistors are the same size and matched,
VBEQ1+VBEQ2＝VBEQ3+VBEQ4 (1)
IC1IC2＝IC3IC4 (2)
IOUT(IAGC+IIN)＝IBIAS(IACC+IBIAS) (3)
as estimated, IIN＝IBIAS+ISIGIn which ISIGIs the input signal level. Thus:
IOUT＝(IBIAS+IAGC)IBIAS/(IAGC+IBIAS+ISIG) (4)
IOUT＝IBIAS/(1+ISIG/(IBIAS+IAGC))
＝IBIAS(1+x)＝IBIAS(1-x+x2-x3) (5)
wherein,
x＝ISIG/(IBIAS+IAGC)
IOUT＝IBIAS/[y+(1-y)+x] (6)
wherein,
y＝IAGC/(IBIAS+IAGC) And
IIN＝[(1-y)+x](IBIAS+IAGC) (7) in this way, the first step of the method,
IOUT＝IBIAS[1-(ai)+(ai)2-(ai)3] (8)
wherein a ≡ 1/(I)BIAS+IAGC)；i≡ISIG
Output current IOUTWith the same DC offset and an AC part that has been phase shifted by 180 and scaled down by the following factor:
IBIAS/(IBIAS+IAGC) The AC part of (1). Because of IAGCMay be positive or negative, so the cell may gain or attenuate.
The basic cell 10 is intended to operate at low supply voltages, e.g. two transistors VBE(about 1.6V) and the total supply current can be compared to the cascaded differential pair. In addition, because transistor Q1 through which the signal is passed always operates at the same attenuation coefficient independent DC bias, the bandwidth is also substantially independent of current gain, and cell 10 maintains a wide and constant bandwidth throughout the attenuation range. The bias current may also be applied to different gains. For example, let I in FIG. 1 beBIASThe value is reduced, then I does not need to be changedAGCThe attenuation can be increased.
Fig. 2 shows a plurality of cells 10, which as is conventional in the art, do not require level shifting and are cascaded without DC blocking capacitors or other matching networks between the cells. The output of one cell 10 may be supplied as an input to the next cell 10'. The cascode cell 10' may use fully isolated elements to change the signal level as shown in fig. 2. If the output of cell 10 becomes the input to the 2 nd identical cell 10, IOUTWith the same DC bias, but the AC part is scaled down by a factor:
[IBIAS/(IBIAS+IAGC)]2
if the output of the 2 nd unit 10 is the input of the 3 rd unit 10, then IOUTWith the same DC offset, but with the AC part having a 180 phase shift and scaled down by a factor ofThe coefficient is:
[IBIAS/(IBIAS+IAGC)]3
for two identical cells 10, an attenuation range from 0 to-45 db can be obtained.
The operation of the gain control circuit is desirably linear and as a result it has been found that the best linearity can be achieved with an even number of cascaded cells. For linear operation, the signal current ISIGAnd IBIASAnd IAGCIs desirably smaller than x (from equation 5), which is the worst case when there is no AGC (maximum gain). However, alternating units help to cancel distortion, and with two cascaded units, the 2 nd unit can cancel the distortion produced by the 1 st unit when AGC is zero and y is 0 (from equation 6). The worst case overall is therefore at some intermediate level of gain. For three units, the distortion is roughly the same as for a single unit, except when IAGCIs equal to IBIASThe improvement is slightly improved when y is 0.5. Therefore, the linearity is best with an even number of stages.
FIG. 3 illustrates a cell 10 "that shares a bias portion (I) with another cell 10BIASQ4, Q3, and Q6) supplied by the power supply systemBIASAnd IAGCThe same, and the transistor size the same.
The base unit 10 is also suitable for application to a differential unit 20, as shown in fig. 4. To provide a secondary input and serve as the output of cell 20, three transistors Q7-9 are added to transistors Q, Q2 and Q3 of redrawn cell 10'.
The circuit of fig. 5 illustrates another embodiment in which the two emitters of transistors Q1 and Q7 are connected together and to ground via resistor R1. A 2 nd resistor R2 having twice the resistance of R1 is connected between the emitter of Q4 and the collector or base of Q3.
The common connection of the emitters forms a true ground and the current flowing from the output signal through R1 is virtually absent at all. This helps stabilize the operating point of transistors Q1 and Q7 with respect to the mismatch between transistors Q1 and Q7, and helps balance signal levels. The disadvantage is that the distortion is onset at a smaller value and therefore the distortion increases slightly as the a.c. portion of the signal increases.
The present invention finds application in a variety of devices including AGC devices (i.e., electronically variable gain devices), gain controlled amplifiers and attenuators, and other similar devices. The invention is particularly suitable for application in high frequency communication systems.
The circuit and method of the present invention are applicable to current gain and automatic gain control amplifiers or attenuators for controlling variable gain in high frequency communication systems. The transistors supplying current through them always operate at the same DC bias regardless of gain control variations. The output signal is supplied to the base of the transistor, while its collector provides an output current whose gain is controlled. An AGC current and a DC bias current for adjusting the gain of an output current are supplied to the base of a multi-transistor circuit.
Claims (10)
1. A gain control circuit having a cell connected between a 1 st potential and ground, the cell comprising: a 1 st transistor having a 1 st terminal connected to the 1 st terminal serving as the cell output, a 2 nd terminal connected to ground, and a base connected to the cell input; a 1 st pair of series connected transistors connected between a 1 st potential and ground, and a 1 st junction between said 1 st pair connected to said 1 st base of said 1 st transistor; an AGC current source for adjusting the gain of the input current of the unit; a bias current source for supplying a DC bias current; a 2 nd pair of series connected transistors connected between said bias current source and ground, each transistor of said 2 nd pair having its base connected to its 1 st terminal, said AGC current source being connected to a 2 nd junction between said 2 nd pair of transistors, and the base of one of said 2 nd pair of transistors being connected to the base of the 1 st transistor of said 1 st pair of transistors; a 6 th transistor connected between said AGC current source and ground and having its base connected to the base of the 2 nd transistor of said 1 st pair of transistors and to the 1 st terminal of said 6 th transistor, such that the DC bias supplied to said base of said 1 st transistor is independent of input current gain variations at the input used as the input to the cell.
2. A circuit according to claim 1, wherein there is a cascade of a plurality of said cells, wherein the output of the 1 st of these cells becomes the input of the 2 nd of these cells, preferably an even number of said cells.
3. A circuit according to claim 1 or 2, characterized in that the unit comprises: a 7 th transistor having a 1 st terminal connected to the 2 nd output of the cell, a 2 nd terminal connected to ground, and a base connected to the 2 nd input of the cell; a 3 rd pair of series connected transistors connected between a 1 st potential and ground, a 3 rd junction between said 3 rd pair being connected to said base of said 7 th transistor; and the base of the 1 st tube of the 3 rd pair is connected to the base of the 1 st tube of the 1 st pair, and the base of the 2 nd tube of the 3 rd pair is connected to the base of the 2 nd tube of the 1 st pair.
4. A circuit according to any one of claims 1 to 3, wherein all of said transistors are substantially equally sized NPN bipolar transistors, or wherein all of said transistors are substantially equally sized PNP bipolar transistors, or wherein all of said transistors are substantially equally sized MOS transistors.
5. A circuit as claimed in any one of claims 1 to 4, wherein all of said transistors are substantially the same size MOS transistors.
6. The circuit according to any one of claims 1 to 5, adapted for use in a gain controlled amplifier, or a gain controlled attenuator, or in an automatic gain control system.
7. A gain control circuit comprising: a 1 st transistor having a 1 st terminal connected to the 1 st terminal serving as the output of the cell, a 2 nd terminal connected to ground, and a base connected to the input serving as the input of the cell; an operating circuit comprising an AGC current source for adjusting gain used as an input current to the circuit and a DC bias current source for supplying a DC bias to said 1 st transistor, said AGC current source and said DC bias current source both being connected to said base of said 1 st transistor such that the DC bias is independent of input current gain variations, and wherein said operating circuit comprises a 1 st pair of series connected transistors having a 1 st junction connected therebetween to said base of said 1 st transistor; the 2 nd pair of series connected transistors is connected to the DC bias current source, the AGC current source is connected to the 2 nd junction between the 2 nd pair of transistors, and the base of one of the 2 nd pair of transistors is connected to the base of the 1 st tube of the 1 st pair of transistors.
8. The circuit of claim 7 wherein said operating circuit includes a 6 th transistor connected to said AGC current source and having its base connected to the base of the 2 nd transistor of said 1 st pair of transistors.
9. A method of controlling current gain, comprising the steps of: supplying an input current to a base of a 1 st transistor having a 1 st terminal for providing an output current whose gain is controlled and a 2 nd terminal connected to ground; providing (i) an AGC current for adjusting an output current gain and (ii) a DC bias current to the base of the 1 st transistor through a multi-transistor circuit such that the DC bias is independent of variations in the output current gain, comprising the steps of connecting a 1 st junction between the 1 st pair of series connected transistors to the base of the 1 st transistor; connecting the AGC current to a 2 nd junction connected between a DC biased 2 nd pair of series connected transistors, wherein a base of one of the 2 nd pair of transistors is connected to a base of a 1 st tube of the 1 st pair of transistors; and connecting the AGC current to a 6 th transistor having its base connected to the base of the 2 nd transistor of the 1 st pair of transistors.
10. The method of claim 9, comprising the steps of: supplying an output current to a base of a 2 nd transistor and the transistor having a 1 st terminal for supplying a 2 nd output current whose gain is controlled and a 2 nd terminal connected to ground, supplying an output current to a base of the 2 nd transistor and the transistor having a 1 st terminal for supplying a 2 nd output current whose gain is controlled and a 2 nd terminal connected to ground; and providing (i) a 2 nd AGC current for adjusting a 2 nd output current gain and (ii) a DC bias current to the base of the 2 nd transistor such that the DC bias is independent of 2 nd output current gain variations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 97120402 CN1179033A (en) | 1996-10-04 | 1997-09-29 | Gain control circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US725,924 | 1996-10-04 | ||
| CN 97120402 CN1179033A (en) | 1996-10-04 | 1997-09-29 | Gain control circuit and method |
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| CN1179033A true CN1179033A (en) | 1998-04-15 |
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| CN 97120402 Pending CN1179033A (en) | 1996-10-04 | 1997-09-29 | Gain control circuit and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1739236B (en) * | 2003-01-20 | 2010-05-05 | 日本电气株式会社 | Gain variable voltage/current conversion circuit and filter circuit using the same |
| CN1985438B (en) * | 2004-05-17 | 2011-01-19 | Nxp股份有限公司 | Plop noise avoiding method and apparatus for an amplifier |
-
1997
- 1997-09-29 CN CN 97120402 patent/CN1179033A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1739236B (en) * | 2003-01-20 | 2010-05-05 | 日本电气株式会社 | Gain variable voltage/current conversion circuit and filter circuit using the same |
| CN1985438B (en) * | 2004-05-17 | 2011-01-19 | Nxp股份有限公司 | Plop noise avoiding method and apparatus for an amplifier |
| US8139786B2 (en) | 2004-05-17 | 2012-03-20 | Nxp B.V. | Plop noise avoidance for an amplifier |
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