CN117792338B - Filter and design method thereof - Google Patents
Filter and design method thereof Download PDFInfo
- Publication number
- CN117792338B CN117792338B CN202410211815.8A CN202410211815A CN117792338B CN 117792338 B CN117792338 B CN 117792338B CN 202410211815 A CN202410211815 A CN 202410211815A CN 117792338 B CN117792338 B CN 117792338B
- Authority
- CN
- China
- Prior art keywords
- filter
- sequence
- output signal
- formula
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000013461 design Methods 0.000 title claims abstract description 14
- 238000001914 filtration Methods 0.000 claims abstract description 15
- 239000011159 matrix material Substances 0.000 claims abstract description 14
- 238000004364 calculation method Methods 0.000 claims abstract description 5
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000000737 periodic effect Effects 0.000 claims description 7
- 108010076504 Protein Sorting Signals Proteins 0.000 claims description 4
- 238000009795 derivation Methods 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims description 3
- 238000006467 substitution reaction Methods 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 238000004891 communication Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention relates to the technical field of communication, and discloses a filter and a design method thereof, wherein the filter comprises the following components: setting complex signals and the first complex signals to perform IQ exchange to obtain second complex signals and constructing a conditional expression, establishing a main bandwidth frequency shift expression based on the conditional expression and the first input signals to obtain output signals after main bandwidth frequency shift, and forming second input signals by the output signals after main bandwidth frequency shift; constructing a formula of a main bandwidth filter output signal according to the second input signal and the set filter coefficient and converting the formula into a matrix form; the sequence of the second input signal is correspondingly converted and then substituted into a formula of a main bandwidth filter output signal in a matrix form, and the main bandwidth filtered output signal is obtained through calculation; and multiplexing the sequence of the formed second input signal to obtain an output signal after auxiliary bandwidth filtering. The invention saves logic design resources, effectively reduces the power consumption of the FPGA or the chip, and can be applied to transceivers supporting WiFi protocols.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a filter and a design method thereof.
Background
The WiFi receiver needs to flexibly receive signals with different bandwidths to perform signal detection, 2 frequency shifters, 2 filters and 2 downsamplers respectively complete the frequency shifting, filtering and downsampling functions of the main bandwidth/the auxiliary bandwidth, occupy more logic processing resources and increase the power consumption of equipment. Taking a 40M cell as an example, it is necessary to detect both the primary and secondary bandwidth signals. The digital receive path thus needs to support both the outputs of the primary 20 and secondary 20, and 2 digital filters are needed to complete the corresponding filtering in the DFE section. For the above-mentioned requirements, 1 filter resource can be reduced by the present invention, and only 1 filter is used to output the primary 20 and secondary 20 signals simultaneously.
Meanwhile, the method is not only suitable for the scenes of the main and auxiliary bandwidths, but also suitable for the scenes of the main and auxiliary 40M, the main and auxiliary 80M and the main and auxiliary 160M, and the communication application scenes of non-WiFi protocols.
Disclosure of Invention
Aiming at the technical defects, the invention aims to provide a filter and a design method thereof, and aims to solve the problem that the existing wifi receiver occupies more logic processing resources to cause high equipment power consumption.
In order to solve the technical problems, the invention adopts the following technical scheme: a method of designing a filter, comprising the steps of:
Setting a complex signal sampled by an analog-to-digital converter and the first complex signal to perform IQ exchange to obtain a second complex signal, constructing a conditional expression according to the second complex signal, establishing a main bandwidth frequency shift formula based on the conditional expression and the first input signal to obtain an output signal after main bandwidth frequency shift, and forming a second input signal by the output signal after main bandwidth frequency shift;
Constructing a formula of a main bandwidth filter output signal according to the second input signal and the set filter coefficient and converting the formula of the main bandwidth filter output signal into a formula of a matrix-form main bandwidth filter output signal formed by a sequence of the second input signal and a sequence of the filter coefficient;
Setting a relation formula which meets the coefficient order of the filter, correspondingly converting the sequence of the second input signal based on the condition formula, substituting the sequence into a formula of a main bandwidth filter output signal in a matrix form, and performing degeneracy calculation to obtain a filtered output signal of a main bandwidth 0 phase and a filtered output signal of a main bandwidth 2 phase; and meanwhile, multiplexing the sequence of the formed second input signal to obtain output signals with auxiliary bandwidth 0 phase and 2 phase after filtering.
Further, a complex signal sampled by an analog-to-digital converter is setAnd sum the complex signal and the first complex/>The IQ exchange is completed through multiplication to obtain a second complex number, and meanwhile signs of imaginary parts of the second complex number are inverted, and a conditional expression is constructed as follows:
The main bandwidth frequency shift formula is established as follows:
Wherein, For input signal,/>Is the output signal after frequency shift,/>Periodic signal of period 4；
Further, the order of the filter coefficients is set to be P, which is an odd number andThe relationship that P satisfies is as follows:
the derivation result M is obtained by upward rounding according to the relation formula satisfied by P as follows:
Where mod is the congruence symbol, For P to 4, floor is rounded up, and M is the derived result indicating that P is M times 4.
Further, the output signal of the filter is constructedThe formula is as follows:
Order the And according to/>And/>Are all the sequence numbers of the output signals of the filter, will/>Substitution to/>The following formula is obtained:
Wherein, =/>Is a coefficient of the filter and is symmetrical about the center tap;
output signal of filter The formula is represented in matrix form.
Further, mod (P-1, 4) =2 is obtained from the relation satisfied by P, and then P-1=4k+2 is used to represent an integer multiple of 4, then,/>At the same time/>Is a periodic function with period 4 and is derived from the relationship that P ultimately satisfies/>Formula/>, substituted into matrix form of output signal of main bandwidth filterThe formula of the filtered output signal as the phase of the main bandwidth 0 after the first simplification is as follows:
Wherein, the upper mark n is the initial phase, A second input signal sequence consisting of the output signal of the phase 0 after the main bandwidth shift, C being the sequence of filter coefficients.
Further, the performing corresponding conversion on the sequence of the second input signals based on the conditional expression includes:
Serial-parallel conversion is carried out on the sequence of the second input signal, the sequence is divided into an even-path sequence x (2 n) and an odd-path sequence x (2n+1), and the even-path sequence x (2 n) is directly assigned to an even-path sequence xc_even of the first sequence xc; IQ exchange is carried out on the odd-way sequence x (2n+1), meanwhile, the I-way symbol is reversely assigned to the odd-way sequence xc_odd of the first sequence xc, and a specific formula is obtained as follows:
xc_even = x(2n)
xc_odd = imag(x(2n+1)) –1jreal(x(2n+1))
Wherein even path is even path, odd path is odd path, imag () is imaginary function, real () is real function;
The filtered output signal formula of the main bandwidth 0 phase is simplified for the second time into the following formula:
。
further, according to the relation that the main bandwidth 0 phase and the 2 phase are 2 beats of delay, the initial phase n in the filtered output signal formula of the main bandwidth 0 phase after the first simplification is replaced by the initial phase n+2, and the second simplification is performed to obtain the output signal formula of the main bandwidth 2 phase after the second simplification as follows:
Wherein, A sequence of a further second input signal consisting of the output signal of 2 phases after the main bandwidth shift.
Further, the sequence of the second input signal after the primary bandwidth conversion is inverted, and the output signal after the primary bandwidth 0 phase and the output signal after the 2 phase filtration is inverted, so as to obtain the output signal after the secondary bandwidth 0 phase and the output signal after the 2 phase filtration.
A filter is designed by adopting a filter design method.
Further, it is composed of one (P-1)/2 multipliers, where P is the order of the filter.
The invention has the beneficial effects that: logic design resources can be saved, and power consumption of the FPGA or the chip can be reduced. Assuming that the order of the filters is P, each filter needs (P-1)/2 multipliers, and two groups of filters need P-1 multipliers in total; after the technology of the invention is adopted, only (P-1)/2 multipliers are needed, and 50% of multiplier resources can be saved; the invention utilizes 1 multiply-accumulate filter structure, the effect is equivalent to the frequency shift of the main bandwidth/auxiliary bandwidth, the filtering and downsampling functions of 2 frequency shifters, 2 filters and 2 downsamplers, not only effectively saves logic processing resources, but also reduces equipment power consumption, and can be applied to transceivers supporting WiFi protocols.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a filter according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an even-path sequence filtering structure.
Fig. 3 is a schematic diagram of an odd-order filtering structure.
Fig. 4 is a schematic diagram of an addition structure.
Fig. 5 is a diagram of a digital reception path of a conventional Wi-Fi receiver when detecting a 40M cell signal.
Fig. 6 is a diagram of a digital reception path of a Wi-Fi receiver according to the present invention when detecting a 40M cell signal.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the present invention provides a filter design method, which is characterized by comprising the following steps:
Setting a complex signal sampled by an analog-to-digital converter and the first complex signal to perform IQ exchange to obtain a second complex signal, constructing a conditional expression according to the second complex signal, establishing a main bandwidth frequency shift formula based on the conditional expression and the first input signal to obtain an output signal after main bandwidth frequency shift, and forming a second input signal by the output signal after main bandwidth frequency shift;
Constructing a formula of a main bandwidth filter output signal according to the second input signal and the set filter coefficient and converting the formula of the main bandwidth filter output signal into a formula of the main bandwidth filter output signal in a matrix form formed by a sequence of the second input signal and a sequence of the filter coefficient;
Setting a relation formula which meets the coefficient order of the filter, correspondingly converting the sequence of the second input signal based on the conditional formula, substituting the sequence into a formula of a main bandwidth filter output signal in a matrix form, and performing degenerate calculation to obtain a filtered output signal of a main bandwidth 0 phase and a main bandwidth 2 phase; and meanwhile, multiplexing the sequence of the formed second input signal to obtain output signals with auxiliary bandwidth 0 phase and 2 phase after filtering.
In this embodiment, taking the main 20M as an example, the specific filter design method is as follows:
In the receiver, the analog signal is converted into 2 paths of orthogonal analog signals after passing through the orthogonal demodulator and then sent to the analog-to-digital converter, and the digital signals obtained after sampling by the analog-to-digital converter are set, so that the complex signals obtained after sampling by the analog-to-digital converter are subjected to IQ exchange to obtain new complex numbers, a conditional expression is constructed according to the new complex numbers, a main 20M frequency shift formula is established based on the conditional expression and the input signals to obtain output signals after main 20M frequency shift, and the output signals after main 20M frequency shift form a second input signal.
Further, a complex signal sampled by an analog-to-digital converter is setAnd sum the complex signal and the first complex/>The IQ exchange is completed through multiplication to obtain a second complex number, and meanwhile signs of imaginary parts of the second complex number are inverted, and a conditional expression is constructed as follows:
The main bandwidth frequency shift formula is established as follows:
Wherein, For input signal,/>Is the output signal after frequency shift,/>Periodic signal of period 41J is a conventional imaginary expression in mathematics. Further, the order of the filter coefficients is set to P, which is an odd number and/>The relationship that P satisfies is as follows:
the derivation result M is obtained by upward rounding according to the relation formula satisfied by P as follows:
Wherein, among them, For P to 4, floor is rounded up, and M is the derived result indicating that P is M times 4.
It should be noted that the formula of the main 20M filter output signal is constructed from the second input signal and the set filter coefficients and is converted into the formula of the main 20M filter output signal in the form of a matrix made up of the sequence of the second input signal and the sequence of the filter coefficients.
Further, the output signal of the filter is constructedThe formula is as follows:
wherein n is a digital signal sequence, the output signal of the filter The formula is a general fir filter expression formula;
to facilitate deriving commands And according to/>And/>Are all the sequence numbers of the output signals of the filter, will/>Substitution to/>The following formula is obtained:
Wherein, =/>Is a coefficient of the filter and is symmetrical about the center tap;
output signal of filter The formula is expressed in matrix form as follows:
it should be noted that, a relational expression satisfying the filter coefficient order is set, and based on the conditional expression, the sequence of the second input signal is correspondingly converted and substituted into the formula of the output signal of the main 20M filter in the matrix form, and the filtered output signals of the 0 phase and the 2 phase of the main 20M are obtained by performing degenerate calculation.
Further, mod (P-1, 4) =2 is obtained from the relation satisfied by P, and then P-1=4k+2 is used to represent an integer multiple of 4, then,/>At the same time/>Is a periodic function with period 4 and is derived from the relationship that P ultimately satisfies/>Formula/>, substituted into matrix form of output signal of main 20M filterThe formula of the filtered output signal of 0 phase, which is the main 20M after the first reduction, is as follows:
Wherein, the upper mark n is the initial phase, A second input signal sequence consisting of the output signal of the phase 0 after the main bandwidth shift, C being the sequence of filter coefficients.
As shown in fig. 2 and 3, the corresponding conversion of the sequence of the second output signals based on the conditional expression includes:
Serial-parallel conversion is carried out on the new input sequence, the new input sequence is divided into an even-path sequence x (2 n) and an odd-path sequence x (2n+1), and the even-path sequence x (2 n) is directly assigned to an even-path sequence xc_even of the first sequence xc; IQ exchange is carried out on the odd-way sequence x (2n+1), meanwhile, the I-way symbol is reversely assigned to the odd-way sequence xc_odd of the first sequence xc, and a specific formula is obtained as follows:
xc_even = x(2n)
xc_odd = imag(x(2n+1)) –1jreal(x(2n+1))
Wherein even path is even path, odd path is odd path, imag () is imaginary function, real () is real function;
The filtered output signal equation for phase 0 of the main 20M is reduced for the second time to the following equation:
for convenience of expression, the following sequences are defined The following are provided:
As shown in fig. 2 and 3, the following simplification is further performed:
Wherein k= (1-P)/2.
The definition is as follows:
The following simplification is further carried out:
Further, as shown in fig. 4, according to the relationship that the 0 phase and the 2 phase of the main 20M are 2 beats of delay, the sign bits of the 0 phase and the 2 phase of the main 20M divided by the filtering result are inverted, and the filtering structures are identical; therefore, the primary phase n in the filtered output signal formula of the 0 phase of the main unit 20M after the first reduction is replaced by the primary phase n+2, and the 2-phase filtered output signal formula of the main unit 20M after the second reduction is obtained as follows:
Wherein, A sequence of a further second input signal consisting of the output signal of 2 phases after the main bandwidth shift.
It should be noted that, as shown in fig. 4, cnt is the output of the 1bit counter, 1 is added to each clock, and the output result is 01, which is alternatively negative: assuming that one number is x, taking the negative number to represent-x; and the sequence of the second input signal converted by the main 20M is subjected to the opposite number, and the output signal filtered by the main 20M 0 phase and the 2 phase is subjected to the opposite number, so that the output signal filtered by the auxiliary 20M 0 phase and the 2 phase is obtained.
The formula for the auxiliary 20M frequency shift is as follows:
Wherein, Is an output signal after 20M frequency shift.
The above can be simplified into:
Wherein, Periodic signal with period 4/>(1 J is a conventional imaginary expression in mathematics,/>Is a signal with period 4/>）；
Since the even-way data of y1 (n) is the same as the even-way data of y (n), the odd-way data of y1 (n) is the opposite number of the odd-way data of y (n); can be conveniently obtained, and the filtering structure of the multiplexing main 20M is used for filtering, and only theAndThe 2 phases and 0 phases of output signals of the auxiliary 20M can be obtained by adding after the opposite numbers are taken:
The 0-phase filtered output signal of the secondary 20M is as follows:
the 2-phase filtered output signal of the secondary 20M is as follows:
。
Example 2
Based on the filter design method provided in embodiment 1, this embodiment provides a filter of the filter design method.
The present embodiment provides a filter of a filter design method, which is composed of a (P-1)/2 multipliers, where P is the order of the filter, as shown in fig. 5, and there are 2 frequency shifters, 2 filters, and 2 downsamplers in the conventional scheme, as shown in fig. 6, where downsampling is completed when deriving the 0 phase and the 2 phases in embodiment 1, and the 1 phase and the 3 phases do not need to be calculated, so that the downsamplers are omitted. The present embodiment utilizes a1 multiply-accumulate filter structure to achieve an effect equivalent to the function of 2 frequency shifters, 2 filters, 2 downsamplers.
The foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A method of designing a filter, comprising the steps of:
Setting a complex signal sampled by an analog-to-digital converter and the first complex signal to perform IQ exchange to obtain a second complex signal, constructing a conditional expression according to the second complex signal, establishing a main bandwidth frequency shift formula based on the conditional expression and the first input signal to obtain an output signal after main bandwidth frequency shift, and forming a second input signal by the output signal after main bandwidth frequency shift;
Constructing a formula of a main bandwidth filter output signal according to the second input signal and the set filter coefficient and converting the formula of the main bandwidth filter output signal into a formula of a matrix-form main bandwidth filter output signal formed by a sequence of the second input signal and a sequence of the filter coefficient;
Setting a relation formula which meets the coefficient order of the filter, correspondingly converting the sequence of the second input signal based on the condition formula, substituting the sequence into a formula of a main bandwidth filter output signal in a matrix form, and performing degeneracy calculation to obtain a filtered output signal of a main bandwidth 0 phase and a filtered output signal of a main bandwidth 2 phase;
the corresponding conversion of the sequence of second input signals based on the conditional expression comprises:
Serial-parallel conversion is carried out on the sequence of the second input signal, the sequence is divided into an even-path sequence x (2 n) and an odd-path sequence x (2n+1), and the even-path sequence x (2 n) is directly assigned to an even-path sequence xc_even of the first sequence xc; IQ exchange is carried out on the odd-way sequence x (2n+1), meanwhile, the I-way symbol is reversely assigned to the odd-way sequence xc_odd of the first sequence xc, and a specific formula is obtained as follows:
xc_even = x(2n)
xc_odd = imag(x(2n+1)) –1jreal(x(2n+1))
Wherein even path is even path, odd path is odd path, imag () is imaginary function, real () is real function;
The filtered output signal formula of the main bandwidth 0 phase is simplified for the second time into the following formula:
；
And meanwhile, multiplexing the sequence of the formed second input signal to obtain output signals with auxiliary bandwidth 0 phase and 2 phase after filtering.
2. A method of designing a filter according to claim 1, wherein a complex signal obtained by sampling an analog-to-digital converter is setAnd sum the complex signal and the first complex/>The IQ exchange is completed through multiplication to obtain a second complex number, and meanwhile signs of imaginary parts of the second complex number are inverted, and a conditional expression is constructed as follows:
The main bandwidth frequency shift formula is established as follows:
Wherein, For input signal,/>Is the output signal after frequency shift,/>Periodic signal of period 4。
3. The method of claim 1, wherein the order of the filter coefficients is set to be P, P is an odd number andThe relationship that P satisfies is as follows:
the derivation result M is obtained by upward rounding according to the relation formula satisfied by P as follows:
Where mod is the congruence symbol, For P to 4, floor is rounded up, and M is the derived result indicating that P is M times 4.
4. A method of designing a filter according to claim 1, wherein the output signal of the filter is constructedThe formula is as follows:
Order the And according to/>And/>Are all the sequence numbers of the output signals of the filter, will/>Substitution to/>The following formula is obtained:
Wherein, =/>Is a coefficient of the filter and is symmetrical about the center tap;
output signal of filter The formula is represented in matrix form.
5. A filter design method as claimed in claim 3, characterized in that mod (P-1, 4) =2 is obtained from the relation satisfied by P, and P-1=4k+2 is used to represent an integer multiple of 4, then,At the same time/>Is a periodic function with period 4 and is derived from the relationship that P ultimately satisfies/>Formula/>, substituted into matrix form of output signal of main bandwidth filterThe formula of the filtered output signal as the phase of the main bandwidth 0 after the first simplification is as follows:
Wherein, the upper mark n is the initial phase, A second input signal sequence consisting of the output signal of the phase 0 after the main bandwidth shift, C being the sequence of filter coefficients.
6. The method for designing a filter according to any one of claims 1 and 5, wherein the primary phase n in the filtered output signal equation of the primary bandwidth 0 phase after the first reduction is replaced by the primary phase n+2 according to the relationship that the primary bandwidth 0 phase and the primary bandwidth 2 phase are 2-beat delays, and the second reduction is performed to obtain the filtered output signal equation of the primary bandwidth 2 phase as follows:
Wherein, A sequence of a further second input signal consisting of the output signal of 2 phases after the main bandwidth shift.
7. A method of designing a filter as claimed in claim 1, characterized in that the sequence of the primary bandwidth converted second input signal is inverted and the primary bandwidth 0 phase and 2 phase filtered output signal is inverted to obtain the secondary bandwidth 0 phase and 2 phase filtered output signal.
8. A filter designed by the method for designing a filter according to any one of claims 1 to 7.
9. A filter as claimed in claim 8, comprising a (P-1)/2 multipliers, wherein P is the order of the filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410211815.8A CN117792338B (en) | 2024-02-27 | 2024-02-27 | Filter and design method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410211815.8A CN117792338B (en) | 2024-02-27 | 2024-02-27 | Filter and design method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117792338A CN117792338A (en) | 2024-03-29 |
| CN117792338B true CN117792338B (en) | 2024-06-21 |
Family
ID=90389542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410211815.8A Active CN117792338B (en) | 2024-02-27 | 2024-02-27 | Filter and design method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117792338B (en) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640416A (en) * | 1995-06-07 | 1997-06-17 | Comsat Corporation | Digital downconverter/despreader for direct sequence spread spectrum communications system |
| JP2000174591A (en) * | 1998-12-02 | 2000-06-23 | Furuno Electric Co Ltd | Filtering device and signal processing method |
| CN101316102A (en) * | 2007-05-28 | 2008-12-03 | 安凡微电子(上海)有限公司 | Wave filter for digital baseband receiver and design method thereof |
| US8233524B2 (en) * | 2009-03-12 | 2012-07-31 | Freescale Semiconductor, Inc. | Radio transmitter IQ imbalance measurement and correction methods and apparatus |
| CN106302300B (en) * | 2015-06-24 | 2020-07-31 | 北京三星通信技术研究有限公司 | Method and device for transmitting and receiving signals based on filter bank multi-carrier system |
| CN109327203B (en) * | 2018-11-29 | 2022-03-01 | 西安恒盛安信智能技术有限公司 | Digital down-conversion method based on secondary symmetric filtering |
| DE112018008226T5 (en) * | 2018-12-28 | 2021-09-09 | Intel Corporation | RADIO DESIGN, CONTROL AND ARCHITECTURE |
| CN113962147A (en) * | 2021-10-14 | 2022-01-21 | 西北大学 | Construction system and method of wide area communication-oriented backscatter low-power-consumption communication network |
| CN115343366A (en) * | 2022-09-07 | 2022-11-15 | 邓军明 | Bridge structure monitoring system based on acoustic emission technology |
| CN115996162A (en) * | 2022-11-23 | 2023-04-21 | 中国电子科技集团公司第五十四研究所 | Time domain O & M timing synchronization method for serial high-efficiency communication |
| CN116707666B (en) * | 2023-05-30 | 2024-04-05 | 南京朗立微集成电路有限公司 | Method and equipment for correcting IQ imbalance of WiFi transmitter |
| CN116582149B (en) * | 2023-07-11 | 2023-10-13 | 南京朗立微集成电路有限公司 | Radio frequency TRX intermediate frequency filter multiplexing circuit and WiFi radio frequency chip |
-
2024
- 2024-02-27 CN CN202410211815.8A patent/CN117792338B/en active Active
Non-Patent Citations (2)
| Title |
|---|
| High-performance FPGA filters using sigma-delta modulation encoding;C. Dick 等;《1999 IEEE International Conference on Acoustics, Speech, and Signal Processing, Proceedings》;20020806;2123-2126 * |
| 基于FPGA的高速FIR滤波器并行结构设计;骆希;陶伟;黄荣鑫;;微处理机(第01期);9-12 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117792338A (en) | 2024-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102346245B (en) | Digital down-conversion method of broadband IF (intermediate frequency) signals | |
| CN108183877B (en) | Multi-tone frequency modulation signal demodulation method based on FPGA | |
| CN111510110B (en) | Interpolation matched filtering method and filter for parallel processing | |
| CN106130507B (en) | High-speed parallel bit synchronization filter time-varying coefficient updates loop | |
| CN117792338B (en) | Filter and design method thereof | |
| CN102347768B (en) | Conversion equipment of digital sampling rate and method thereof | |
| EP1388942B1 (en) | Conversion circuit, tuner and demodulator | |
| CN102638269A (en) | Multiphase frequency conversion circuit | |
| CN109818616A (en) | A kind of ADC harmonic level reduction system and method based on digital canceller | |
| CN101610077A (en) | A kind of half-band filter implementation method | |
| CN101917376B (en) | Two-stage frequency conversion method for digital down conversion system in multi-carrier digital receiver | |
| CN108696464B (en) | IQ and 4-channel TIADC combined distortion blind estimation and correction method | |
| CN109787648A (en) | A kind of ADC harmonic level reduction system and method based on digital phase shift synthesis | |
| CN102685055A (en) | Multi-data stream interpolation and extraction multiplexing device and method | |
| CN100455006C (en) | Frequency variation multiple stage filtering method used in ATSC high resolution digital TV | |
| CN215499016U (en) | Zero-frequency error digital baseband signal processing device for wireless repeater | |
| CN110808713A (en) | FPGA-based multi-path parallel demodulation method for ultra-high-speed frequency division signals | |
| JP3893078B2 (en) | Multichannel receiver | |
| CN103066949B (en) | A kind of multi-channel comb filter | |
| CN114584109B (en) | Method for real-time filtering parallel signals transmitted by high-speed serial interface | |
| TW201919344A (en) | Signal receiving apparatus and signal processing method thereof | |
| US7266161B1 (en) | Efficient method and apparatus for parallel processing for use with high-speed single-bit sampling | |
| WO2012151783A1 (en) | Double frequency conversion modulation system and frequency conversion method | |
| CN109120241B (en) | Real number cross type complex coefficient FIR filter | |
| CN117478155A (en) | Broadband signal extraction method and system based on multiphase filtering |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |