CN117792137B - Model predictive control method for five-level HERIC active clamp inverter - Google Patents
Model predictive control method for five-level HERIC active clamp inverter Download PDFInfo
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Abstract
The application provides a model predictive control method and a system for a five-level HERIC active clamp inverter. The method comprises the following steps: at the moment of sampling k, performing on-line calculation and evaluation of an objective function g (k) on 9 voltage vectors of the inverter based on a desired voltage and bus voltage prediction model; selecting a voltage vector minimizing the objective function g (k) as a predicted voltage vector; the predicted voltage vector is used for the next switching cycle to control the active clamp inverter. The present application not only provides a high degree of dynamic response capability, but also accommodates the complexity of non-linear and time-varying systems by optimizing a limited number of switch states in each control period. The extremely short calculation time of the FCS-MPC is suitable for scenes with high real-time control requirements, and the FCS-MPC can effectively inhibit harmonic waves output by an inverter, improve the electric energy quality, and has the potential of multi-objective optimization while improving the stability and performance of a system.
Description
Technical Field
The application relates to the technical field of inverter control, in particular to a model predictive control method and a system for a five-level HERIC active clamp inverter.
Background
HERIC clamp inverter topology, a five level output voltage waveform is achieved. The number of output voltage levels can be increased by level shifting or PS-PWM techniques compared to the original three-level topology and sinusoidal bipolar modulation schemes. The requirements on the output filter size can be significantly reduced due to the increase in apparent output switching frequency.
PR (Proportional-reserve) control is a method for regulating the inverter output voltage and frequency. First, the inverter measures the real-time voltage and frequency of the grid through the sensor, and then sets the reference voltage and frequency values. PR control employs a PI controller in which the proportional part reduces the difference between the actual output and the reference value and the integral part reduces the static error of the system. Furthermore, the frequency control ensures that the output frequency of the inverter is synchronized with the grid frequency. By continuously measuring the parameters of the power grid and adjusting the parameters in real time, the inverter realizes the synchronization with the power grid, thereby maintaining the stability and reliability of the system.
MPCs can be divided into two classes: a Continuous Control Set (CCS) and a Finite Control Set (FCS). The CCS-MPC generates the desired output voltage or current by calculating a continuous control signal and driving the inverter through the modulator while generating a fixed switching frequency. However, when constraints are considered in a CCS-MPC, the online calculation is very computationally intensive. In contrast, FCS-MPC fully considers the discrete characteristics and system constraints of the inverter. Specifically, the FCS-MPC first establishes a discrete mathematical model of the system, predicts the future state with a fixed step size, calculates a cost function of the controlled object and the reference object in a limited switching state, and then determines the optimal switching state of the next control period acting on the inverter through online optimization. In recent years, many advanced FCS-MPC methods have been validated in two-level grid-tie and off-grid inverters. However, the application of the finite switch state model predictive control is mainly focused on inverters such as three-phase two-level inverters, three-phase three-level inverters and multi-phase multi-level inverters, and the research of the finite switch state model predictive control in single-phase inverters is relatively less.
The prior art has the defects that: the complexity of PR control strategies is relatively high, requires precise parameter adjustment, and may cause excessive overshoot under rapidly changing grid conditions. In addition, sensitivity to system parameters also needs to be comprehensively considered. Therefore, when PR control is applied, its advantages and disadvantages must be carefully balanced to ensure optimum system stability and power quality.
Disclosure of Invention
In view of the above, the present application aims to provide a model predictive control method and system for a five-level HERIC active clamp inverter, which can solve the existing problems in a targeted manner.
Based on the above object, the present application provides a model predictive control method for a five-level HERIC active clamp inverter, comprising:
at the moment of sampling k, performing on-line calculation and evaluation of an objective function g (k) on 9 voltage vectors of the inverter based on a desired voltage and bus voltage prediction model;
selecting a voltage vector minimizing the objective function g (k) as a predicted voltage vector;
The predicted voltage vector is used for the next switching cycle to control the active clamp inverter.
Based on the above object, the present application further provides a model predictive control system of a five-level HERIC active clamp inverter, comprising:
the objective function module is used for carrying out on-line calculation and evaluation of an objective function g (k) on 9 voltage vectors of the inverter based on the expected voltage and the bus voltage prediction model at the moment of sampling k;
A predicted voltage vector module for selecting a voltage vector that minimizes the objective function g (k) as a predicted voltage vector;
and the control module is used for using the predicted voltage vector for the next switching cycle and controlling the active clamp inverter.
Overall, the advantages of the application and the experience brought to the user are: in grid-connected inverter control, the finite switch state model predictive control exhibits excellent dynamic performance and adaptability. It not only provides a high degree of dynamic response capability, but also accommodates the complexity of non-linear and time-varying systems by optimizing a limited number of switch states per control period. The extremely short calculation time of the FCS-MPC is suitable for scenes with high real-time control requirements, and the FCS-MPC can effectively inhibit harmonic waves output by an inverter, improve the electric energy quality, and has the potential of multi-objective optimization while improving the stability and performance of a system.
Drawings
In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.
Fig. 1 shows a five level HERIC active clamp inverter topology of the present application.
FIG. 2 illustrates a finite switch state model predictive control diagram according to an embodiment of the application.
Fig. 3 is a schematic diagram of a five-level HERIC active clamp inverter finite switch state model predictive control strategy according to an embodiment of the application.
Fig. 4 shows a configuration diagram of a model predictive control system of a five-level HERIC active clamp inverter according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a storage medium according to an embodiment of the present application.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
Term interpretation:
Grid-connected inverter: grid-tied inverters are devices for converting direct current electrical energy into alternating current electrical energy and are connected to the power grid. Such inverters are commonly used in solar and wind power generation systems to convert the direct current generated by renewable energy sources into the alternating current required by the power grid. Grid-tied inverters need to have an efficient, reliable control system to ensure that they stably inject electrical energy into the grid.
Heric topology: compared with other types of inverters, the Heric (HIGHLY EFFICIENT AND reliable inverter concept) topology is added with a bypass structure independently, so that the defect of low power factor of the inverter is avoided, and the Heric (HIGHLY EFFICIENT AND reliable inverter concept) topology is widely applied to single-phase grid-connected systems.
Finite control set model predictive control (Finite Control Set Model Predictive Control, FCS-MPC): the FCS-MPC firstly establishes a discrete mathematical model of the system, then calculates a cost function in a limited switching state in a control period according to a control instruction and constraint conditions, and then determines the optimal switching state applied to the inverter at the next moment through on-line optimization. The FCS-MPC can fully take into account the nonlinear characteristics of the system, handle complex systems with multiple discrete states, and achieve multi-objective optimization.
A. model construction
The structure of the five-level HERIC active clamp inverter is shown in fig. 1. The system consists of a direct-current power supply, a five-level HERIC active clamp inverter and a filter circuit. The direct current power supply provides input power of the system, and the five-level HERIC active clamp inverter realizes direct current to alternating current conversion. Wherein u aN、ubN is the output voltage of the a-phase bridge arm and the b-phase bridge arm respectively, and i g is the output current of the inverter. V dc、Vp、Vn、Vg is a direct current bus, a positive bus voltage, a negative bus voltage and a power grid voltage respectively. i c1、ic2、io is the negative bus capacitance current, the positive bus capacitance current, and the bus midpoint current, respectively.
For the power switching tube of each bridge arm of the five-level HERIC active clamp inverter, "1" represents the power switching tube to be on and "0" represents the power switching tube to be off. Wherein the driving signals of the switching transistors S 1 and S 7 are complementary, the driving signals of the switching transistors S 2 and S 5 are complementary, the driving signals of the switching transistors S 3 and S 6 are complementary, and the driving signals of the switching transistors S 4 and S 8 are complementary. For the convenience of modeling, assuming that all switching components are ideal components, ignoring dead time, the inverter output end is connected with a power grid through a filter, and the five-level HERIC active clamp inverter circuit can be equivalent to a corresponding switching model.
TABLE 1 combinations of different switching devices and corresponding output voltages
Table 1 lists all switch states that produce a 5L output voltage using the proposed five-level HERIC active clamp inverter topology. The output switch state of the inverter is
Sj＝[S1 S2 S3 S4]T.#(1)
Where j=1, …,7.
The differential voltage developed between u aN and u bN represents the output voltage u out of the inverter, i.e
uout＝uaN-ubN.#(2)
The output voltage equation is
Wherein R is a filter resistor, and L is a filter inductor.
Assuming that the sampling period T s is relatively small, discretizing the formula (3) by a forward Euler formula to obtain
Then at time k+1 the inverter predicts current as
It is assumed that at time k+1, the inverter current reaches a given current, i.e
According to equation (6), the output reference voltage of the inverter is
Wherein five levels HERIC at time k+1 active clamp inverter current is givenCan be obtained from the reference current at time kReference current at time k-1And reference current at time k-2Obtained by linear interpolation
According to FIG. 1, the relationship between the bus capacitance current and the neutral point current is
io＝ic1-ic2.#(9)
According to the switching function and the output current of the inverter, the neutral point current of the inverter can be obtained as
io＝(S4-S1)ig+(S2-S3)ig.#(10)
B. DC side model
The DC bus capacitor voltage is
Discretizing the formula (11) to obtain
Wherein C 1 and C 2 are respectively a positive dc bus capacitor and a negative dc bus capacitor, which are equal in value.
From the formulae (9), (10) and (12): the neutral point voltage can be predicted by the switching function of the five-level HERIC active clamp inverter output and the inverter output current without measuring the inverter bus capacitance currents i c1 and i c2.
C. Constructing a predictive model
The application adopts a prediction model based on expected voltage and bus voltage to select an objective function g (k), wherein g (k) is
Lambda v is the voltage balance weight coefficient.
As can be seen from the combination of the formulas (9) and (12), the difference of the DC bus capacitance voltage can be expressed as
The inverter output voltage can be derived from the dc bus voltage and the inverter switching function:
uout(k)＝-Vp(k)(S1+S3)-Vn(k)(S2+S4)#(15)
A five-level HERIC active clamp inverter finite switch state model predictive control flow diagram is shown in figure 2,
Measuring an output current i g (k), a positive bus voltage V p (k), a negative bus voltage V n (k) and a grid voltage V g (k) of the inverter;
Calculating an inverter output reference voltage
V p(k+1)-Vn (k+1) and the output voltage u out (k) of the inverter are calculated from the switching state S 1、S2、S3、S4 of the inverter and the dc bus voltage.
At sampling time k, the objective function g (k) is calculated and evaluated on-line for 9 voltage vectors of the inverter, which voltage vector minimizes the objective function g (k), which voltage vector will be active in the next switching cycle.
Based on the above mathematical model and the control flow diagram of fig. 2, a five-level HERIC active clamp inverter finite switch state model predictive control strategy is shown in fig. 3.
The application embodiment provides a model predictive control system of a five-level HERIC active clamp inverter, which is used for executing the model predictive control method of the five-level HERIC active clamp inverter described in the above embodiment, as shown in fig. 4, and the system includes:
An objective function module 401, configured to perform on-line computation and evaluation of an objective function g (k) on 9 voltage vectors of the inverter based on the expected voltage and the bus voltage prediction model at the time of sampling k;
A predicted voltage vector module 402 for selecting a voltage vector that minimizes an objective function g (k) as a predicted voltage vector;
a control module 403 for using the predicted voltage vector for the next switching cycle, controls the active clamp inverter.
The model predictive control system of the five-level HERIC active clamp inverter provided by the embodiment of the application and the model predictive control method of the five-level HERIC active clamp inverter provided by the embodiment of the application have the same beneficial effects as the method adopted, operated or realized by the stored application program because of the same inventive concept.
The embodiment of the application also provides an electronic device corresponding to the model predictive control method of the five-level HERIC active clamp inverter provided by the previous embodiment, so as to execute the model predictive control method of the upper five-level HERIC active clamp inverter. The embodiment of the application is not limited.
Referring to fig. 5, a schematic diagram of an electronic device according to some embodiments of the present application is shown. As shown in fig. 5, the electronic device 20 includes: a processor 200, a memory 201, a bus 202 and a communication interface 203, the processor 200, the communication interface 203 and the memory 201 being connected by the bus 202; the memory 201 stores a computer program that can be run on the processor 200, and when the processor 200 runs the computer program, the model predictive control method of the five-level HERIC active clamp inverter provided by any one of the foregoing embodiments of the present application is executed.
The memory 201 may include a high-speed random access memory (RAM: random Access Memory), and may further include a non-volatile memory (non-volatile memory), such as at least one disk memory. The communication connection between the system network element and at least one other network element is implemented via at least one communication interface 203 (which may be wired or wireless), the internet, a wide area network, a local network, a metropolitan area network, etc. may be used.
Bus 202 may be an ISA bus, a PCI bus, an EISA bus, or the like. The buses may be classified as address buses, data buses, control buses, etc. The memory 201 is configured to store a program, and the processor 200 executes the program after receiving an execution instruction, and the model predictive control method of the five-level HERIC active clamp inverter disclosed in any of the foregoing embodiments of the present application may be applied to the processor 200 or implemented by the processor 200.
The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 200 or by instructions in the form of software. The processor 200 may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), etc.; but may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201, and in combination with its hardware, performs the steps of the above method.
The electronic equipment provided by the embodiment of the application and the model predictive control method of the five-level HERIC active clamp inverter provided by the embodiment of the application have the same beneficial effects as the method adopted, operated or realized by the same inventive concept.
The embodiment of the present application further provides a computer readable storage medium corresponding to the model predictive control method of the five-level HERIC active clamp inverter provided in the foregoing embodiment, referring to fig. 6, the computer readable storage medium is shown as an optical disc 30, on which a computer program (i.e. a program product) is stored, where the computer program, when executed by a processor, performs the model predictive control method of the five-level HERIC active clamp inverter provided in any of the foregoing embodiments.
It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical or magnetic storage medium, which will not be described in detail herein.
The computer readable storage medium provided by the above embodiment of the present application has the same beneficial effects as the method adopted, operated or implemented by the application program stored in the computer readable storage medium, because of the same inventive concept as the model predictive control method of the five-level HERIC active clamp inverter provided by the embodiment of the present application.
It should be noted that:
The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with the teachings herein. The required structure for a construction of such a system is apparent from the description above. In addition, the present application is not directed to any particular programming language. It will be appreciated that the teachings of the present application described herein may be implemented in a variety of programming languages, and the above description of specific languages is provided for disclosure of enablement and best mode of the present application.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the above description of exemplary embodiments of the application, various features of the application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed application requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
Various component embodiments of the application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that some or all of the functions of some or all of the components in a virtual machine creation system according to embodiments of the application may be implemented in practice using a microprocessor or Digital Signal Processor (DSP). The present application can also be implemented as an apparatus or system program (e.g., a computer program and a computer program product) for performing a portion or all of the methods described herein. Such a program embodying the present application may be stored on a computer readable medium, or may have the form of one or more signals. Such signals may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (6)
1. A model predictive control method of a five-level HERIC active clamp inverter is characterized by comprising the following steps:
At the moment of sampling k, performing on-line calculation and evaluation of an objective function g (k) on 9 voltage vectors of the active clamp inverter based on a desired voltage and bus voltage prediction model;
selecting a voltage vector minimizing the objective function g (k) as a predicted voltage vector;
using the predicted voltage vector for a next switching cycle to control the active clamp inverter;
Before the objective function is calculated online, further comprising: measuring an output current i g (k), a positive bus voltage V p (k), a negative bus voltage V n (k) and a grid voltage V g (k) of the active clamp inverter;
calculating an output reference voltage of an active clamp inverter
Calculating V p(k+1)-Vn (k+1) and output voltage u out (k) of the active clamp inverter according to the switching state S 1、S2、S3、S4 and the DC bus voltage of the active clamp inverter;
the output reference voltage of the inverter is
Wherein five levels HERIC at time k+1 active clamp inverter current is givenFrom reference current at time kReference current at time k-1And reference current at time k-2Obtained by linear interpolation; r is a filter resistor, L is a filter inductor, and T s is a sampling period.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The objective function g (k) is
Lambda v is the voltage balance weight coefficient.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The output voltage of the inverter is obtained by the DC bus voltage and an inverter switching function:
uout(k)＝-Vp(k)(S1+S3)-Vn(k)(S2+S4)。
4. A model predictive control system for a five level HERIC active clamp inverter using the method of any one of claims 1-3, comprising:
the objective function module is used for carrying out on-line calculation and evaluation of an objective function g (k) on 9 voltage vectors of the inverter based on the expected voltage and the bus voltage prediction model at the moment of sampling k;
A predicted voltage vector module for selecting a voltage vector that minimizes the objective function g (k) as a predicted voltage vector;
and the control module is used for using the predicted voltage vector for the next switching cycle and controlling the active clamp inverter.
5. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor runs the computer program to implement the method of any one of claims 1-3.
6. A computer readable storage medium having stored thereon a computer program, wherein the program is executed by a processor to implement the method of any of claims 1-3.
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